diff --git a/nongnu/configs/pinenote_config b/nongnu/configs/pinenote_config
new file mode 100644
index 0000000..95c693d
--- /dev/null
+++ b/nongnu/configs/pinenote_config
@@ -0,0 +1,5853 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 5.17.0-2 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.2.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=110200
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=23800
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=23800
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION="-danctnix"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_DEBUGFS=y
+# end of IRQ subsystem
+
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+# CONFIG_BPF_PRELOAD is not set
+# end of BPF subsystem
+
+CONFIG_PREEMPT_BUILD=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_SCHED_AVG_IRQ=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_PSI_DEFAULT_DISABLED=y
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=0
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_ARCH_SUPPORTS_INT128=y
+# CONFIG_NUMA_BALANCING is not set
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+# CONFIG_CGROUP_BPF is not set
+CONFIG_CGROUP_MISC=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_ZSTD=y
+# CONFIG_BOOT_CONFIG is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_USERFAULTFD=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+# CONFIG_DEBUG_RSEQ is not set
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_GUEST_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_SMP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+
+#
+# Platform selection
+#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_BCM2835 is not set
+# CONFIG_ARCH_BCM4908 is not set
+# CONFIG_ARCH_BCM_IPROC is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_S32 is not set
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# end of Platform selection
+
+#
+# Kernel Features
+#
+
+#
+# ARM errata workarounds via the alternatives framework
+#
+# CONFIG_ARM64_ERRATUM_826319 is not set
+# CONFIG_ARM64_ERRATUM_827319 is not set
+# CONFIG_ARM64_ERRATUM_824069 is not set
+# CONFIG_ARM64_ERRATUM_819472 is not set
+# CONFIG_ARM64_ERRATUM_832075 is not set
+CONFIG_ARM64_ERRATUM_834220=y
+# CONFIG_ARM64_ERRATUM_845719 is not set
+# CONFIG_ARM64_ERRATUM_843419 is not set
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+# CONFIG_ARM64_ERRATUM_1418040 is not set
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+# CONFIG_ARM64_ERRATUM_1165522 is not set
+# CONFIG_ARM64_ERRATUM_1319367 is not set
+CONFIG_ARM64_ERRATUM_1530923=y
+# CONFIG_ARM64_ERRATUM_1286807 is not set
+# CONFIG_ARM64_ERRATUM_1463225 is not set
+# CONFIG_ARM64_ERRATUM_1542419 is not set
+# CONFIG_ARM64_ERRATUM_1508412 is not set
+CONFIG_ARM64_ERRATUM_2051678=y
+# CONFIG_ARM64_ERRATUM_2077057 is not set
+# CONFIG_ARM64_ERRATUM_2054223 is not set
+# CONFIG_ARM64_ERRATUM_2067961 is not set
+# CONFIG_CAVIUM_ERRATUM_22375 is not set
+CONFIG_CAVIUM_ERRATUM_23144=y
+# CONFIG_CAVIUM_ERRATUM_23154 is not set
+# CONFIG_CAVIUM_ERRATUM_27456 is not set
+# CONFIG_CAVIUM_ERRATUM_30115 is not set
+# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
+# CONFIG_FUJITSU_ERRATUM_010001 is not set
+# CONFIG_HISILICON_ERRATUM_161600802 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
+# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
+# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
+# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
+# end of ARM errata workarounds via the alternatives framework
+
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+CONFIG_ARM64_VA_BITS_39=y
+# CONFIG_ARM64_VA_BITS_48 is not set
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SCHED_MC=y
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_NR_CPUS=64
+CONFIG_HOTPLUG_CPU=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=4
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_PARAVIRT=y
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_SIG is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
+CONFIG_COMPAT=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_ARMV8_DEPRECATED=y
+# CONFIG_SWP_EMULATION is not set
+CONFIG_CP15_BARRIER_EMULATION=y
+# CONFIG_SETEND_EMULATION is not set
+
+#
+# ARMv8.1 architectural features
+#
+# CONFIG_ARM64_HW_AFDBM is not set
+CONFIG_ARM64_PAN=y
+CONFIG_AS_HAS_LDAPR=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+# end of ARMv8.1 architectural features
+
+#
+# ARMv8.2 architectural features
+#
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
+# CONFIG_ARM64_PMEM is not set
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+# end of ARMv8.2 architectural features
+
+#
+# ARMv8.3 architectural features
+#
+# CONFIG_ARM64_PTR_AUTH is not set
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_AS_HAS_PAC=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+# end of ARMv8.3 architectural features
+
+#
+# ARMv8.4 architectural features
+#
+# CONFIG_ARM64_AMU_EXTN is not set
+CONFIG_AS_HAS_ARMV8_4=y
+# CONFIG_ARM64_TLB_RANGE is not set
+# end of ARMv8.4 architectural features
+
+#
+# ARMv8.5 architectural features
+#
+CONFIG_AS_HAS_ARMV8_5=y
+# CONFIG_ARM64_BTI is not set
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+# CONFIG_ARM64_E0PD is not set
+# CONFIG_ARCH_RANDOM is not set
+CONFIG_ARM64_AS_HAS_MTE=y
+# end of ARMv8.5 architectural features
+
+#
+# ARMv8.7 architectural features
+#
+# CONFIG_ARM64_EPAN is not set
+# end of ARMv8.7 architectural features
+
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_MODULE_PLTS=y
+# CONFIG_ARM64_PSEUDO_NMI is not set
+CONFIG_RELOCATABLE=y
+# CONFIG_RANDOMIZE_BASE is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+# end of Kernel Features
+
+#
+# Boot options
+#
+CONFIG_CMDLINE=""
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+CONFIG_DMI=y
+# end of Boot options
+
+CONFIG_SYSVIPC_COMPAT=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SUSPEND_SKIP_SYNC is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_PM_SLEEP_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_GOV_TEO=y
+CONFIG_DT_IDLE_STATES=y
+
+#
+# ARM CPU Idle Drivers
+#
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# end of ARM CPU Idle Drivers
+# end of CPU Idle
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+# CONFIG_ARM_SCMI_CPUFREQ is not set
+# end of CPU Frequency scaling
+# end of CPU Power Management
+
+CONFIG_ARCH_SUPPORTS_ACPI=y
+# CONFIG_ACPI is not set
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_KVM_MMIO=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=y
+# CONFIG_CRYPTO_SHA3_ARM64 is not set
+# CONFIG_CRYPTO_SM3_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE is not set
+# CONFIG_CRYPTO_GHASH_ARM64_CE is not set
+# CONFIG_CRYPTO_AES_ARM64 is not set
+CONFIG_CRYPTO_AES_ARM64_CE=y
+# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_POLY1305_NEON=m
+# CONFIG_CRYPTO_NHPOLY1305_NEON is not set
+# CONFIG_CRYPTO_AES_ARM64_BS is not set
+
+#
+# General architecture-dependent options
+#
+CONFIG_CRASH_CORE=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_HAS_RELR=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGINS is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ASM_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS_NONE is not set
+CONFIG_MODULE_COMPRESS_GZIP=y
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_DECOMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+# CONFIG_BLK_WBT is not set
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOPRIO=y
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_ASN1=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ELFCORE=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_COREDUMP is not set
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_COMPACTION=y
+# CONFIG_PAGE_REPORTING is not set
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU_NOTIFIER=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+# CONFIG_CMA is not set
+# CONFIG_ZSWAP is not set
+# CONFIG_ZPOOL is not set
+CONFIG_ZSMALLOC=m
+# CONFIG_ZSMALLOC_STAT is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+# CONFIG_ANON_VMA_NAME is not set
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_IPVTI is not set
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=m
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+# CONFIG_BT_BNEP is not set
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_LEDS=y
+# CONFIG_BT_MSFTEXT is not set
+# CONFIG_BT_AOSPEXT is not set
+CONFIG_BT_DEBUGFS=y
+# CONFIG_BT_SELFTEST is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_BCM=m
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_NOKIA is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIUART_3WIRE is not set
+# CONFIG_BT_HCIUART_INTEL is not set
+CONFIG_BT_HCIUART_BCM=y
+# CONFIG_BT_HCIUART_RTL is not set
+# CONFIG_BT_HCIUART_QCA is not set
+# CONFIG_BT_HCIUART_AG6XX is not set
+# CONFIG_BT_HCIUART_MRVL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_MTKSDIO is not set
+# CONFIG_BT_MTKUART is not set
+# end of Bluetooth device drivers
+
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_MCTP is not set
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_CERTIFICATION_ONUS=y
+# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set
+# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set
+# CONFIG_CFG80211_REG_RELAX_NO_IR is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT=""
+
+#
+# Some wireless drivers require a rate control algorithm
+#
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SELFTESTS=m
+CONFIG_NET_SOCK_MSG=y
+CONFIG_PAGE_POOL=y
+# CONFIG_FAILOVER is not set
+# CONFIG_ETHTOOL_NETLINK is not set
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+# CONFIG_PCI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_CACHE=y
+# end of Firmware loader
+
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=m
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_ARCH_NUMA=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_MHI_BUS is not set
+# end of Bus devices
+
+CONFIG_CONNECTOR=m
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SDE_INTERFACE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+# CONFIG_ARM_FFA_TRANSPORT is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_TEST is not set
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_EFI_EARLYCON=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+# CONFIG_ARM_SMCCC_SOC_ID is not set
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_NUMA=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+CONFIG_ZRAM=m
+# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
+CONFIG_ZRAM_DEF_COMP_ZSTD=y
+# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
+# CONFIG_ZRAM_DEF_COMP_LZO is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
+# CONFIG_ZRAM_DEF_COMP_842 is not set
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZRAM_WRITEBACK=y
+# CONFIG_ZRAM_MEMORY_TRACKING is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+# CONFIG_XEN_BLKDEV_BACKEND is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# NVME Support
+#
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_ECHO is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_UACCE is not set
+# CONFIG_PVPANIC is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# end of SCSI device support
+
+CONFIG_HAVE_PATA_PLATFORM=y
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+# CONFIG_MD_LINEAR is not set
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_BUFIO=m
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_PERSISTENT_DATA=m
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_EBS=m
+CONFIG_DM_ERA=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+# CONFIG_DM_INIT is not set
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_SWITCH=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_INTEGRITY=m
+CONFIG_DM_AUDIT=y
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=m
+CONFIG_NET_CORE=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+CONFIG_TUN=m
+CONFIG_TAP=m
+# CONFIG_TUN_VNET_CROSS_LE is not set
+CONFIG_VETH=m
+# CONFIG_NLMON is not set
+# CONFIG_ETHERNET is not set
+CONFIG_PHYLIB=m
+CONFIG_SWPHY=y
+# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=m
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+CONFIG_AX88796B_PHY=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_MICROCHIP_PHY=m
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+# CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_ROCKCHIP_PHY is not set
+CONFIG_SMSC_PHY=m
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_MDIO_DEVICE=m
+CONFIG_MDIO_BUS=m
+CONFIG_FWNODE_MDIO=m
+CONFIG_OF_MDIO=m
+CONFIG_MDIO_DEVRES=m
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+
+#
+# MDIO Multiplexers
+#
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+
+#
+# PCS device drivers
+#
+# CONFIG_PCS_XPCS is not set
+# end of PCS device drivers
+
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_WLAN=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+CONFIG_WLAN_VENDOR_BROADCOM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_BRCMUTIL=m
+# CONFIG_BRCMSMAC is not set
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+# CONFIG_BRCMFMAC_USB is not set
+# CONFIG_BRCM_TRACING is not set
+# CONFIG_BRCMDBG is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+CONFIG_XEN_NETDEV_FRONTEND=y
+# CONFIG_XEN_NETDEV_BACKEND is not set
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NET_FAILOVER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ADC=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ADC is not set
+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_BU21029 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
+# CONFIG_TOUCHSCREEN_EXC3000 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+# CONFIG_TOUCHSCREEN_HIDEEP is not set
+# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_ILITEK is not set
+# CONFIG_TOUCHSCREEN_S6SY761 is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_EKTF2127 is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
+# CONFIG_TOUCHSCREEN_MSG2638 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_RM_TS is not set
+# CONFIG_TOUCHSCREEN_SILEAD is not set
+# CONFIG_TOUCHSCREEN_SIS_I2C is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_STMFTS is not set
+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZET6223 is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
+# CONFIG_TOUCHSCREEN_IQS5XX is not set
+# CONFIG_TOUCHSCREEN_ZINITIX is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_PWM_VIBRA is not set
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_INPUT_WS8100_PEN=m
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_LDISC_AUTOLOAD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+# CONFIG_HVC_DCC is not set
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_DEVMEM=y
+# CONFIG_TCG_TPM is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+# end of I2C Algorithms
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CADENCE is not set
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_RK3X=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MEM is not set
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_ROCKCHIP is not set
+# CONFIG_SPI_ROCKCHIP_SFC is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+# CONFIG_SPI_MUX is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_DYNAMIC=y
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_RK805 is not set
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_CADENCE is not set
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_LOGICVC is not set
+# CONFIG_GPIO_MB86S7X is not set
+# CONFIG_GPIO_PL061 is not set
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SAMA5D2_PIOBU is not set
+# CONFIG_GPIO_SIFIVE is not set
+# CONFIG_GPIO_SYSCON is not set
+# CONFIG_GPIO_XGENE is not set
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCA9570 is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_TPIC2810 is not set
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+# end of MFD GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+# CONFIG_W1 is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_BRCMSTB is not set
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_XGENE is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+# CONFIG_SYSCON_REBOOT_MODE is not set
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_GENERIC_ADC_BATTERY is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_BQ256XX is not set
+CONFIG_CHARGER_RK817=y
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHARGER_BD99954 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+# CONFIG_SENSORS_ARM_SCMI is not set
+# CONFIG_SENSORS_ARM_SCPI is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FTSTEUTATES is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IIO_HWMON is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_PWM_FAN is not set
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_THERMAL_EMULATION=y
+# CONFIG_THERMAL_MMIO is not set
+CONFIG_ROCKCHIP_THERMAL=y
+# CONFIG_GENERIC_ADC_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG_SYSFS=y
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_GPIO_WATCHDOG is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_ARM_SBSA_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_MEN_A21_WDT is not set
+# CONFIG_XEN_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+CONFIG_MFD_RK808=y
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# CONFIG_MFD_KHADAS_MCU is not set
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+CONFIG_REGULATOR_FAN53555=y
+# CONFIG_REGULATOR_FAN53880 is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+# CONFIG_REGULATOR_PWM is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+CONFIG_REGULATOR_TPS65185=y
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_VCTRL is not set
+# CONFIG_RC_CORE is not set
+
+#
+# CEC support
+#
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=m
+# CONFIG_MEDIA_SUPPORT_FILTER is not set
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+# end of Media device types
+
+#
+# Media core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=m
+# end of Media core support
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+# CONFIG_V4L2_FLASH_LED_CLASS is not set
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+# CONFIG_MEDIA_CONTROLLER_DVB is not set
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+# CONFIG_DVB_MMAP is not set
+# CONFIG_DVB_NET is not set
+CONFIG_DVB_MAX_ADAPTERS=16
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+# CONFIG_SDR_PLATFORM_DRIVERS is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+# CONFIG_DVB_TEST_DRIVERS is not set
+# end of Media drivers
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA1997X is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS3308 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_UDA1342 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_SONY_BTF_MPX is not set
+# end of Audio decoders, processors and mixers
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+# end of RDS decoders
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_ADV748X is not set
+# CONFIG_VIDEO_ADV7604 is not set
+# CONFIG_VIDEO_ADV7842 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_ML86V7667 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_TC358743 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_TW2804 is not set
+# CONFIG_VIDEO_TW9903 is not set
+# CONFIG_VIDEO_TW9906 is not set
+# CONFIG_VIDEO_TW9910 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+# end of Video decoders
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_ADV7511 is not set
+# CONFIG_VIDEO_AD9389B is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_THS8200 is not set
+# end of Video encoders
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# end of Video improvement chips
+
+#
+# Audio/Video compression chips
+#
+# CONFIG_VIDEO_SAA6752HS is not set
+# end of Audio/Video compression chips
+
+#
+# SDR tuner chips
+#
+# CONFIG_SDR_MAX2175 is not set
+# end of SDR tuner chips
+
+#
+# Miscellaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_I2C is not set
+# CONFIG_VIDEO_ST_MIPID02 is not set
+# end of Miscellaneous helper chips
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
+# CONFIG_VIDEO_IMX208 is not set
+# CONFIG_VIDEO_IMX214 is not set
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_IMX258 is not set
+# CONFIG_VIDEO_IMX274 is not set
+# CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX319 is not set
+# CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
+# CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
+# CONFIG_VIDEO_OV02A10 is not set
+# CONFIG_VIDEO_OV2640 is not set
+# CONFIG_VIDEO_OV2659 is not set
+# CONFIG_VIDEO_OV2680 is not set
+# CONFIG_VIDEO_OV2685 is not set
+# CONFIG_VIDEO_OV5640 is not set
+# CONFIG_VIDEO_OV5645 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV5648 is not set
+# CONFIG_VIDEO_OV6650 is not set
+# CONFIG_VIDEO_OV5670 is not set
+# CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
+# CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV7251 is not set
+# CONFIG_VIDEO_OV772X is not set
+# CONFIG_VIDEO_OV7640 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_OV7740 is not set
+# CONFIG_VIDEO_OV8856 is not set
+# CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9282 is not set
+# CONFIG_VIDEO_OV9640 is not set
+# CONFIG_VIDEO_OV9650 is not set
+# CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_MT9M001 is not set
+# CONFIG_VIDEO_MT9M032 is not set
+# CONFIG_VIDEO_MT9M111 is not set
+# CONFIG_VIDEO_MT9P031 is not set
+# CONFIG_VIDEO_MT9T001 is not set
+# CONFIG_VIDEO_MT9T112 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_MT9V032 is not set
+# CONFIG_VIDEO_MT9V111 is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_M5MOLS is not set
+# CONFIG_VIDEO_RDACM20 is not set
+# CONFIG_VIDEO_RDACM21 is not set
+# CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_S5K6AA is not set
+# CONFIG_VIDEO_S5K6A3 is not set
+# CONFIG_VIDEO_S5K4ECGX is not set
+# CONFIG_VIDEO_S5K5BAF is not set
+# CONFIG_VIDEO_CCS is not set
+# CONFIG_VIDEO_ET8EK8 is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# end of Camera sensor devices
+
+#
+# Lens drivers
+#
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# end of Lens drivers
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# end of Flash devices
+
+#
+# SPI helper chips
+#
+# CONFIG_VIDEO_GS1662 is not set
+# end of SPI helper chips
+
+#
+# Media SPI Adapters
+#
+# CONFIG_CXD2880_SPI_DRV is not set
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=m
+
+#
+# Customize TV tuners
+#
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+# end of Customize TV tuners
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6100 is not set
+# CONFIG_DVB_STV090x is not set
+# CONFIG_DVB_STV0910 is not set
+# CONFIG_DVB_STV6110x is not set
+# CONFIG_DVB_STV6111 is not set
+# CONFIG_DVB_MXL5XX is not set
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+# CONFIG_DVB_DRXK is not set
+# CONFIG_DVB_TDA18271C2DD is not set
+# CONFIG_DVB_SI2165 is not set
+# CONFIG_DVB_MN88472 is not set
+# CONFIG_DVB_MN88473 is not set
+
+#
+# DVB-S (satellite) frontends
+#
+# CONFIG_DVB_CX24110 is not set
+# CONFIG_DVB_CX24123 is not set
+# CONFIG_DVB_MT312 is not set
+# CONFIG_DVB_ZL10036 is not set
+# CONFIG_DVB_ZL10039 is not set
+# CONFIG_DVB_S5H1420 is not set
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+# CONFIG_DVB_STV0299 is not set
+# CONFIG_DVB_STV6110 is not set
+# CONFIG_DVB_STV0900 is not set
+# CONFIG_DVB_TDA8083 is not set
+# CONFIG_DVB_TDA10086 is not set
+# CONFIG_DVB_TDA8261 is not set
+# CONFIG_DVB_VES1X93 is not set
+# CONFIG_DVB_TUNER_ITD1000 is not set
+# CONFIG_DVB_TUNER_CX24113 is not set
+# CONFIG_DVB_TDA826X is not set
+# CONFIG_DVB_TUA6100 is not set
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_CX24117 is not set
+# CONFIG_DVB_CX24120 is not set
+# CONFIG_DVB_SI21XX is not set
+# CONFIG_DVB_TS2020 is not set
+# CONFIG_DVB_DS3000 is not set
+# CONFIG_DVB_MB86A16 is not set
+# CONFIG_DVB_TDA10071 is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+# CONFIG_DVB_SP887X is not set
+# CONFIG_DVB_CX22700 is not set
+# CONFIG_DVB_CX22702 is not set
+# CONFIG_DVB_S5H1432 is not set
+# CONFIG_DVB_DRXD is not set
+# CONFIG_DVB_L64781 is not set
+# CONFIG_DVB_TDA1004X is not set
+# CONFIG_DVB_NXT6000 is not set
+# CONFIG_DVB_MT352 is not set
+# CONFIG_DVB_ZL10353 is not set
+# CONFIG_DVB_DIB3000MB is not set
+# CONFIG_DVB_DIB3000MC is not set
+# CONFIG_DVB_DIB7000M is not set
+# CONFIG_DVB_DIB7000P is not set
+# CONFIG_DVB_DIB9000 is not set
+# CONFIG_DVB_TDA10048 is not set
+# CONFIG_DVB_EC100 is not set
+# CONFIG_DVB_STV0367 is not set
+# CONFIG_DVB_CXD2820R is not set
+# CONFIG_DVB_CXD2841ER is not set
+# CONFIG_DVB_ZD1301_DEMOD is not set
+# CONFIG_DVB_CXD2880 is not set
+
+#
+# DVB-C (cable) frontends
+#
+# CONFIG_DVB_VES1820 is not set
+# CONFIG_DVB_TDA10021 is not set
+# CONFIG_DVB_TDA10023 is not set
+# CONFIG_DVB_STV0297 is not set
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+# CONFIG_DVB_NXT200X is not set
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+# CONFIG_DVB_BCM3510 is not set
+# CONFIG_DVB_LGDT330X is not set
+# CONFIG_DVB_LGDT3305 is not set
+# CONFIG_DVB_LG2160 is not set
+# CONFIG_DVB_S5H1409 is not set
+# CONFIG_DVB_AU8522_DTV is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_S5H1411 is not set
+# CONFIG_DVB_MXL692 is not set
+
+#
+# ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_S921 is not set
+# CONFIG_DVB_DIB8000 is not set
+# CONFIG_DVB_MB86A20S is not set
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_TC90522 is not set
+# CONFIG_DVB_MN88443X is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+# CONFIG_DVB_PLL is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+
+#
+# SEC control devices for DVB-S
+#
+# CONFIG_DVB_DRX39XYJ is not set
+# CONFIG_DVB_LNBH25 is not set
+# CONFIG_DVB_LNBH29 is not set
+# CONFIG_DVB_LNBP21 is not set
+# CONFIG_DVB_LNBP22 is not set
+# CONFIG_DVB_ISL6405 is not set
+# CONFIG_DVB_ISL6421 is not set
+# CONFIG_DVB_ISL6423 is not set
+# CONFIG_DVB_A8293 is not set
+# CONFIG_DVB_LGS8GL5 is not set
+# CONFIG_DVB_LGS8GXX is not set
+# CONFIG_DVB_ATBM8830 is not set
+# CONFIG_DVB_TDA665x is not set
+# CONFIG_DVB_IX2505V is not set
+# CONFIG_DVB_M88RS2000 is not set
+# CONFIG_DVB_AF9033 is not set
+# CONFIG_DVB_HORUS3A is not set
+# CONFIG_DVB_ASCOT2E is not set
+# CONFIG_DVB_HELENE is not set
+
+#
+# Common Interface (EN50221) controller drivers
+#
+# CONFIG_DVB_CXD2099 is not set
+# CONFIG_DVB_SP2 is not set
+# end of Customise DVB Frontends
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_DRM=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=m
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_SCHED=m
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_HDLCD is not set
+# CONFIG_DRM_MALI_DISPLAY is not set
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_ROCKCHIP is not set
+CONFIG_DRM_ROCKCHIP_EBC=m
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_EDP is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_SIMPLE_BRIDGE is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_HISI_KIRIN is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_XEN_FRONTEND is not set
+# CONFIG_DRM_LIMA is not set
+CONFIG_DRM_PANFROST=m
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_EFI is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_XEN_FBDEV_FRONTEND=y
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SSD1307 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_PWM is not set
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_LM3630A=y
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_LED is not set
+# end of Backlight & LCD device support
+
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+# end of Console display driver support
+
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# end of Graphics support
+
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_MPU401=m
+
+#
+# HD-Audio
+#
+# end of HD-Audio
+
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_ADI is not set
+# CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_AUDMIX is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_FSL_MICFIL is not set
+# CONFIG_SND_SOC_FSL_XCVR is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# end of SoC Audio for Freescale CPUs
+
+# CONFIG_SND_I2S_HI6210_I2S is not set
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+CONFIG_SND_SOC_ROCKCHIP=m
+# CONFIG_SND_SOC_ROCKCHIP_I2S is not set
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
+# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
+# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
+# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set
+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+
+#
+# CODEC drivers
+#
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4613 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+CONFIG_SND_SOC_BT_SCO=m
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+CONFIG_SND_SOC_DMIC=m
+# CONFIG_SND_SOC_ES7134 is not set
+# CONFIG_SND_SOC_ES7241 is not set
+# CONFIG_SND_SOC_ES8316 is not set
+# CONFIG_SND_SOC_ES8328_I2C is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+# CONFIG_SND_SOC_MAX98357A is not set
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+# CONFIG_SND_SOC_MAX98927 is not set
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_I2C is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM5102A is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_RK3328 is not set
+CONFIG_SND_SOC_RK817=m
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+# CONFIG_SND_SOC_RT5659 is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SGTL5000 is not set
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+# CONFIG_SND_SOC_SIMPLE_MUX is not set
+# CONFIG_SND_SOC_SPDIF is not set
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731 is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SND_SOC_WM8904 is not set
+# CONFIG_SND_SOC_WM8960 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SIMPLE_CARD=m
+# CONFIG_SND_AUDIO_GRAPH_CARD is not set
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+# CONFIG_SND_XEN_FRONTEND is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_ASUS is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_BIGBEN_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CORSAIR is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CP2112 is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELAN is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_FT260 is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_GLORIOUS is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_XIAOMI is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LED is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NINTENDO is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PLAYSTATION is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SEMITEK is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# CONFIG_HID_MCP2221 is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+# end of USB HID support
+
+#
+# I2C HID support
+#
+CONFIG_I2C_HID_OF=m
+CONFIG_I2C_HID_OF_GOODIX=m
+# end of I2C HID support
+
+CONFIG_I2C_HID_CORE=m
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_LED_TRIG=y
+# CONFIG_USB_ULPI_BUS is not set
+# CONFIG_USB_CONN_GPIO is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+CONFIG_USB_LEDS_TRIGGER_USBPORT=y
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+# CONFIG_USB_XEN_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_MUSB_HDRC is not set
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+#
+# Platform Glue Driver Support
+#
+CONFIG_USB_DWC3_OF_SIMPLE=y
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_ULPI is not set
+# end of USB Physical Layer drivers
+
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_U_SERIAL_CONSOLE is not set
+
+#
+# USB Peripheral Controller
+#
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_SNP_UDC_PLAT is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_BDC_UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_DUMMY_HCD is not set
+# end of USB Peripheral Controller
+
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_F_SERIAL=y
+CONFIG_USB_F_NCM=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_F_SUBSET=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_F_HID=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+# CONFIG_USB_CONFIGFS_OBEX is not set
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+# CONFIG_USB_CONFIGFS_RNDIS is not set
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+# CONFIG_USB_CONFIGFS_F_LB_SS is not set
+# CONFIG_USB_CONFIGFS_F_FS is not set
+CONFIG_USB_CONFIGFS_F_UAC1=y
+# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
+CONFIG_USB_CONFIGFS_F_UAC2=y
+# CONFIG_USB_CONFIGFS_F_MIDI is not set
+CONFIG_USB_CONFIGFS_F_HID=y
+# CONFIG_USB_CONFIGFS_F_UVC is not set
+# CONFIG_USB_CONFIGFS_F_PRINTER is not set
+
+#
+# USB Gadget precomposed configurations
+#
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_ACM_MS is not set
+CONFIG_USB_G_MULTI=m
+# CONFIG_USB_G_MULTI_RNDIS is not set
+CONFIG_USB_G_MULTI_CDC=y
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_USB_RAW_GADGET is not set
+# end of USB Gadget precomposed configurations
+
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_TCPM is not set
+# CONFIG_TYPEC_UCSI is not set
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_WUSB3801=y
+
+#
+# USB Type-C Multiplexer/DeMultiplexer Switch support
+#
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# end of USB Type-C Multiplexer/DeMultiplexer Switch support
+
+#
+# USB Type-C Alternate Mode drivers
+#
+# CONFIG_TYPEC_DP_ALTMODE is not set
+# end of USB Type-C Alternate Mode drivers
+
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_OF_ASPEED is not set
+# CONFIG_MMC_SDHCI_OF_AT91 is not set
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_CADENCE is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MMC_SDHCI_XENON is not set
+# CONFIG_MMC_SDHCI_OMAP is not set
+# CONFIG_MMC_SDHCI_AM654 is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_CLASS_MULTICOLOR=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_EL15203000 is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+# CONFIG_LEDS_SYSCON is not set
+# CONFIG_LEDS_MLXREG is not set
+# CONFIG_LEDS_USER is not set
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+
+#
+# Flash and Torch LED drivers
+#
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PATTERN=y
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_TTY=y
+
+#
+# Simple LED drivers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_RK808=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_EFI is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_ZYNQMP is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_BCM_SBA_RAID is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_MV_XOR_V2 is not set
+CONFIG_PL330_DMA=y
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_SF_PDMA is not set
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VFIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VDPA is not set
+# CONFIG_VHOST_MENU is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+#
+# Xen driver support
+#
+CONFIG_XEN_BALLOON=y
+CONFIG_XEN_SCRUB_PAGES_DEFAULT=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XENFS=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_SYS_HYPERVISOR=y
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XEN_GNTDEV=m
+CONFIG_XEN_GRANT_DEV_ALLOC=m
+# CONFIG_XEN_GRANT_DMA_ALLOC is not set
+CONFIG_SWIOTLB_XEN=y
+# CONFIG_XEN_PVCALLS_FRONTEND is not set
+# CONFIG_XEN_PVCALLS_BACKEND is not set
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_EFI=y
+CONFIG_XEN_AUTO_XLATE=y
+# end of Xen driver support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+# CONFIG_PRISM2_USB is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_RTL8723BS is not set
+# CONFIG_R8712U is not set
+# CONFIG_R8188EU is not set
+# CONFIG_VT6656 is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16240 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7816 is not set
+# CONFIG_AD7280 is not set
+# end of Analog to digital converters
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+# end of Analog digital bi-direction converters
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7746 is not set
+# end of Capacitance to digital converters
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# end of Direct Digital Synthesis
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+# end of Network Analyzer, Impedance Converters
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7854 is not set
+# end of Active energy metering IC
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S1210 is not set
+# end of Resolver to digital converters
+# end of IIO staging drivers
+
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+
+#
+# Android
+#
+# end of Android
+
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_KS7010 is not set
+# CONFIG_PI433 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_WFX is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCMI=y
+# CONFIG_COMMON_CLK_SCPI is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+# CONFIG_COMMON_CLK_PWM is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_COMMON_CLK_ROCKCHIP=y
+# CONFIG_CLK_PX30 is not set
+# CONFIG_CLK_RK3308 is not set
+# CONFIG_CLK_RK3328 is not set
+# CONFIG_CLK_RK3368 is not set
+# CONFIG_CLK_RK3399 is not set
+CONFIG_CLK_RK3568=y
+# CONFIG_XILINX_VCU is not set
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_FSL_ERRATUM_A008585 is not set
+# CONFIG_HISILICON_ERRATUM_161010101 is not set
+# CONFIG_ARM64_ERRATUM_858921 is not set
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+# CONFIG_ARM_MHU is not set
+# CONFIG_ARM_MHU_V2 is not set
+# CONFIG_PLATFORM_MHU is not set
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_OF_IOMMU=y
+CONFIG_IOMMU_DMA=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SMMU_V3 is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# end of Enable LiteX SoC Builder specific drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+# CONFIG_EXTCON_ADC_JACK is not set
+# CONFIG_EXTCON_FSA9480 is not set
+# CONFIG_EXTCON_GPIO is not set
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+# CONFIG_EXTCON_USB_GPIO is not set
+# CONFIG_EXTCON_USBC_TUSB320 is not set
+# CONFIG_MEMORY is not set
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+# CONFIG_IIO_SW_DEVICE is not set
+CONFIG_IIO_SW_TRIGGER=y
+CONFIG_IIO_TRIGGERED_EVENT=y
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
+# CONFIG_ADXL345_I2C is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXL372_I2C is not set
+# CONFIG_BMA180 is not set
+# CONFIG_BMA220 is not set
+# CONFIG_BMA400 is not set
+# CONFIG_BMC150_ACCEL is not set
+# CONFIG_BMI088_ACCEL is not set
+# CONFIG_DA280 is not set
+# CONFIG_DA311 is not set
+# CONFIG_DMARD06 is not set
+# CONFIG_DMARD09 is not set
+# CONFIG_DMARD10 is not set
+# CONFIG_FXLS8962AF_I2C is not set
+# CONFIG_FXLS8962AF_SPI is not set
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+# CONFIG_KXSD9 is not set
+# CONFIG_KXCJK1013 is not set
+# CONFIG_MC3230 is not set
+# CONFIG_MMA7455_I2C is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMA7660 is not set
+# CONFIG_MMA8452 is not set
+# CONFIG_MMA9551 is not set
+# CONFIG_MMA9553 is not set
+# CONFIG_MXC4005 is not set
+# CONFIG_MXC6255 is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SCA3300 is not set
+# CONFIG_STK8312 is not set
+# CONFIG_STK8BA50 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7091R5 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7291 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606_IFACE_PARALLEL is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD799X is not set
+# CONFIG_ADI_AXI_ADC is not set
+# CONFIG_CC10001_ADC is not set
+# CONFIG_ENVELOPE_DETECTOR is not set
+# CONFIG_HI8435 is not set
+# CONFIG_HX711 is not set
+# CONFIG_INA2XX_ADC is not set
+# CONFIG_LTC2471 is not set
+# CONFIG_LTC2485 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2497 is not set
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX1363 is not set
+# CONFIG_MAX9611 is not set
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3422 is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_NAU7802 is not set
+CONFIG_ROCKCHIP_SARADC=y
+# CONFIG_SD_ADC_MODULATOR is not set
+# CONFIG_TI_ADC081C is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS1015 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS131E08 is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_TI_TSC2046 is not set
+# CONFIG_VF610_ADC is not set
+# CONFIG_XILINX_XADC is not set
+# end of Analog to digital converters
+
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
+# Analog Front Ends
+#
+# CONFIG_IIO_RESCALE is not set
+# end of Analog Front Ends
+
+#
+# Amplifiers
+#
+# CONFIG_AD8366 is not set
+# CONFIG_HMC425 is not set
+# end of Amplifiers
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# end of Capacitance to digital converters
+
+#
+# Chemical Sensors
+#
+# CONFIG_ATLAS_PH_SENSOR is not set
+# CONFIG_ATLAS_EZO_SENSOR is not set
+# CONFIG_BME680 is not set
+# CONFIG_CCS811 is not set
+# CONFIG_IAQCORE is not set
+# CONFIG_PMS7003 is not set
+# CONFIG_SCD30_CORE is not set
+# CONFIG_SCD4X is not set
+# CONFIG_SENSIRION_SGP30 is not set
+# CONFIG_SENSIRION_SGP40 is not set
+# CONFIG_SPS30_I2C is not set
+# CONFIG_SPS30_SERIAL is not set
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
+# CONFIG_VZ89X is not set
+# end of Chemical Sensors
+
+#
+# Hid Sensor IIO Common
+#
+# end of Hid Sensor IIO Common
+
+#
+# IIO SCMI Sensors
+#
+# CONFIG_IIO_SCMI is not set
+# end of IIO SCMI Sensors
+
+#
+# SSP Sensor Common
+#
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# end of SSP Sensor Common
+
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD3552R is not set
+# CONFIG_AD5064 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5593R is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5696_I2C is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5766 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_DPOT_DAC is not set
+# CONFIG_DS4424 is not set
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_M62332 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MAX5821 is not set
+# CONFIG_MCP4725 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC5571 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_VF610_DAC is not set
+# end of Digital to analog converters
+
+#
+# IIO dummy driver
+#
+# end of IIO dummy driver
+
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+# CONFIG_AD9523 is not set
+# end of Clock Generator/Distribution
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADRF6780 is not set
+# end of Phase-Locked Loop (PLL) frequency synthesizers
+# end of Frequency Synthesizers DDS/PLL
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_BMG160 is not set
+# CONFIG_FXAS21002C is not set
+# CONFIG_MPU3050_I2C is not set
+# CONFIG_IIO_ST_GYRO_3AXIS is not set
+# CONFIG_ITG3200 is not set
+# end of Digital gyroscope sensors
+
+#
+# Health Sensors
+#
+
+#
+# Heart Rate Monitors
+#
+# CONFIG_AFE4403 is not set
+# CONFIG_AFE4404 is not set
+# CONFIG_MAX30100 is not set
+# CONFIG_MAX30102 is not set
+# end of Heart Rate Monitors
+# end of Health Sensors
+
+#
+# Humidity sensors
+#
+# CONFIG_AM2315 is not set
+# CONFIG_DHT11 is not set
+# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
+# CONFIG_HTS221 is not set
+# CONFIG_HTU21 is not set
+# CONFIG_SI7005 is not set
+# CONFIG_SI7020 is not set
+# end of Humidity sensors
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_BMI160_I2C is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_FXOS8700_I2C is not set
+# CONFIG_FXOS8700_SPI is not set
+# CONFIG_KMX61 is not set
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_I2C is not set
+# CONFIG_INV_MPU6050_SPI is not set
+# CONFIG_IIO_ST_LSM6DSX is not set
+# CONFIG_IIO_ST_LSM9DS0 is not set
+# end of Inertial measurement units
+
+#
+# Light sensors
+#
+# CONFIG_ADJD_S311 is not set
+# CONFIG_ADUX1020 is not set
+# CONFIG_AL3010 is not set
+# CONFIG_AL3320A is not set
+# CONFIG_APDS9300 is not set
+# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
+# CONFIG_BH1750 is not set
+# CONFIG_BH1780 is not set
+# CONFIG_CM32181 is not set
+# CONFIG_CM3232 is not set
+# CONFIG_CM3323 is not set
+# CONFIG_CM3605 is not set
+# CONFIG_CM36651 is not set
+# CONFIG_GP2AP002 is not set
+# CONFIG_GP2AP020A00F is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_ISL29125 is not set
+# CONFIG_JSA1212 is not set
+# CONFIG_RPR0521 is not set
+# CONFIG_LTR501 is not set
+# CONFIG_LV0104CS is not set
+# CONFIG_MAX44000 is not set
+# CONFIG_MAX44009 is not set
+# CONFIG_NOA1305 is not set
+# CONFIG_OPT3001 is not set
+# CONFIG_PA12203001 is not set
+# CONFIG_SI1133 is not set
+# CONFIG_SI1145 is not set
+# CONFIG_STK3310 is not set
+# CONFIG_ST_UVIS25 is not set
+# CONFIG_TCS3414 is not set
+# CONFIG_TCS3472 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TSL2591 is not set
+# CONFIG_TSL2772 is not set
+# CONFIG_TSL4531 is not set
+# CONFIG_US5182D is not set
+# CONFIG_VCNL4000 is not set
+# CONFIG_VCNL4035 is not set
+# CONFIG_VEML6030 is not set
+# CONFIG_VEML6070 is not set
+# CONFIG_VL6180 is not set
+# CONFIG_ZOPT2201 is not set
+# end of Light sensors
+
+#
+# Magnetometer sensors
+#
+# CONFIG_AK8974 is not set
+# CONFIG_AK8975 is not set
+# CONFIG_AK09911 is not set
+# CONFIG_BMC150_MAGN_I2C is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_MAG3110 is not set
+# CONFIG_MMC35240 is not set
+# CONFIG_IIO_ST_MAGN_3AXIS is not set
+# CONFIG_SENSORS_HMC5843_I2C is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_RM3100_I2C is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_YAMAHA_YAS530 is not set
+# end of Magnetometer sensors
+
+#
+# Multiplexers
+#
+# CONFIG_IIO_MUX is not set
+# end of Multiplexers
+
+#
+# Inclinometer sensors
+#
+# end of Inclinometer sensors
+
+#
+# Triggers - standalone
+#
+# CONFIG_IIO_HRTIMER_TRIGGER is not set
+# CONFIG_IIO_INTERRUPT_TRIGGER is not set
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+# CONFIG_IIO_SYSFS_TRIGGER is not set
+# end of Triggers - standalone
+
+#
+# Linear and angular position sensors
+#
+# end of Linear and angular position sensors
+
+#
+# Digital potentiometers
+#
+# CONFIG_AD5110 is not set
+# CONFIG_AD5272 is not set
+# CONFIG_DS1803 is not set
+# CONFIG_MAX5432 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MCP4018 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4531 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_TPL0102 is not set
+# end of Digital potentiometers
+
+#
+# Digital potentiostats
+#
+# CONFIG_LMP91000 is not set
+# end of Digital potentiostats
+
+#
+# Pressure sensors
+#
+# CONFIG_ABP060MG is not set
+# CONFIG_BMP280 is not set
+# CONFIG_DLHL60D is not set
+# CONFIG_DPS310 is not set
+# CONFIG_HP03 is not set
+# CONFIG_ICP10100 is not set
+# CONFIG_MPL115_I2C is not set
+# CONFIG_MPL115_SPI is not set
+# CONFIG_MPL3115 is not set
+# CONFIG_MS5611 is not set
+# CONFIG_MS5637 is not set
+# CONFIG_IIO_ST_PRESS is not set
+# CONFIG_T5403 is not set
+# CONFIG_HP206C is not set
+# CONFIG_ZPA2326 is not set
+# end of Pressure sensors
+
+#
+# Lightning sensors
+#
+# CONFIG_AS3935 is not set
+# end of Lightning sensors
+
+#
+# Proximity and distance sensors
+#
+# CONFIG_ISL29501 is not set
+# CONFIG_LIDAR_LITE_V2 is not set
+# CONFIG_MB1232 is not set
+# CONFIG_PING is not set
+# CONFIG_RFD77402 is not set
+# CONFIG_SRF04 is not set
+# CONFIG_SX9310 is not set
+# CONFIG_SX9500 is not set
+# CONFIG_SRF08 is not set
+# CONFIG_VCNL3020 is not set
+# CONFIG_VL53L0X_I2C is not set
+# end of Proximity and distance sensors
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1200 is not set
+# end of Resolver to digital converters
+
+#
+# Temperature sensors
+#
+# CONFIG_LTC2983 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MLX90614 is not set
+# CONFIG_MLX90632 is not set
+# CONFIG_TMP006 is not set
+# CONFIG_TMP007 is not set
+# CONFIG_TMP117 is not set
+# CONFIG_TSYS01 is not set
+# CONFIG_TSYS02D is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX31865 is not set
+# end of Temperature sensors
+
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+# CONFIG_AL_FIC is not set
+CONFIG_PARTITION_PERCPU=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_SCMI is not set
+# CONFIG_RESET_TI_SYSCON is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+
+#
+# PHY drivers for Broadcom platforms
+#
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+# CONFIG_PHY_ROCKCHIP_EMMC is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_PHY_ROCKCHIP_INNO_VIDEO_COMBO_PHY is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+# CONFIG_PHY_ROCKCHIP_PCIE is not set
+# CONFIG_PHY_ROCKCHIP_TYPEC is not set
+# CONFIG_PHY_ROCKCHIP_USB is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# CONFIG_ARM_CCI_PMU is not set
+# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
+CONFIG_ARM_PMU=y
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_SPE_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
+# end of Performance monitor support
+
+# CONFIG_RAS is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+# CONFIG_DAX is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_OTP=y
+# CONFIG_NVMEM_RMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_ZSTD=y
+CONFIG_F2FS_IOSTAT=y
+# CONFIG_FS_DAX is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=m
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+# CONFIG_VIRTIO_FS is not set
+CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+CONFIG_OVERLAY_FS_METACOPY=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_EXFAT_FS=y
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+# CONFIG_NTFS_FS is not set
+CONFIG_NTFS3_FS=m
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTFS3_FS_POSIX_ACL=y
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+# end of Pseudo filesystems
+
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V2=m
+CONFIG_NFS_V3=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_PNFS_BLOCK=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFS_V4_SECURITY_LABEL=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+# CONFIG_NFSD_FLEXFILELAYOUT is not set
+CONFIG_NFSD_V4_2_INTER_SSC=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_GRACE_PERIOD=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_SWAP=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DEBUG=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_SWN_UPCALL=y
+CONFIG_SMB_SERVER=m
+CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_SMBFS_COMMON=m
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf-8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+CONFIG_UNICODE=y
+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+# CONFIG_SECURITY_SELINUX is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_APPARMOR_HASH=y
+CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
+# CONFIG_SECURITY_APPARMOR_DEBUG is not set
+# CONFIG_SECURITY_LOADPIN is not set
+# CONFIG_SECURITY_YAMA is not set
+# CONFIG_SECURITY_SAFESETID is not set
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
+# CONFIG_SECURITY_LANDLOCK is not set
+CONFIG_INTEGRITY=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
+CONFIG_INTEGRITY_AUDIT=y
+# CONFIG_IMA is not set
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+# CONFIG_EVM is not set
+# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM=""
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_ESSIV=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_BLAKE2B=m
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD160 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ZSTD=m
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
+CONFIG_CRYPTO_HASH_INFO=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+# CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_XXHASH=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_COMPAT_GENERIC=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_842_COMPRESS=m
+CONFIG_842_DECOMPRESS=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_COMPRESS=m
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+# CONFIG_XZ_DEC_MICROLZMA is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_RESTRICTED_POOL is not set
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_DIRECT_REMAP=y
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_CLZ_TAB=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_MPILIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_UCS2_STRING=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_SBITMAP=y
+# end of Library routines
+
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+# CONFIG_DEBUG_INFO is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_MISC is not set
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=5
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_INFO=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+CONFIG_DEBUG_PREEMPT=y
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_TRACE=y
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+CONFIG_CPU_HOTPLUG_STATE_CONTROL=y
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+
+#
+# arm64 Debugging
+#
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_CORESIGHT is not set
+# end of arm64 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_ARCH_USE_MEMTEST=y
+# CONFIG_MEMTEST is not set
+# end of Kernel Testing and Coverage
+# end of Kernel hacking
diff --git a/nongnu/configs/pinenote_defconfig b/nongnu/configs/pinenote_defconfig
new file mode 100644
index 0000000..c69b9f1
--- /dev/null
+++ b/nongnu/configs/pinenote_defconfig
@@ -0,0 +1,6026 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 5.17.0-rc6 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 10.3.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=100300
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=23700
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=23700
+CONFIG_LLD_VERSION=0
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_PAHOLE_VERSION=0
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="pinenote"
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_DEBUGFS=y
+# end of IRQ subsystem
+
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+# CONFIG_BPF_PRELOAD is not set
+# end of BPF subsystem
+
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_DYNAMIC is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_SCHED_AVG_IRQ=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_PSI_DEFAULT_DISABLED=y
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=0
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+# CONFIG_PROC_PID_CPUSET is not set
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_RD_ZSTD=y
+# CONFIG_BOOT_CONFIG is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_EXPERT=y
+# CONFIG_UID16 is not set
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_USERFAULTFD=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+# CONFIG_DEBUG_RSEQ is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
+# end of General setup
+
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_SMP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+
+#
+# Platform selection
+#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_BCM2835 is not set
+# CONFIG_ARCH_BCM4908 is not set
+# CONFIG_ARCH_BCM_IPROC is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_S32 is not set
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# end of Platform selection
+
+#
+# Kernel Features
+#
+
+#
+# ARM errata workarounds via the alternatives framework
+#
+# CONFIG_ARM64_ERRATUM_826319 is not set
+# CONFIG_ARM64_ERRATUM_827319 is not set
+# CONFIG_ARM64_ERRATUM_824069 is not set
+# CONFIG_ARM64_ERRATUM_819472 is not set
+# CONFIG_ARM64_ERRATUM_832075 is not set
+# CONFIG_ARM64_ERRATUM_845719 is not set
+# CONFIG_ARM64_ERRATUM_843419 is not set
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+# CONFIG_ARM64_ERRATUM_1418040 is not set
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+# CONFIG_ARM64_ERRATUM_1165522 is not set
+# CONFIG_ARM64_ERRATUM_1319367 is not set
+CONFIG_ARM64_ERRATUM_1530923=y
+# CONFIG_ARM64_ERRATUM_1286807 is not set
+# CONFIG_ARM64_ERRATUM_1463225 is not set
+# CONFIG_ARM64_ERRATUM_1542419 is not set
+# CONFIG_ARM64_ERRATUM_1508412 is not set
+# CONFIG_ARM64_ERRATUM_2051678 is not set
+CONFIG_ARM64_ERRATUM_2077057=y
+# CONFIG_ARM64_ERRATUM_2054223 is not set
+# CONFIG_ARM64_ERRATUM_2067961 is not set
+# CONFIG_CAVIUM_ERRATUM_22375 is not set
+# CONFIG_CAVIUM_ERRATUM_23154 is not set
+# CONFIG_CAVIUM_ERRATUM_27456 is not set
+# CONFIG_CAVIUM_ERRATUM_30115 is not set
+# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
+# CONFIG_FUJITSU_ERRATUM_010001 is not set
+# CONFIG_HISILICON_ERRATUM_161600802 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
+# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
+# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
+# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
+# end of ARM errata workarounds via the alternatives framework
+
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+CONFIG_ARM64_VA_BITS_39=y
+# CONFIG_ARM64_VA_BITS_48 is not set
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SCHED_MC=y
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_NUMA is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HW_PERF_EVENTS=y
+# CONFIG_PARAVIRT is not set
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+# CONFIG_KEXEC is not set
+# CONFIG_KEXEC_FILE is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_XEN is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
+CONFIG_COMPAT=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_ARMV8_DEPRECATED=y
+# CONFIG_SWP_EMULATION is not set
+CONFIG_CP15_BARRIER_EMULATION=y
+# CONFIG_SETEND_EMULATION is not set
+
+#
+# ARMv8.1 architectural features
+#
+# CONFIG_ARM64_HW_AFDBM is not set
+CONFIG_ARM64_PAN=y
+CONFIG_AS_HAS_LDAPR=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+# end of ARMv8.1 architectural features
+
+#
+# ARMv8.2 architectural features
+#
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
+# CONFIG_ARM64_PMEM is not set
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+# end of ARMv8.2 architectural features
+
+#
+# ARMv8.3 architectural features
+#
+# CONFIG_ARM64_PTR_AUTH is not set
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_AS_HAS_PAC=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+# end of ARMv8.3 architectural features
+
+#
+# ARMv8.4 architectural features
+#
+# CONFIG_ARM64_AMU_EXTN is not set
+CONFIG_AS_HAS_ARMV8_4=y
+CONFIG_ARM64_TLB_RANGE=y
+# end of ARMv8.4 architectural features
+
+#
+# ARMv8.5 architectural features
+#
+CONFIG_AS_HAS_ARMV8_5=y
+# CONFIG_ARM64_BTI is not set
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+# CONFIG_ARM64_E0PD is not set
+# CONFIG_ARCH_RANDOM is not set
+CONFIG_ARM64_AS_HAS_MTE=y
+# end of ARMv8.5 architectural features
+
+#
+# ARMv8.7 architectural features
+#
+# CONFIG_ARM64_EPAN is not set
+# end of ARMv8.7 architectural features
+
+# CONFIG_ARM64_SVE is not set
+# CONFIG_ARM64_MODULE_PLTS is not set
+# CONFIG_ARM64_PSEUDO_NMI is not set
+# CONFIG_RELOCATABLE is not set
+# CONFIG_RANDOMIZE_BASE is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+# end of Kernel Features
+
+#
+# Boot options
+#
+CONFIG_CMDLINE=""
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+CONFIG_DMI=y
+# end of Boot options
+
+CONFIG_SYSVIPC_COMPAT=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SUSPEND_SKIP_SYNC is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_PM_SLEEP_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_GOV_TEO=y
+CONFIG_DT_IDLE_STATES=y
+
+#
+# ARM CPU Idle Drivers
+#
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# end of ARM CPU Idle Drivers
+# end of CPU Idle
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+# CONFIG_ARM_SCMI_CPUFREQ is not set
+# end of CPU Frequency scaling
+# end of CPU Power Management
+
+CONFIG_ARCH_SUPPORTS_ACPI=y
+# CONFIG_ACPI is not set
+CONFIG_HAVE_KVM=y
+# CONFIG_VIRTUALIZATION is not set
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=y
+# CONFIG_CRYPTO_SHA3_ARM64 is not set
+# CONFIG_CRYPTO_SM3_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE is not set
+# CONFIG_CRYPTO_GHASH_ARM64_CE is not set
+# CONFIG_CRYPTO_AES_ARM64 is not set
+CONFIG_CRYPTO_AES_ARM64_CE=y
+# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_POLY1305_NEON=m
+# CONFIG_CRYPTO_NHPOLY1305_NEON is not set
+# CONFIG_CRYPTO_AES_ARM64_BS is not set
+
+#
+# General architecture-dependent options
+#
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_HAVE_PREEMPT_DYNAMIC=y
+CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ASM_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEV_BSG_COMMON=m
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+# CONFIG_BLK_WBT is not set
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+# CONFIG_BLK_DEBUG_FS is not set
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BLK_MQ_STACKING=y
+
+#
+# IO Schedulers
+#
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
+CONFIG_ARCH_INLINE_SPIN_LOCK=y
+CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
+CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
+CONFIG_ARCH_INLINE_READ_LOCK=y
+CONFIG_ARCH_INLINE_READ_LOCK_BH=y
+CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
+CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
+CONFIG_ARCH_INLINE_READ_UNLOCK=y
+CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
+CONFIG_ARCH_INLINE_WRITE_LOCK=y
+CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
+CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
+CONFIG_INLINE_SPIN_TRYLOCK=y
+CONFIG_INLINE_SPIN_TRYLOCK_BH=y
+CONFIG_INLINE_SPIN_LOCK=y
+CONFIG_INLINE_SPIN_LOCK_BH=y
+CONFIG_INLINE_SPIN_LOCK_IRQ=y
+CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
+CONFIG_INLINE_SPIN_UNLOCK_BH=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
+CONFIG_INLINE_READ_LOCK=y
+CONFIG_INLINE_READ_LOCK_BH=y
+CONFIG_INLINE_READ_LOCK_IRQ=y
+CONFIG_INLINE_READ_LOCK_IRQSAVE=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_BH=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
+CONFIG_INLINE_WRITE_LOCK=y
+CONFIG_INLINE_WRITE_LOCK_BH=y
+CONFIG_INLINE_WRITE_LOCK_IRQ=y
+CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_BH=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ELFCORE=y
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_COREDUMP is not set
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_COMPACTION=y
+# CONFIG_PAGE_REPORTING is not set
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_CMA=y
+CONFIG_CMA_DEBUG=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA_AREAS=7
+# CONFIG_ZPOOL is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_FILTER_PGPROT=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+CONFIG_SKB_EXTENSIONS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=m
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_INTERFACE is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_ESP=m
+# CONFIG_NET_KEY is not set
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_IPVTI is not set
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_ESP=m
+# CONFIG_INET_ESP_OFFLOAD is not set
+# CONFIG_INET_ESPINTCP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=m
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+# CONFIG_NETFILTER_NETLINK_HOOK is not set
+# CONFIG_NETFILTER_NETLINK_ACCT is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_OSF is not set
+CONFIG_NF_CONNTRACK=m
+# CONFIG_NF_LOG_SYSLOG is not set
+CONFIG_NETFILTER_CONNCOUNT=m
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_ZONES is not set
+CONFIG_NF_CONNTRACK_PROCFS=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CONNTRACK_LABELS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_TABLES=m
+# CONFIG_NF_TABLES_INET is not set
+# CONFIG_NF_TABLES_NETDEV is not set
+# CONFIG_NFT_NUMGEN is not set
+CONFIG_NFT_CT=m
+CONFIG_NFT_CONNLIMIT=m
+# CONFIG_NFT_LOG is not set
+# CONFIG_NFT_LIMIT is not set
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+# CONFIG_NFT_TUNNEL is not set
+# CONFIG_NFT_OBJREF is not set
+# CONFIG_NFT_QUOTA is not set
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+# CONFIG_NFT_XFRM is not set
+# CONFIG_NFT_SOCKET is not set
+# CONFIG_NFT_OSF is not set
+# CONFIG_NFT_TPROXY is not set
+# CONFIG_NFT_SYNPROXY is not set
+# CONFIG_NF_FLOW_TABLE is not set
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XTABLES_COMPAT=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+# CONFIG_NETFILTER_XT_TARGET_LOG is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_NAT=m
+# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+# CONFIG_NETFILTER_XT_MATCH_BPF is not set
+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ECN is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# end of Core Netfilter Configuration
+
+# CONFIG_IP_SET is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+# CONFIG_IP_VS_PROTO_ESP is not set
+# CONFIG_IP_VS_PROTO_AH is not set
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+# CONFIG_IP_VS_WRR is not set
+# CONFIG_IP_VS_LC is not set
+# CONFIG_IP_VS_WLC is not set
+# CONFIG_IP_VS_FO is not set
+# CONFIG_IP_VS_OVF is not set
+# CONFIG_IP_VS_LBLC is not set
+# CONFIG_IP_VS_LBLCR is not set
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_SH is not set
+# CONFIG_IP_VS_MH is not set
+# CONFIG_IP_VS_SED is not set
+# CONFIG_IP_VS_NQ is not set
+# CONFIG_IP_VS_TWOS is not set
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_NFCT=y
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+# CONFIG_NF_SOCKET_IPV4 is not set
+# CONFIG_NF_TPROXY_IPV4 is not set
+# CONFIG_NF_TABLES_IPV4 is not set
+# CONFIG_NF_TABLES_ARP is not set
+# CONFIG_NF_DUP_IPV4 is not set
+# CONFIG_NF_LOG_ARP is not set
+# CONFIG_NF_LOG_IPV4 is not set
+# CONFIG_NF_REJECT_IPV4 is not set
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=m
+# CONFIG_IP_NF_TARGET_REJECT is not set
+# CONFIG_IP_NF_TARGET_SYNPROXY is not set
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_SOCKET_IPV6 is not set
+# CONFIG_NF_TPROXY_IPV6 is not set
+# CONFIG_NF_TABLES_IPV6 is not set
+# CONFIG_NF_DUP_IPV6 is not set
+# CONFIG_NF_REJECT_IPV6 is not set
+# CONFIG_NF_LOG_IPV6 is not set
+CONFIG_IP6_NF_IPTABLES=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_MATCH_SRH is not set
+# CONFIG_IP6_NF_FILTER is not set
+# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP6_NF_NAT is not set
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+# CONFIG_NF_TABLES_BRIDGE is not set
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_CFM is not set
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_CBS is not set
+# CONFIG_NET_SCH_ETF is not set
+# CONFIG_NET_SCH_TAPRIO is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_SKBPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_FQ_CODEL is not set
+# CONFIG_NET_SCH_CAKE is not set
+# CONFIG_NET_SCH_FQ is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_PIE is not set
+# CONFIG_NET_SCH_PLUG is not set
+# CONFIG_NET_SCH_ETS is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_CLS_CGROUP=m
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_CLS_FLOWER is not set
+# CONFIG_NET_CLS_MATCHALL is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NET_L3_MASTER_DEV=y
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_STREAM_PARSER is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+# CONFIG_BT_BNEP is not set
+CONFIG_BT_HIDP=m
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_LEDS=y
+# CONFIG_BT_MSFTEXT is not set
+# CONFIG_BT_AOSPEXT is not set
+CONFIG_BT_DEBUGFS=y
+# CONFIG_BT_SELFTEST is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_BCM=m
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_NOKIA is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIUART_3WIRE is not set
+# CONFIG_BT_HCIUART_INTEL is not set
+CONFIG_BT_HCIUART_BCM=y
+# CONFIG_BT_HCIUART_RTL is not set
+# CONFIG_BT_HCIUART_QCA is not set
+# CONFIG_BT_HCIUART_AG6XX is not set
+# CONFIG_BT_HCIUART_MRVL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_MTKSDIO is not set
+# CONFIG_BT_MTKUART is not set
+# end of Bluetooth device drivers
+
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_MCTP is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_CERTIFICATION_ONUS=y
+# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set
+# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set
+# CONFIG_CFG80211_REG_RELAX_NO_IR is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEBUGFS=y
+# CONFIG_CFG80211_CRDA_SUPPORT is not set
+# CONFIG_CFG80211_WEXT is not set
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT=""
+
+#
+# Some wireless drivers require a rate control algorithm
+#
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SOCK_MSG=y
+# CONFIG_FAILOVER is not set
+# CONFIG_ETHTOOL_NETLINK is not set
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+# CONFIG_PCI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# CONFIG_FW_CACHE is not set
+# end of Firmware loader
+
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=m
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_MHI_BUS is not set
+# CONFIG_MHI_BUS_EP is not set
+# end of Bus devices
+
+# CONFIG_CONNECTOR is not set
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+# CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+# CONFIG_ARM_SCMI_POWER_DOMAIN is not set
+# end of ARM System Control and Management Interface Protocol
+
+# CONFIG_ARM_SCPI_PROTOCOL is not set
+CONFIG_ARM_SDE_INTERFACE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_ROCKCHIP_SIP=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+# CONFIG_ARM_FFA_TRANSPORT is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_TEST is not set
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_EFI_EARLYCON=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+# CONFIG_ARM_SMCCC_SOC_ID is not set
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+CONFIG_CDROM=m
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# NVME Support
+#
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_OPEN_DICE is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_ECHO is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_UACCE is not set
+# CONFIG_PVPANIC is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI_COMMON=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+CONFIG_HAVE_PATA_PLATFORM=y
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_BUFIO=m
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_PERSISTENT_DATA=m
+# CONFIG_DM_UNSTRIPED is not set
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+CONFIG_DM_THIN_PROVISIONING=m
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_WRITECACHE is not set
+# CONFIG_DM_EBS is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_CLONE is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_DUST is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_DM_INTEGRITY is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=m
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_TEAM is not set
+CONFIG_MACVLAN=m
+# CONFIG_MACVTAP is not set
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+# CONFIG_IPVTAP is not set
+CONFIG_VXLAN=m
+# CONFIG_GENEVE is not set
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+CONFIG_VETH=m
+# CONFIG_NLMON is not set
+# CONFIG_ETHERNET is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_MDIO_DEVICE is not set
+
+#
+# PCS device drivers
+#
+# end of PCS device drivers
+
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=m
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_LAN78XX is not set
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
+# CONFIG_USB_NET_CDC_MBIM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SR9700 is not set
+# CONFIG_USB_NET_SR9800 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_NET_CH9200 is not set
+# CONFIG_USB_NET_AQC111 is not set
+# CONFIG_USB_RTL8153_ECM is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+CONFIG_WLAN_VENDOR_BROADCOM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_BRCMUTIL=m
+# CONFIG_BRCMSMAC is not set
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+# CONFIG_BRCMFMAC_USB is not set
+# CONFIG_BRCM_TRACING is not set
+# CONFIG_BRCMDBG is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NET_FAILOVER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ADC=m
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ADC is not set
+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_BU21029 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
+# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
+# CONFIG_TOUCHSCREEN_EXC3000 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+# CONFIG_TOUCHSCREEN_HIDEEP is not set
+# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_ILITEK is not set
+# CONFIG_TOUCHSCREEN_S6SY761 is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_EKTF2127 is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
+# CONFIG_TOUCHSCREEN_MSG2638 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_RM_TS is not set
+# CONFIG_TOUCHSCREEN_SILEAD is not set
+# CONFIG_TOUCHSCREEN_SIS_I2C is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_STMFTS is not set
+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZET6223 is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
+# CONFIG_TOUCHSCREEN_IQS5XX is not set
+# CONFIG_TOUCHSCREEN_ZINITIX is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_PWM_VIBRA is not set
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_INPUT_WS8100_PEN=m
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_LDISC_AUTOLOAD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_SPRD is not set
+# CONFIG_SERIAL_SUNPLUS is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NULL_TTY is not set
+# CONFIG_HVC_DCC is not set
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_DEVMEM=y
+# CONFIG_TCG_TPM is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+# end of I2C Algorithms
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CADENCE is not set
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_RK3X=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MEM is not set
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+CONFIG_SPI_ROCKCHIP=y
+# CONFIG_SPI_ROCKCHIP_SFC is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+# CONFIG_SPI_MUX is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_RK805 is not set
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_CADENCE is not set
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_LOGICVC is not set
+# CONFIG_GPIO_MB86S7X is not set
+# CONFIG_GPIO_PL061 is not set
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SAMA5D2_PIOBU is not set
+# CONFIG_GPIO_SIFIVE is not set
+# CONFIG_GPIO_SYSCON is not set
+# CONFIG_GPIO_XGENE is not set
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCA9570 is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_TPIC2810 is not set
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+# end of MFD GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+# CONFIG_W1 is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_BRCMSTB is not set
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_XGENE is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+# CONFIG_SYSCON_REBOOT_MODE is not set
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_GENERIC_ADC_BATTERY is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_BQ256XX is not set
+CONFIG_CHARGER_RK817=y
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_BATTERY_UG3105 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+# CONFIG_SENSORS_ARM_SCMI is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FTSTEUTATES is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IIO_HWMON is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_PWM_FAN is not set
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP464 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_THERMAL_EMULATION=y
+# CONFIG_THERMAL_MMIO is not set
+CONFIG_ROCKCHIP_THERMAL=y
+# CONFIG_GENERIC_ADC_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG_SYSFS=y
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_GPIO_WATCHDOG is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_ARM_SBSA_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_MEN_A21_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+CONFIG_MFD_RK808=y
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# CONFIG_MFD_KHADAS_MCU is not set
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+CONFIG_REGULATOR_FAN53555=y
+# CONFIG_REGULATOR_FAN53880 is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+# CONFIG_REGULATOR_PWM is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY7636A is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+CONFIG_REGULATOR_TPS65185=m
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_VCTRL is not set
+# CONFIG_RC_CORE is not set
+
+#
+# CEC support
+#
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=m
+# CONFIG_MEDIA_SUPPORT_FILTER is not set
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+# end of Media device types
+
+#
+# Media core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=m
+# end of Media core support
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+# CONFIG_V4L2_FLASH_LED_CLASS is not set
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+# CONFIG_MEDIA_CONTROLLER_DVB is not set
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+# CONFIG_DVB_MMAP is not set
+# CONFIG_DVB_NET is not set
+CONFIG_DVB_MAX_ADAPTERS=16
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+# CONFIG_SDR_PLATFORM_DRIVERS is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+# CONFIG_DVB_TEST_DRIVERS is not set
+# end of Media drivers
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA1997X is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS3308 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_UDA1342 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_SONY_BTF_MPX is not set
+# end of Audio decoders, processors and mixers
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+# end of RDS decoders
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_ADV748X is not set
+# CONFIG_VIDEO_ADV7604 is not set
+# CONFIG_VIDEO_ADV7842 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_ML86V7667 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_TC358743 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_TW2804 is not set
+# CONFIG_VIDEO_TW9903 is not set
+# CONFIG_VIDEO_TW9906 is not set
+# CONFIG_VIDEO_TW9910 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+# end of Video decoders
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_ADV7511 is not set
+# CONFIG_VIDEO_AD9389B is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_THS8200 is not set
+# end of Video encoders
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# end of Video improvement chips
+
+#
+# Audio/Video compression chips
+#
+# CONFIG_VIDEO_SAA6752HS is not set
+# end of Audio/Video compression chips
+
+#
+# SDR tuner chips
+#
+# CONFIG_SDR_MAX2175 is not set
+# end of SDR tuner chips
+
+#
+# Miscellaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_I2C is not set
+# CONFIG_VIDEO_ST_MIPID02 is not set
+# end of Miscellaneous helper chips
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
+# CONFIG_VIDEO_HI847 is not set
+# CONFIG_VIDEO_IMX208 is not set
+# CONFIG_VIDEO_IMX214 is not set
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_IMX258 is not set
+# CONFIG_VIDEO_IMX274 is not set
+# CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX319 is not set
+# CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
+# CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
+# CONFIG_VIDEO_OV02A10 is not set
+# CONFIG_VIDEO_OV08D10 is not set
+# CONFIG_VIDEO_OV2640 is not set
+# CONFIG_VIDEO_OV2659 is not set
+# CONFIG_VIDEO_OV2680 is not set
+# CONFIG_VIDEO_OV2685 is not set
+# CONFIG_VIDEO_OV5640 is not set
+# CONFIG_VIDEO_OV5645 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV5648 is not set
+# CONFIG_VIDEO_OV6650 is not set
+# CONFIG_VIDEO_OV5670 is not set
+# CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
+# CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV7251 is not set
+# CONFIG_VIDEO_OV772X is not set
+# CONFIG_VIDEO_OV7640 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_OV7740 is not set
+# CONFIG_VIDEO_OV8856 is not set
+# CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9282 is not set
+# CONFIG_VIDEO_OV9640 is not set
+# CONFIG_VIDEO_OV9650 is not set
+# CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_MT9M001 is not set
+# CONFIG_VIDEO_MT9M032 is not set
+# CONFIG_VIDEO_MT9M111 is not set
+# CONFIG_VIDEO_MT9P031 is not set
+# CONFIG_VIDEO_MT9T001 is not set
+# CONFIG_VIDEO_MT9T112 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_MT9V032 is not set
+# CONFIG_VIDEO_MT9V111 is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_M5MOLS is not set
+# CONFIG_VIDEO_RDACM20 is not set
+# CONFIG_VIDEO_RDACM21 is not set
+# CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_S5K6AA is not set
+# CONFIG_VIDEO_S5K6A3 is not set
+# CONFIG_VIDEO_S5K4ECGX is not set
+# CONFIG_VIDEO_S5K5BAF is not set
+# CONFIG_VIDEO_CCS is not set
+# CONFIG_VIDEO_ET8EK8 is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# end of Camera sensor devices
+
+#
+# Lens drivers
+#
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# end of Lens drivers
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# end of Flash devices
+
+#
+# SPI helper chips
+#
+# CONFIG_VIDEO_GS1662 is not set
+# end of SPI helper chips
+
+#
+# Media SPI Adapters
+#
+# CONFIG_CXD2880_SPI_DRV is not set
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=m
+
+#
+# Customize TV tuners
+#
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+# end of Customize TV tuners
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6100 is not set
+# CONFIG_DVB_STV090x is not set
+# CONFIG_DVB_STV0910 is not set
+# CONFIG_DVB_STV6110x is not set
+# CONFIG_DVB_STV6111 is not set
+# CONFIG_DVB_MXL5XX is not set
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+# CONFIG_DVB_DRXK is not set
+# CONFIG_DVB_TDA18271C2DD is not set
+# CONFIG_DVB_SI2165 is not set
+# CONFIG_DVB_MN88472 is not set
+# CONFIG_DVB_MN88473 is not set
+
+#
+# DVB-S (satellite) frontends
+#
+# CONFIG_DVB_CX24110 is not set
+# CONFIG_DVB_CX24123 is not set
+# CONFIG_DVB_MT312 is not set
+# CONFIG_DVB_ZL10036 is not set
+# CONFIG_DVB_ZL10039 is not set
+# CONFIG_DVB_S5H1420 is not set
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+# CONFIG_DVB_STV0299 is not set
+# CONFIG_DVB_STV6110 is not set
+# CONFIG_DVB_STV0900 is not set
+# CONFIG_DVB_TDA8083 is not set
+# CONFIG_DVB_TDA10086 is not set
+# CONFIG_DVB_TDA8261 is not set
+# CONFIG_DVB_VES1X93 is not set
+# CONFIG_DVB_TUNER_ITD1000 is not set
+# CONFIG_DVB_TUNER_CX24113 is not set
+# CONFIG_DVB_TDA826X is not set
+# CONFIG_DVB_TUA6100 is not set
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_CX24117 is not set
+# CONFIG_DVB_CX24120 is not set
+# CONFIG_DVB_SI21XX is not set
+# CONFIG_DVB_TS2020 is not set
+# CONFIG_DVB_DS3000 is not set
+# CONFIG_DVB_MB86A16 is not set
+# CONFIG_DVB_TDA10071 is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+# CONFIG_DVB_SP887X is not set
+# CONFIG_DVB_CX22700 is not set
+# CONFIG_DVB_CX22702 is not set
+# CONFIG_DVB_S5H1432 is not set
+# CONFIG_DVB_DRXD is not set
+# CONFIG_DVB_L64781 is not set
+# CONFIG_DVB_TDA1004X is not set
+# CONFIG_DVB_NXT6000 is not set
+# CONFIG_DVB_MT352 is not set
+# CONFIG_DVB_ZL10353 is not set
+# CONFIG_DVB_DIB3000MB is not set
+# CONFIG_DVB_DIB3000MC is not set
+# CONFIG_DVB_DIB7000M is not set
+# CONFIG_DVB_DIB7000P is not set
+# CONFIG_DVB_DIB9000 is not set
+# CONFIG_DVB_TDA10048 is not set
+# CONFIG_DVB_EC100 is not set
+# CONFIG_DVB_STV0367 is not set
+# CONFIG_DVB_CXD2820R is not set
+# CONFIG_DVB_CXD2841ER is not set
+# CONFIG_DVB_ZD1301_DEMOD is not set
+# CONFIG_DVB_CXD2880 is not set
+
+#
+# DVB-C (cable) frontends
+#
+# CONFIG_DVB_VES1820 is not set
+# CONFIG_DVB_TDA10021 is not set
+# CONFIG_DVB_TDA10023 is not set
+# CONFIG_DVB_STV0297 is not set
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+# CONFIG_DVB_NXT200X is not set
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+# CONFIG_DVB_BCM3510 is not set
+# CONFIG_DVB_LGDT330X is not set
+# CONFIG_DVB_LGDT3305 is not set
+# CONFIG_DVB_LG2160 is not set
+# CONFIG_DVB_S5H1409 is not set
+# CONFIG_DVB_AU8522_DTV is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_S5H1411 is not set
+# CONFIG_DVB_MXL692 is not set
+
+#
+# ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_S921 is not set
+# CONFIG_DVB_DIB8000 is not set
+# CONFIG_DVB_MB86A20S is not set
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_TC90522 is not set
+# CONFIG_DVB_MN88443X is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+# CONFIG_DVB_PLL is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+
+#
+# SEC control devices for DVB-S
+#
+# CONFIG_DVB_DRX39XYJ is not set
+# CONFIG_DVB_LNBH25 is not set
+# CONFIG_DVB_LNBH29 is not set
+# CONFIG_DVB_LNBP21 is not set
+# CONFIG_DVB_LNBP22 is not set
+# CONFIG_DVB_ISL6405 is not set
+# CONFIG_DVB_ISL6421 is not set
+# CONFIG_DVB_ISL6423 is not set
+# CONFIG_DVB_A8293 is not set
+# CONFIG_DVB_LGS8GL5 is not set
+# CONFIG_DVB_LGS8GXX is not set
+# CONFIG_DVB_ATBM8830 is not set
+# CONFIG_DVB_TDA665x is not set
+# CONFIG_DVB_IX2505V is not set
+# CONFIG_DVB_M88RS2000 is not set
+# CONFIG_DVB_AF9033 is not set
+# CONFIG_DVB_HORUS3A is not set
+# CONFIG_DVB_ASCOT2E is not set
+# CONFIG_DVB_HELENE is not set
+
+#
+# Common Interface (EN50221) controller drivers
+#
+# CONFIG_DVB_CXD2099 is not set
+# CONFIG_DVB_SP2 is not set
+# end of Customise DVB Frontends
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_DRM=m
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=m
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_EPD_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_SCHED=m
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_HDLCD is not set
+# CONFIG_DRM_MALI_DISPLAY is not set
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_ROCKCHIP is not set
+CONFIG_DRM_ROCKCHIP_EBC=m
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+CONFIG_DRM_PANEL_SIMPLE=m
+# CONFIG_DRM_PANEL_EDP is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_SIMPLE_BRIDGE is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_HISI_KIRIN is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_LIMA is not set
+CONFIG_DRM_PANFROST=m
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_SSD130X is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
+CONFIG_DRM_NOMODESET=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_EFI is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SSD1307 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_PWM is not set
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_LM3630A=y
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_LED is not set
+# end of Backlight & LCD device support
+
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_OSSEMUL is not set
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+# CONFIG_SND_CTL_VALIDATION is not set
+# CONFIG_SND_JACK_INJECTION_DEBUG is not set
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_DRIVERS is not set
+
+#
+# HD-Audio
+#
+# end of HD-Audio
+
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_USB_HIFACE is not set
+# CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_USB_POD is not set
+# CONFIG_SND_USB_PODHD is not set
+# CONFIG_SND_USB_TONEPORT is not set
+# CONFIG_SND_USB_VARIAX is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_ADI is not set
+# CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_AUDMIX is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_FSL_MICFIL is not set
+# CONFIG_SND_SOC_FSL_XCVR is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# end of SoC Audio for Freescale CPUs
+
+# CONFIG_SND_I2S_HI6210_I2S is not set
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+CONFIG_SND_SOC_ROCKCHIP=m
+# CONFIG_SND_SOC_ROCKCHIP_I2S is not set
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
+# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
+# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
+# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set
+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+
+#
+# CODEC drivers
+#
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4613 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+CONFIG_SND_SOC_BT_SCO=m
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+CONFIG_SND_SOC_DMIC=m
+# CONFIG_SND_SOC_ES7134 is not set
+# CONFIG_SND_SOC_ES7241 is not set
+# CONFIG_SND_SOC_ES8316 is not set
+# CONFIG_SND_SOC_ES8328_I2C is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+# CONFIG_SND_SOC_MAX98357A is not set
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+# CONFIG_SND_SOC_MAX98927 is not set
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_I2C is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM5102A is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_RK3328 is not set
+CONFIG_SND_SOC_RK817=m
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+# CONFIG_SND_SOC_RT5659 is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SGTL5000 is not set
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+# CONFIG_SND_SOC_SIMPLE_MUX is not set
+# CONFIG_SND_SOC_SPDIF is not set
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS5805M is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731 is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SND_SOC_WM8904 is not set
+# CONFIG_SND_SOC_WM8960 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SIMPLE_CARD=m
+# CONFIG_SND_AUDIO_GRAPH_CARD is not set
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_ASUS is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_BIGBEN_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CORSAIR is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CP2112 is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELAN is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_FT260 is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_GLORIOUS is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_XIAOMI is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LED is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_REDRAGON is not set
+CONFIG_HID_MICROSOFT=y
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NINTENDO is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PLAYSTATION is not set
+# CONFIG_HID_RAZER is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SEMITEK is not set
+# CONFIG_HID_SIGMAMICRO is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# CONFIG_HID_MCP2221 is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+# end of USB HID support
+
+#
+# I2C HID support
+#
+CONFIG_I2C_HID_OF=m
+CONFIG_I2C_HID_OF_GOODIX=m
+# end of I2C HID support
+
+CONFIG_I2C_HID_CORE=m
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_LED_TRIG=y
+# CONFIG_USB_ULPI_BUS is not set
+# CONFIG_USB_CONN_GPIO is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+CONFIG_USB_LEDS_TRIGGER_USBPORT=y
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=m
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_MUSB_HDRC is not set
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_HOST is not set
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+#
+# Platform Glue Driver Support
+#
+CONFIG_USB_DWC3_OF_SIMPLE=y
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_ULPI is not set
+# end of USB Physical Layer drivers
+
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_U_SERIAL_CONSOLE is not set
+
+#
+# USB Peripheral Controller
+#
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_SNP_UDC_PLAT is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_BDC_UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_DUMMY_HCD is not set
+# end of USB Peripheral Controller
+
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+# CONFIG_USB_CONFIGFS_OBEX is not set
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+# CONFIG_USB_CONFIGFS_RNDIS is not set
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+# CONFIG_USB_CONFIGFS_F_LB_SS is not set
+# CONFIG_USB_CONFIGFS_F_FS is not set
+CONFIG_USB_CONFIGFS_F_UAC1=y
+# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
+CONFIG_USB_CONFIGFS_F_UAC2=y
+# CONFIG_USB_CONFIGFS_F_MIDI is not set
+CONFIG_USB_CONFIGFS_F_HID=y
+# CONFIG_USB_CONFIGFS_F_UVC is not set
+# CONFIG_USB_CONFIGFS_F_PRINTER is not set
+
+#
+# USB Gadget precomposed configurations
+#
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_ACM_MS is not set
+CONFIG_USB_G_MULTI=m
+# CONFIG_USB_G_MULTI_RNDIS is not set
+CONFIG_USB_G_MULTI_CDC=y
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_USB_RAW_GADGET is not set
+# end of USB Gadget precomposed configurations
+
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_TCPM is not set
+# CONFIG_TYPEC_UCSI is not set
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_WUSB3801=m
+
+#
+# USB Type-C Multiplexer/DeMultiplexer Switch support
+#
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# end of USB Type-C Multiplexer/DeMultiplexer Switch support
+
+#
+# USB Type-C Alternate Mode drivers
+#
+# CONFIG_TYPEC_DP_ALTMODE is not set
+# end of USB Type-C Alternate Mode drivers
+
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_OF_ASPEED is not set
+# CONFIG_MMC_SDHCI_OF_AT91 is not set
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_CADENCE is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MMC_SDHCI_XENON is not set
+# CONFIG_MMC_SDHCI_OMAP is not set
+# CONFIG_MMC_SDHCI_AM654 is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_CLASS_MULTICOLOR=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_EL15203000 is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+# CONFIG_LEDS_SYSCON is not set
+# CONFIG_LEDS_MLXREG is not set
+# CONFIG_LEDS_USER is not set
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+
+#
+# Flash and Torch LED drivers
+#
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PATTERN=y
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_TTY=y
+
+#
+# Simple LED drivers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_RK808=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_EFI is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_ZYNQMP is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_BCM_SBA_RAID is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_MV_XOR_V2 is not set
+CONFIG_PL330_DMA=y
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_SF_PDMA is not set
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VFIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VDPA is not set
+# CONFIG_VHOST_MENU is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+# CONFIG_PRISM2_USB is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_RTL8723BS is not set
+# CONFIG_R8712U is not set
+# CONFIG_R8188EU is not set
+# CONFIG_VT6656 is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16240 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7816 is not set
+# end of Analog to digital converters
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+# end of Analog digital bi-direction converters
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7746 is not set
+# end of Capacitance to digital converters
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# end of Direct Digital Synthesis
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+# end of Network Analyzer, Impedance Converters
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7854 is not set
+# end of Active energy metering IC
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S1210 is not set
+# end of Resolver to digital converters
+# end of IIO staging drivers
+
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+
+#
+# Android
+#
+# end of Android
+
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_KS7010 is not set
+# CONFIG_PI433 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_WFX is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCMI=y
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+# CONFIG_COMMON_CLK_PWM is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_COMMON_CLK_ROCKCHIP=y
+# CONFIG_CLK_PX30 is not set
+# CONFIG_CLK_RK3308 is not set
+# CONFIG_CLK_RK3328 is not set
+# CONFIG_CLK_RK3368 is not set
+# CONFIG_CLK_RK3399 is not set
+CONFIG_CLK_RK3568=y
+# CONFIG_XILINX_VCU is not set
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_FSL_ERRATUM_A008585 is not set
+# CONFIG_HISILICON_ERRATUM_161010101 is not set
+# CONFIG_ARM64_ERRATUM_858921 is not set
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+# CONFIG_ARM_MHU is not set
+# CONFIG_ARM_MHU_V2 is not set
+# CONFIG_PLATFORM_MHU is not set
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_OF_IOMMU=y
+CONFIG_IOMMU_DMA=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SMMU_V3 is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# end of Enable LiteX SoC Builder specific drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_ROCKCHIP_SUSPEND_MODE=y
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+# CONFIG_EXTCON_ADC_JACK is not set
+# CONFIG_EXTCON_FSA9480 is not set
+# CONFIG_EXTCON_GPIO is not set
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+# CONFIG_EXTCON_USB_GPIO is not set
+# CONFIG_EXTCON_USBC_TUSB320 is not set
+# CONFIG_MEMORY is not set
+CONFIG_IIO=m
+CONFIG_IIO_BUFFER=y
+# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_CONFIGFS=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+# CONFIG_IIO_SW_DEVICE is not set
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
+# CONFIG_ADXL345_I2C is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
+# CONFIG_ADXL367_SPI is not set
+# CONFIG_ADXL367_I2C is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXL372_I2C is not set
+# CONFIG_BMA180 is not set
+# CONFIG_BMA220 is not set
+# CONFIG_BMA400 is not set
+# CONFIG_BMC150_ACCEL is not set
+# CONFIG_BMI088_ACCEL is not set
+# CONFIG_DA280 is not set
+# CONFIG_DA311 is not set
+# CONFIG_DMARD06 is not set
+# CONFIG_DMARD09 is not set
+# CONFIG_DMARD10 is not set
+# CONFIG_FXLS8962AF_I2C is not set
+# CONFIG_FXLS8962AF_SPI is not set
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+# CONFIG_KXSD9 is not set
+# CONFIG_KXCJK1013 is not set
+# CONFIG_MC3230 is not set
+# CONFIG_MMA7455_I2C is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMA7660 is not set
+# CONFIG_MMA8452 is not set
+# CONFIG_MMA9551 is not set
+# CONFIG_MMA9553 is not set
+# CONFIG_MXC4005 is not set
+# CONFIG_MXC6255 is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SCA3300 is not set
+# CONFIG_STK8312 is not set
+# CONFIG_STK8BA50 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7091R5 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7280 is not set
+# CONFIG_AD7291 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606_IFACE_PARALLEL is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD799X is not set
+# CONFIG_ADI_AXI_ADC is not set
+# CONFIG_CC10001_ADC is not set
+# CONFIG_ENVELOPE_DETECTOR is not set
+# CONFIG_HI8435 is not set
+# CONFIG_HX711 is not set
+# CONFIG_INA2XX_ADC is not set
+# CONFIG_LTC2471 is not set
+# CONFIG_LTC2485 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2497 is not set
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX1363 is not set
+# CONFIG_MAX9611 is not set
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3422 is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_NAU7802 is not set
+CONFIG_ROCKCHIP_SARADC=m
+# CONFIG_SD_ADC_MODULATOR is not set
+# CONFIG_TI_ADC081C is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS1015 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS131E08 is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_TI_TSC2046 is not set
+# CONFIG_VF610_ADC is not set
+# CONFIG_XILINX_XADC is not set
+# end of Analog to digital converters
+
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
+# Analog Front Ends
+#
+# CONFIG_IIO_RESCALE is not set
+# end of Analog Front Ends
+
+#
+# Amplifiers
+#
+# CONFIG_AD8366 is not set
+# CONFIG_ADA4250 is not set
+# CONFIG_HMC425 is not set
+# end of Amplifiers
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# end of Capacitance to digital converters
+
+#
+# Chemical Sensors
+#
+# CONFIG_ATLAS_PH_SENSOR is not set
+# CONFIG_ATLAS_EZO_SENSOR is not set
+# CONFIG_BME680 is not set
+# CONFIG_CCS811 is not set
+# CONFIG_IAQCORE is not set
+# CONFIG_PMS7003 is not set
+# CONFIG_SCD30_CORE is not set
+# CONFIG_SCD4X is not set
+# CONFIG_SENSIRION_SGP30 is not set
+# CONFIG_SENSIRION_SGP40 is not set
+# CONFIG_SPS30_I2C is not set
+# CONFIG_SPS30_SERIAL is not set
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
+# CONFIG_VZ89X is not set
+# end of Chemical Sensors
+
+#
+# Hid Sensor IIO Common
+#
+# end of Hid Sensor IIO Common
+
+#
+# IIO SCMI Sensors
+#
+# CONFIG_IIO_SCMI is not set
+# end of IIO SCMI Sensors
+
+#
+# SSP Sensor Common
+#
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# end of SSP Sensor Common
+
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD3552R is not set
+# CONFIG_AD5064 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5593R is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_LTC2688 is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5696_I2C is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5766 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_DPOT_DAC is not set
+# CONFIG_DS4424 is not set
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_M62332 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MAX5821 is not set
+# CONFIG_MCP4725 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC5571 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_VF610_DAC is not set
+# end of Digital to analog converters
+
+#
+# IIO dummy driver
+#
+# end of IIO dummy driver
+
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+# CONFIG_AD9523 is not set
+# end of Clock Generator/Distribution
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADMV1014 is not set
+# CONFIG_ADMV4420 is not set
+# CONFIG_ADRF6780 is not set
+# end of Phase-Locked Loop (PLL) frequency synthesizers
+# end of Frequency Synthesizers DDS/PLL
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_BMG160 is not set
+# CONFIG_FXAS21002C is not set
+# CONFIG_MPU3050_I2C is not set
+# CONFIG_IIO_ST_GYRO_3AXIS is not set
+# CONFIG_ITG3200 is not set
+# end of Digital gyroscope sensors
+
+#
+# Health Sensors
+#
+
+#
+# Heart Rate Monitors
+#
+# CONFIG_AFE4403 is not set
+# CONFIG_AFE4404 is not set
+# CONFIG_MAX30100 is not set
+# CONFIG_MAX30102 is not set
+# end of Heart Rate Monitors
+# end of Health Sensors
+
+#
+# Humidity sensors
+#
+# CONFIG_AM2315 is not set
+# CONFIG_DHT11 is not set
+# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
+# CONFIG_HTS221 is not set
+# CONFIG_HTU21 is not set
+# CONFIG_SI7005 is not set
+# CONFIG_SI7020 is not set
+# end of Humidity sensors
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_BMI160_I2C is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_FXOS8700_I2C is not set
+# CONFIG_FXOS8700_SPI is not set
+# CONFIG_KMX61 is not set
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_I2C is not set
+# CONFIG_INV_MPU6050_SPI is not set
+# CONFIG_IIO_ST_LSM6DSX is not set
+# CONFIG_IIO_ST_LSM9DS0 is not set
+# end of Inertial measurement units
+
+#
+# Light sensors
+#
+# CONFIG_ADJD_S311 is not set
+# CONFIG_ADUX1020 is not set
+# CONFIG_AL3010 is not set
+# CONFIG_AL3320A is not set
+# CONFIG_APDS9300 is not set
+# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
+# CONFIG_BH1750 is not set
+# CONFIG_BH1780 is not set
+# CONFIG_CM32181 is not set
+# CONFIG_CM3232 is not set
+# CONFIG_CM3323 is not set
+# CONFIG_CM3605 is not set
+# CONFIG_CM36651 is not set
+# CONFIG_GP2AP002 is not set
+# CONFIG_GP2AP020A00F is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_ISL29125 is not set
+# CONFIG_JSA1212 is not set
+# CONFIG_RPR0521 is not set
+# CONFIG_LTR501 is not set
+# CONFIG_LV0104CS is not set
+# CONFIG_MAX44000 is not set
+# CONFIG_MAX44009 is not set
+# CONFIG_NOA1305 is not set
+# CONFIG_OPT3001 is not set
+# CONFIG_PA12203001 is not set
+# CONFIG_SI1133 is not set
+# CONFIG_SI1145 is not set
+# CONFIG_STK3310 is not set
+# CONFIG_ST_UVIS25 is not set
+# CONFIG_TCS3414 is not set
+# CONFIG_TCS3472 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TSL2591 is not set
+# CONFIG_TSL2772 is not set
+# CONFIG_TSL4531 is not set
+# CONFIG_US5182D is not set
+# CONFIG_VCNL4000 is not set
+# CONFIG_VCNL4035 is not set
+# CONFIG_VEML6030 is not set
+# CONFIG_VEML6070 is not set
+# CONFIG_VL6180 is not set
+# CONFIG_ZOPT2201 is not set
+# end of Light sensors
+
+#
+# Magnetometer sensors
+#
+# CONFIG_AK8974 is not set
+# CONFIG_AK8975 is not set
+# CONFIG_AK09911 is not set
+# CONFIG_BMC150_MAGN_I2C is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_MAG3110 is not set
+# CONFIG_MMC35240 is not set
+# CONFIG_IIO_ST_MAGN_3AXIS is not set
+# CONFIG_SENSORS_HMC5843_I2C is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_RM3100_I2C is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_YAMAHA_YAS530 is not set
+# end of Magnetometer sensors
+
+#
+# Multiplexers
+#
+# CONFIG_IIO_MUX is not set
+# end of Multiplexers
+
+#
+# Inclinometer sensors
+#
+# end of Inclinometer sensors
+
+#
+# Triggers - standalone
+#
+# CONFIG_IIO_HRTIMER_TRIGGER is not set
+# CONFIG_IIO_INTERRUPT_TRIGGER is not set
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+# CONFIG_IIO_SYSFS_TRIGGER is not set
+# end of Triggers - standalone
+
+#
+# Linear and angular position sensors
+#
+# end of Linear and angular position sensors
+
+#
+# Digital potentiometers
+#
+# CONFIG_AD5110 is not set
+# CONFIG_AD5272 is not set
+# CONFIG_DS1803 is not set
+# CONFIG_MAX5432 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MCP4018 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4531 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_TPL0102 is not set
+# end of Digital potentiometers
+
+#
+# Digital potentiostats
+#
+# CONFIG_LMP91000 is not set
+# end of Digital potentiostats
+
+#
+# Pressure sensors
+#
+# CONFIG_ABP060MG is not set
+# CONFIG_BMP280 is not set
+# CONFIG_DLHL60D is not set
+# CONFIG_DPS310 is not set
+# CONFIG_HP03 is not set
+# CONFIG_ICP10100 is not set
+# CONFIG_MPL115_I2C is not set
+# CONFIG_MPL115_SPI is not set
+# CONFIG_MPL3115 is not set
+# CONFIG_MS5611 is not set
+# CONFIG_MS5637 is not set
+# CONFIG_IIO_ST_PRESS is not set
+# CONFIG_T5403 is not set
+# CONFIG_HP206C is not set
+# CONFIG_ZPA2326 is not set
+# end of Pressure sensors
+
+#
+# Lightning sensors
+#
+# CONFIG_AS3935 is not set
+# end of Lightning sensors
+
+#
+# Proximity and distance sensors
+#
+# CONFIG_ISL29501 is not set
+# CONFIG_LIDAR_LITE_V2 is not set
+# CONFIG_MB1232 is not set
+# CONFIG_PING is not set
+# CONFIG_RFD77402 is not set
+# CONFIG_SRF04 is not set
+# CONFIG_SX9310 is not set
+# CONFIG_SX9324 is not set
+# CONFIG_SX9360 is not set
+# CONFIG_SX9500 is not set
+# CONFIG_SRF08 is not set
+# CONFIG_VCNL3020 is not set
+# CONFIG_VL53L0X_I2C is not set
+# end of Proximity and distance sensors
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1200 is not set
+# end of Resolver to digital converters
+
+#
+# Temperature sensors
+#
+# CONFIG_LTC2983 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MLX90614 is not set
+# CONFIG_MLX90632 is not set
+# CONFIG_TMP006 is not set
+# CONFIG_TMP007 is not set
+# CONFIG_TMP117 is not set
+# CONFIG_TSYS01 is not set
+# CONFIG_TSYS02D is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX31865 is not set
+# end of Temperature sensors
+
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+# CONFIG_AL_FIC is not set
+CONFIG_PARTITION_PERCPU=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_SCMI is not set
+# CONFIG_RESET_TI_SYSCON is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+
+#
+# PHY drivers for Broadcom platforms
+#
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+# CONFIG_PHY_ROCKCHIP_EMMC is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+# CONFIG_PHY_ROCKCHIP_PCIE is not set
+# CONFIG_PHY_ROCKCHIP_TYPEC is not set
+# CONFIG_PHY_ROCKCHIP_USB is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# CONFIG_ARM_CCI_PMU is not set
+# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
+CONFIG_ARM_PMU=y
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_SPE_PMU is not set
+# end of Performance monitor support
+
+# CONFIG_RAS is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+# CONFIG_DAX is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_OTP=y
+# CONFIG_NVMEM_RMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# CONFIG_PECI is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_SUPPORT_V4 is not set
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_ONLINE_SCRUB is not set
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+# CONFIG_F2FS_FS_COMPRESSION is not set
+CONFIG_F2FS_IOSTAT=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+# CONFIG_VIRTIO_FS is not set
+CONFIG_OVERLAY_FS=m
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_INDEX is not set
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+# CONFIG_OVERLAY_FS_METACOPY is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_EXFAT_FS=m
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+# CONFIG_NTFS_FS is not set
+CONFIG_NTFS3_FS=m
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+# CONFIG_NTFS3_LZX_XPRESS is not set
+# CONFIG_NTFS3_FS_POSIX_ACL is not set
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+# end of Pseudo filesystems
+
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+CONFIG_UNICODE=y
+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM=""
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Public-key cryptography
+#
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_DH is not set
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_ECHAINIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ESSIV is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_BLAKE2B=m
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD160 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+
+#
+# Certificates for signature checking
+#
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+# CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_XXHASH=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_ZSTD_COMPRESS=m
+CONFIG_ZSTD_DECOMPRESS=y
+# CONFIG_XZ_DEC is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_RESTRICTED_POOL is not set
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_CMA=y
+# CONFIG_DMA_PERNUMA_CMA is not set
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_LIBFDT=y
+CONFIG_UCS2_STRING=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_SBITMAP=y
+# end of Library routines
+
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_MISC is not set
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_NONE is not set
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+CONFIG_DEBUG_INFO_DWARF5=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_DEBUG_INFO_COMPRESSED is not set
+# CONFIG_GDB_SCRIPTS is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+# end of Generic Kernel Debugging Instruments
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_PAGE_REF is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_ON_OOPS_VALUE=1
+CONFIG_PANIC_TIMEOUT=1
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHEDSTATS=y
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=21000
+CONFIG_RCU_TRACE=y
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+CONFIG_CPU_HOTPLUG_STATE_CONTROL=y
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_BOOTTIME_TRACING is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_OSNOISE_TRACER is not set
+# CONFIG_TIMERLAT_TRACER is not set
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_UPROBE_EVENTS is not set
+# CONFIG_SYNTH_EVENTS is not set
+# CONFIG_USER_EVENTS is not set
+# CONFIG_HIST_TRIGGERS is not set
+# CONFIG_TRACE_EVENT_INJECT is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_TRACE_EVAL_MAP_FILE is not set
+# CONFIG_RING_BUFFER_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_STRICT_DEVMEM is not set
+
+#
+# arm64 Debugging
+#
+# CONFIG_DEBUG_AID_FOR_SYZBOT is not set
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_DEBUG_EFI is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_CORESIGHT is not set
+# end of arm64 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_ARCH_USE_MEMTEST=y
+# CONFIG_MEMTEST is not set
+# end of Kernel Testing and Coverage
+
+#
+# Rust hacking
+#
+# end of Rust hacking
+# end of Kernel hacking
diff --git a/nongnu/configs/quartz64_defconfig b/nongnu/configs/quartz64_defconfig
new file mode 100644
index 0000000..39c7f65
--- /dev/null
+++ b/nongnu/configs/quartz64_defconfig
@@ -0,0 +1,7916 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 6.1.0-rc1 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 10.3.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=100300
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=23700
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=23700
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_PAHOLE_VERSION=0
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_DEBUGFS=y
+# end of IRQ subsystem
+
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BPF_JIT=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+# end of BPF subsystem
+
+CONFIG_PREEMPT_BUILD=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+# CONFIG_SCHED_CORE is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_SCHED_AVG_IRQ=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKS_RUDE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_GCC12_NO_ARRAY_BOUNDS=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+# CONFIG_CGROUP_FAVOR_DYNMODS is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_CGROUP_PIDS=y
+# CONFIG_CGROUP_RDMA is not set
+# CONFIG_CGROUP_FREEZER is not set
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_MISC=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_ZSTD=y
+CONFIG_BOOT_CONFIG=y
+# CONFIG_BOOT_CONFIG_EMBED is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_EXPERT is not set
+CONFIG_MULTIUSER=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_GUEST_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# end of General setup
+
+CONFIG_ARM64=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_SMP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+
+#
+# Platform selection
+#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_BCM is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_NXP is not set
+# CONFIG_ARCH_NPCM is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# end of Platform selection
+
+#
+# Kernel Features
+#
+
+#
+# ARM errata workarounds via the alternatives framework
+#
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+# end of ARM errata workarounds via the alternatives framework
+
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+CONFIG_ARM64_VA_BITS_39=y
+# CONFIG_ARM64_VA_BITS_48 is not set
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SCHED_MC=y
+# CONFIG_SCHED_CLUSTER is not set
+CONFIG_SCHED_SMT=y
+CONFIG_NR_CPUS=256
+CONFIG_HOTPLUG_CPU=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=4
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_PARAVIRT=y
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_SIG is not set
+CONFIG_CRASH_DUMP=y
+CONFIG_TRANS_TABLE=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+# CONFIG_COMPAT is not set
+
+#
+# ARMv8.1 architectural features
+#
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+# end of ARMv8.1 architectural features
+
+#
+# ARMv8.2 architectural features
+#
+# CONFIG_ARM64_PMEM is not set
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+# end of ARMv8.2 architectural features
+
+#
+# ARMv8.3 architectural features
+#
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+# end of ARMv8.3 architectural features
+
+#
+# ARMv8.4 architectural features
+#
+CONFIG_ARM64_AMU_EXTN=y
+# end of ARMv8.4 architectural features
+
+#
+# ARMv8.5 architectural features
+#
+CONFIG_ARM64_BTI=y
+CONFIG_ARM64_E0PD=y
+# end of ARMv8.5 architectural features
+
+#
+# ARMv8.7 architectural features
+#
+CONFIG_ARM64_EPAN=y
+# end of ARMv8.7 architectural features
+
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_MODULE_PLTS=y
+# CONFIG_ARM64_PSEUDO_NMI is not set
+CONFIG_RELOCATABLE=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_ARCH_NR_GPIO=0
+# end of Kernel Features
+
+#
+# Boot options
+#
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
+CONFIG_CMDLINE=""
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+CONFIG_DMI=y
+# end of Boot options
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_IDLE_GOV_TEO is not set
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DT_IDLE_GENPD=y
+
+#
+# ARM CPU Idle Drivers
+#
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# end of ARM CPU Idle Drivers
+# end of CPU Idle
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+# end of CPU Frequency scaling
+# end of CPU Power Management
+
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ACPI=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_CCA_REQUIRED=y
+# CONFIG_ACPI_DEBUGGER is not set
+CONFIG_ACPI_SPCR_TABLE=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_VIDEO is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_TAD is not set
+# CONFIG_ACPI_DOCK is not set
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_CPPC_LIB=y
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_IPMI is not set
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_HED=y
+# CONFIG_ACPI_CUSTOM_METHOD is not set
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_NUMA=y
+# CONFIG_ACPI_HMAT is not set
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_SEA=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+# CONFIG_ACPI_APEI_ERST_DEBUG is not set
+# CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_GTDT=y
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PCC=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_ACPI_PRMT=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_KVM_MMIO=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+
+#
+# General architecture-dependent options
+#
+CONFIG_CRASH_CORE=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_UPROBES=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_HAVE_CONTEXT_TRACKING_USER=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_HAS_RELR=y
+CONFIG_HAVE_PREEMPT_DYNAMIC=y
+CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+# CONFIG_BLK_WBT is not set
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BLK_MQ_STACKING=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_ASN1=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ELFCORE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_ZPOOL=y
+CONFIG_SWAP=y
+CONFIG_ZSWAP=y
+CONFIG_ZSWAP_DEFAULT_ON=y
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC=y
+CONFIG_ZSWAP_ZPOOL_DEFAULT="zsmalloc"
+# CONFIG_ZBUD is not set
+# CONFIG_Z3FOLD is not set
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+
+#
+# SLAB allocator options
+#
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# end of SLAB allocator options
+
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_PAGE_REPORTING=y
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_MEMORY_FAILURE=y
+# CONFIG_HWPOISON_INJECT is not set
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_THP_SWAP=y
+# CONFIG_READ_ONLY_THP_FOR_FS is not set
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_FRONTSWAP=y
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMA_AREAS=19
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
+# CONFIG_USERFAULTFD is not set
+# CONFIG_LRU_GEN is not set
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=m
+# CONFIG_IP_MROUTE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NET_PTP_CLASSIFY=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_BRIDGE_NETFILTER is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
+# CONFIG_NETFILTER_NETLINK_ACCT is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_OSF is not set
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_SYSLOG=m
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_ZONES is not set
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CONNTRACK_LABELS is not set
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_MASQUERADE=y
+# CONFIG_NF_TABLES is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_HL is not set
+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+CONFIG_NETFILTER_XT_NAT=m
+# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+# CONFIG_NETFILTER_XT_MATCH_BPF is not set
+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ECN is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# end of Core Netfilter Configuration
+
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+# CONFIG_NF_SOCKET_IPV4 is not set
+# CONFIG_NF_TPROXY_IPV4 is not set
+# CONFIG_NF_DUP_IPV4 is not set
+# CONFIG_NF_LOG_ARP is not set
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_RPFILTER is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+# CONFIG_IP_NF_TARGET_SYNPROXY is not set
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_SOCKET_IPV6 is not set
+# CONFIG_NF_TPROXY_IPV6 is not set
+# CONFIG_NF_DUP_IPV6 is not set
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RPFILTER is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_MATCH_SRH is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP6_NF_SECURITY is not set
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+# CONFIG_IP6_NF_TARGET_NPT is not set
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_MRP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_CFM is not set
+CONFIG_NET_DSA=m
+# CONFIG_NET_DSA_TAG_AR9331 is not set
+# CONFIG_NET_DSA_TAG_BRCM is not set
+# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set
+# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set
+# CONFIG_NET_DSA_TAG_HELLCREEK is not set
+# CONFIG_NET_DSA_TAG_GSWIP is not set
+# CONFIG_NET_DSA_TAG_DSA is not set
+# CONFIG_NET_DSA_TAG_EDSA is not set
+# CONFIG_NET_DSA_TAG_MTK is not set
+# CONFIG_NET_DSA_TAG_KSZ is not set
+# CONFIG_NET_DSA_TAG_OCELOT is not set
+# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
+# CONFIG_NET_DSA_TAG_QCA is not set
+# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_RTL8_4 is not set
+# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
+# CONFIG_NET_DSA_TAG_LAN9303 is not set
+# CONFIG_NET_DSA_TAG_SJA1105 is not set
+# CONFIG_NET_DSA_TAG_TRAILER is not set
+# CONFIG_NET_DSA_TAG_XRS700X is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_TAPRIO=m
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_MQPRIO=m
+# CONFIG_NET_SCH_SKBPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_FQ_CODEL is not set
+# CONFIG_NET_SCH_CAKE is not set
+# CONFIG_NET_SCH_FQ is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_PIE is not set
+CONFIG_NET_SCH_INGRESS=m
+# CONFIG_NET_SCH_PLUG is not set
+# CONFIG_NET_SCH_ETS is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_CLS_BPF is not set
+CONFIG_NET_CLS_FLOWER=m
+# CONFIG_NET_CLS_MATCHALL is not set
+# CONFIG_NET_EMATCH is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+CONFIG_NET_ACT_GACT=m
+# CONFIG_GACT_PROB is not set
+CONFIG_NET_ACT_MIRRED=m
+# CONFIG_NET_ACT_SAMPLE is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_ACT_CSUM is not set
+# CONFIG_NET_ACT_MPLS is not set
+# CONFIG_NET_ACT_VLAN is not set
+# CONFIG_NET_ACT_BPF is not set
+# CONFIG_NET_ACT_SKBMOD is not set
+# CONFIG_NET_ACT_IFE is not set
+# CONFIG_NET_ACT_TUNNEL_KEY is not set
+CONFIG_NET_ACT_GATE=m
+# CONFIG_NET_TC_SKB_EXT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_L3_MASTER_DEV is not set
+CONFIG_QRTR=m
+CONFIG_QRTR_TUN=m
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_GW=m
+# CONFIG_CAN_J1939 is not set
+# CONFIG_CAN_ISOTP is not set
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_LEDS=y
+CONFIG_BT_MSFTEXT=y
+# CONFIG_BT_AOSPEXT is not set
+CONFIG_BT_DEBUGFS=y
+# CONFIG_BT_SELFTEST is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+# CONFIG_BT_HCIBTUSB_BCM is not set
+# CONFIG_BT_HCIBTUSB_MTK is not set
+CONFIG_BT_HCIBTUSB_RTL=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_NOKIA is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+# CONFIG_BT_HCIUART_INTEL is not set
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+# CONFIG_BT_HCIUART_QCA is not set
+# CONFIG_BT_HCIUART_AG6XX is not set
+# CONFIG_BT_HCIUART_MRVL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_BT_MTKSDIO is not set
+# CONFIG_BT_MTKUART is not set
+# CONFIG_BT_VIRTIO is not set
+# end of Bluetooth device drivers
+
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_MCTP is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_GPIO is not set
+CONFIG_NET_9P=y
+CONFIG_NET_9P_FD=y
+CONFIG_NET_9P_VIRTIO=y
+# CONFIG_NET_9P_XEN is not set
+# CONFIG_NET_9P_DEBUG is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+CONFIG_NFC=m
+# CONFIG_NFC_DIGITAL is not set
+CONFIG_NFC_NCI=m
+# CONFIG_NFC_NCI_SPI is not set
+# CONFIG_NFC_NCI_UART is not set
+# CONFIG_NFC_HCI is not set
+
+#
+# Near Field Communication (NFC) devices
+#
+# CONFIG_NFC_VIRTUAL_NCI is not set
+# CONFIG_NFC_FDP is not set
+# CONFIG_NFC_PN533_USB is not set
+# CONFIG_NFC_PN533_I2C is not set
+# CONFIG_NFC_PN532_UART is not set
+# CONFIG_NFC_MRVL_USB is not set
+# CONFIG_NFC_ST_NCI_I2C is not set
+# CONFIG_NFC_ST_NCI_SPI is not set
+# CONFIG_NFC_NXP_NCI is not set
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN5_I2C=m
+# CONFIG_NFC_S3FWRN82_UART is not set
+# end of Near Field Communication (NFC) devices
+
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_DEVLINK=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PAGE_POOL_STATS is not set
+CONFIG_FAILOVER=y
+CONFIG_ETHTOOL_NETLINK=y
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCIE_PTM is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_PF_STUB is not set
+CONFIG_PCI_ATS=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+# CONFIG_PCI_PRI is not set
+CONFIG_PCI_PASID=y
+CONFIG_PCI_LABEL=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# PCI controller drivers
+#
+# CONFIG_PCI_FTPCI100 is not set
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCIE_XILINX is not set
+# CONFIG_PCI_XGENE is not set
+# CONFIG_PCIE_ALTERA is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+# CONFIG_PCIE_ROCKCHIP_HOST is not set
+# CONFIG_PCIE_ROCKCHIP_EP is not set
+# CONFIG_PCIE_MICROCHIP_HOST is not set
+# CONFIG_PCIE_HISI_ERR is not set
+
+#
+# DesignWare PCI Core Support
+#
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+# CONFIG_PCIE_DW_PLAT_EP is not set
+# CONFIG_PCI_HISI is not set
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+# CONFIG_PCIE_KIRIN is not set
+# CONFIG_PCI_MESON is not set
+# CONFIG_PCIE_AL is not set
+# end of DesignWare PCI Core Support
+
+#
+# Mobiveil PCIe Core Support
+#
+# end of Mobiveil PCIe Core Support
+
+#
+# Cadence PCIe controllers support
+#
+# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
+# CONFIG_PCIE_CADENCE_PLAT_EP is not set
+# CONFIG_PCI_J721E_HOST is not set
+# CONFIG_PCI_J721E_EP is not set
+# end of Cadence PCIe controllers support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
+# CONFIG_PCI_EPF_NTB is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_CXL_BUS is not set
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_AUXILIARY_BUS=y
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_LOADER_COMPRESS is not set
+CONFIG_FW_CACHE=y
+# CONFIG_FW_UPLOAD is not set
+# end of Firmware loader
+
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=m
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_ARCH_NUMA=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+CONFIG_BRCMSTB_GISB_ARB=y
+# CONFIG_MOXTET is not set
+CONFIG_VEXPRESS_CONFIG=y
+# CONFIG_MHI_BUS is not set
+# CONFIG_MHI_BUS_EP is not set
+# end of Bus devices
+
+# CONFIG_CONNECTOR is not set
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_MSG=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+# CONFIG_ARM_SCMI_POWER_CONTROL is not set
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+# CONFIG_ARM_SDE_INTERFACE is not set
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+# CONFIG_ISCSI_IBFT is not set
+# CONFIG_FW_CFG_SYSFS is not set
+CONFIG_SYSFB=y
+CONFIG_SYSFB_SIMPLEFB=y
+# CONFIG_ARM_FFA_TRANSPORT is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_VARS_PSTORE=y
+# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+CONFIG_EFI_CAPSULE_LOADER=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_UEFI_CPER=y
+CONFIG_UEFI_CPER_ARM=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+
+#
+# Partition parsers
+#
+# CONFIG_MTD_AR7_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# end of Partition parsers
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+
+#
+# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
+#
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_PARTITIONED_MASTER is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# end of RAM/ROM/Flash chip drivers
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PHYSMAP_VERSATILE is not set
+# CONFIG_MTD_PHYSMAP_GEMINI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+# end of Mapping drivers for chip access
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_MCHP48L640 is not set
+CONFIG_MTD_SST25L=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# end of Self-contained MTD device drivers
+
+#
+# NAND
+#
+CONFIG_MTD_NAND_CORE=y
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_RAW_NAND=y
+
+#
+# Raw/parallel NAND flash controllers
+#
+CONFIG_MTD_NAND_DENALI=y
+# CONFIG_MTD_NAND_DENALI_PCI is not set
+CONFIG_MTD_NAND_DENALI_DT=y
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_BRCMNAND is not set
+# CONFIG_MTD_NAND_MXIC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_CADENCE is not set
+# CONFIG_MTD_NAND_ARASAN is not set
+# CONFIG_MTD_NAND_INTEL_LGM is not set
+# CONFIG_MTD_NAND_ROCKCHIP is not set
+
+#
+# Misc
+#
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_SPI_NAND is not set
+
+#
+# ECC engine support
+#
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
+# CONFIG_MTD_NAND_ECC_SW_BCH is not set
+# CONFIG_MTD_NAND_ECC_MXIC is not set
+# end of ECC engine support
+# end of NAND
+
+#
+# LPDDR & LPDDR2 PCM memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# end of LPDDR & LPDDR2 PCM memory drivers
+
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
+CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
+# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_MTD_HYPERBUS is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_NUMA=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+CONFIG_ZRAM=y
+CONFIG_ZRAM_DEF_COMP_ZSTD=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+# CONFIG_ZRAM_WRITEBACK is not set
+CONFIG_ZRAM_MEMORY_TRACKING=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_VIRTIO_BLK=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_UBLK is not set
+
+#
+# NVME Support
+#
+CONFIG_NVME_CORE=y
+CONFIG_BLK_DEV_NVME=y
+# CONFIG_NVME_MULTIPATH is not set
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+CONFIG_NVME_HWMON=y
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_AUTH is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HI6421V600_IRQ is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_SRAM=y
+CONFIG_DW_XDATA_PCIE=y
+CONFIG_PCI_ENDPOINT_TEST=m
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_OPEN_DICE is not set
+# CONFIG_VCPU_STALL_DETECTOR is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_VMWARE_VMCI is not set
+# CONFIG_GENWQE is not set
+# CONFIG_ECHO is not set
+# CONFIG_BCM_VK is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_HABANA_AI is not set
+CONFIG_UACCE=m
+# CONFIG_PVPANIC is not set
+# CONFIG_GP_PCI1XXXX is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+CONFIG_SCSI_HISI_SAS=y
+CONFIG_SCSI_HISI_SAS_PCI=y
+# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_MVUMI is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_ESAS2R is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+CONFIG_MEGARAID_SAS=y
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_MPI3MR is not set
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+# CONFIG_XEN_SCSI_FRONTEND is not set
+# CONFIG_SCSI_SNIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_VIRTIO is not set
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+CONFIG_ATA=y
+CONFIG_SATA_HOST=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_ACPI=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_DWC is not set
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_QORIQ=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_DWC is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_PATA_ACPI is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID10 is not set
+# CONFIG_MD_RAID456 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_UNSTRIPED is not set
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_WRITECACHE is not set
+# CONFIG_DM_EBS is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_CLONE is not set
+CONFIG_DM_MIRROR=m
+# CONFIG_DM_LOG_USERSPACE is not set
+# CONFIG_DM_RAID is not set
+CONFIG_DM_ZERO=m
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_DUST is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_DM_INTEGRITY is not set
+# CONFIG_DM_AUDIT is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_WIREGUARD is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_IFB is not set
+# CONFIG_NET_TEAM is not set
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+# CONFIG_IPVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+# CONFIG_AMT is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+CONFIG_TUN=y
+CONFIG_TAP=m
+# CONFIG_TUN_VNET_CROSS_LE is not set
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_B53 is not set
+# CONFIG_NET_DSA_BCM_SF2 is not set
+# CONFIG_NET_DSA_LOOP is not set
+# CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK is not set
+# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
+# CONFIG_NET_DSA_MT7530 is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_AR9331 is not set
+# CONFIG_NET_DSA_QCA8K is not set
+# CONFIG_NET_DSA_SJA1105 is not set
+# CONFIG_NET_DSA_XRS700X_I2C is not set
+# CONFIG_NET_DSA_XRS700X_MDIO is not set
+# CONFIG_NET_DSA_REALTEK is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_MDIO=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+CONFIG_NET_VENDOR_DAVICOM=y
+# CONFIG_DM9051 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+CONFIG_NET_VENDOR_FUNGIBLE=y
+# CONFIG_FUN_ETH is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_E100=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IGB_HWMON=y
+CONFIG_IGBVF=y
+CONFIG_IXGB=y
+CONFIG_IXGBE=y
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBEVF=y
+CONFIG_I40E=y
+CONFIG_IAVF=y
+CONFIG_I40EVF=y
+CONFIG_ICE=y
+CONFIG_ICE_SWITCHDEV=y
+CONFIG_FM10K=y
+CONFIG_IGC=y
+CONFIG_NET_VENDOR_WANGXUN=y
+# CONFIG_NGBE is not set
+# CONFIG_TXGBE is not set
+# CONFIG_JME is not set
+CONFIG_NET_VENDOR_ADI=y
+# CONFIG_ADIN1110 is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETERION is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RDC is not set
+CONFIG_NET_VENDOR_REALTEK=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+CONFIG_R8169=y
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
+# CONFIG_DWMAC_LOONGSON is not set
+# CONFIG_STMMAC_PCI is not set
+# CONFIG_NET_VENDOR_SUN is not set
+CONFIG_NET_VENDOR_SYNOPSYS=y
+# CONFIG_DWC_XLGMAC is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_NET_SB1000 is not set
+CONFIG_PHYLINK=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_SFP is not set
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_ADIN1100_PHY is not set
+CONFIG_AQUANTIA_PHY=y
+CONFIG_AX88796B_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM7XXX_PHY=m
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+CONFIG_BCM_NET_PHYLIB=m
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_PHY=m
+# CONFIG_MICROCHIP_T1_PHY is not set
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MOTORCOMM_PHY=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+CONFIG_AT803X_PHY=y
+# CONFIG_QSEMI_PHY is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_RENESAS_PHY is not set
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_SMSC_PHY=m
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
+# CONFIG_DP83TD510_PHY is not set
+CONFIG_VITESSE_PHY=y
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_PSE_CONTROLLER is not set
+CONFIG_CAN_DEV=m
+# CONFIG_CAN_VCAN is not set
+# CONFIG_CAN_VXCAN is not set
+CONFIG_CAN_NETLINK=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_RX_OFFLOAD=y
+# CONFIG_CAN_CAN327 is not set
+CONFIG_CAN_FLEXCAN=m
+# CONFIG_CAN_GRCAN is not set
+# CONFIG_CAN_KVASER_PCIEFD is not set
+# CONFIG_CAN_SLCAN is not set
+# CONFIG_CAN_XILINXCAN is not set
+# CONFIG_CAN_C_CAN is not set
+# CONFIG_CAN_CC770 is not set
+# CONFIG_CAN_CTUCANFD_PCI is not set
+# CONFIG_CAN_CTUCANFD_PLATFORM is not set
+# CONFIG_CAN_IFI_CANFD is not set
+# CONFIG_CAN_M_CAN is not set
+# CONFIG_CAN_PEAK_PCIEFD is not set
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_SOFTING is not set
+
+#
+# CAN SPI interfaces
+#
+# CONFIG_CAN_HI311X is not set
+# CONFIG_CAN_MCP251X is not set
+# CONFIG_CAN_MCP251XFD is not set
+# end of CAN SPI interfaces
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_8DEV_USB is not set
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB is not set
+# CONFIG_CAN_ETAS_ES58X is not set
+# CONFIG_CAN_GS_USB is not set
+# CONFIG_CAN_KVASER_USB is not set
+# CONFIG_CAN_MCBA_USB is not set
+# CONFIG_CAN_PEAK_USB is not set
+# CONFIG_CAN_UCAN is not set
+# end of CAN USB interfaces
+
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_OF_MDIO=y
+CONFIG_ACPI_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_GPIO is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+# CONFIG_MDIO_THUNDER is not set
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+# end of PCS device drivers
+
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=m
+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
+# CONFIG_USB_NET_CDC_MBIM is not set
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SR9700 is not set
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_NET_CH9200 is not set
+# CONFIG_USB_NET_AQC111 is not set
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_WLAN=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+CONFIG_WLAN_VENDOR_BROADCOM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_BRCMUTIL=m
+# CONFIG_BRCMSMAC is not set
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+# CONFIG_BRCMFMAC_USB is not set
+# CONFIG_BRCMFMAC_PCIE is not set
+CONFIG_BRCM_TRACING=y
+CONFIG_BRCMDBG=y
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+CONFIG_WLAN_VENDOR_PURELIFI=y
+# CONFIG_PLFXLC is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+CONFIG_WLAN_VENDOR_REALTEK=y
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+CONFIG_RTL_CARDS=y
+CONFIG_RTL8192CE=y
+CONFIG_RTL8192SE=y
+CONFIG_RTL8192DE=y
+CONFIG_RTL8723AE=y
+CONFIG_RTL8723BE=y
+CONFIG_RTL8188EE=y
+CONFIG_RTL8192EE=y
+CONFIG_RTL8821AE=y
+CONFIG_RTL8192CU=y
+CONFIG_RTLWIFI=y
+CONFIG_RTLWIFI_PCI=y
+CONFIG_RTLWIFI_USB=y
+CONFIG_RTLWIFI_DEBUG=y
+CONFIG_RTL8192C_COMMON=y
+CONFIG_RTL8723_COMMON=y
+CONFIG_RTLBTCOEXIST=y
+CONFIG_RTL8XXXU=y
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_RTW88=y
+CONFIG_RTW88_CORE=y
+CONFIG_RTW88_PCI=y
+CONFIG_RTW88_8822B=y
+CONFIG_RTW88_8822C=y
+CONFIG_RTW88_8723D=y
+CONFIG_RTW88_8821C=y
+CONFIG_RTW88_8822BE=y
+CONFIG_RTW88_8822CE=y
+CONFIG_RTW88_8723DE=y
+CONFIG_RTW88_8821CE=y
+CONFIG_RTW88_DEBUG=y
+CONFIG_RTW88_DEBUGFS=y
+# CONFIG_RTW89 is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+CONFIG_WLAN_VENDOR_SILABS=y
+# CONFIG_WFX is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+CONFIG_XEN_NETDEV_FRONTEND=y
+# CONFIG_VMXNET3 is not set
+# CONFIG_FUJITSU_ES is not set
+# CONFIG_NETDEVSIM is not set
+CONFIG_NET_FAILOVER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ADC=m
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_PINEPHONE is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_SMBUS=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ADC is not set
+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_BU21029 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
+# CONFIG_TOUCHSCREEN_EXC3000 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_GOODIX=y
+# CONFIG_TOUCHSCREEN_HIDEEP is not set
+# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_ILITEK is not set
+# CONFIG_TOUCHSCREEN_S6SY761 is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_EKTF2127 is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
+# CONFIG_TOUCHSCREEN_MSG2638 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_IMAGIS is not set
+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_RM_TS is not set
+# CONFIG_TOUCHSCREEN_SILEAD is not set
+# CONFIG_TOUCHSCREEN_SIS_I2C is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_STMFTS is not set
+# CONFIG_TOUCHSCREEN_SUR40 is not set
+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZET6223 is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
+# CONFIG_TOUCHSCREEN_IQS5XX is not set
+# CONFIG_TOUCHSCREEN_ZINITIX is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+CONFIG_INPUT_PWM_VIBRA=m
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IBM_PANEL is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_IQS7222 is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_GPIO_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LDISC_AUTOLOAD=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_PERICOM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+# CONFIG_HVC_DCC is not set
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_PLAT_DATA=y
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+# CONFIG_IPMI_SSIF is not set
+# CONFIG_IPMI_IPMB is not set
+# CONFIG_IPMI_WATCHDOG is not set
+# CONFIG_IPMI_POWEROFF is not set
+# CONFIG_IPMB_DEVICE_INTERFACE is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_BA431 is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+CONFIG_HW_RANDOM_OPTEE=m
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+# CONFIG_HW_RANDOM_CN10K is not set
+# CONFIG_APPLICOM is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+CONFIG_TCG_TPM=y
+# CONFIG_TCG_TIS is not set
+# CONFIG_TCG_TIS_SPI is not set
+# CONFIG_TCG_TIS_I2C is not set
+# CONFIG_TCG_TIS_I2C_CR50 is not set
+# CONFIG_TCG_TIS_I2C_ATMEL is not set
+CONFIG_TCG_TIS_I2C_INFINEON=y
+# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_TCG_INFINEON is not set
+# CONFIG_TCG_XEN is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_VTPM_PROXY is not set
+# CONFIG_TCG_FTPM_TEE is not set
+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
+# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+CONFIG_RANDOM_TRUST_CPU=y
+CONFIG_RANDOM_TRUST_BOOTLOADER=y
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_GPMUX is not set
+# CONFIG_I2C_MUX_LTC4306 is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_I2C_MUX_PINCTRL is not set
+# CONFIG_I2C_MUX_REG is not set
+# CONFIG_I2C_DEMUX_PINCTRL is not set
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# end of Multiplexer I2C Chip support
+
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_AMD_MP2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# ACPI drivers
+#
+# CONFIG_I2C_SCMI is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CADENCE is not set
+# CONFIG_I2C_CBUS_GPIO is not set
+CONFIG_I2C_DESIGNWARE_CORE=y
+# CONFIG_I2C_DESIGNWARE_SLAVE is not set
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EMEV2 is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
+# CONFIG_I2C_HISI is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_RK3X=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_THUNDERX is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_PCI1XXXX is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_EEPROM is not set
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_CADENCE is not set
+CONFIG_SPI_CADENCE_QUADSPI=y
+# CONFIG_SPI_CADENCE_XSPI is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_HISI_KUNPENG is not set
+# CONFIG_SPI_HISI_SFC_V3XX is not set
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_MICROCHIP_CORE is not set
+# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_PL022=y
+# CONFIG_SPI_PXA2XX is not set
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+# CONFIG_SPI_MUX is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_HSI is not set
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+CONFIG_PTP_1588_CLOCK_KVM=y
+# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
+# CONFIG_PTP_1588_CLOCK_IDTCM is not set
+# CONFIG_PTP_1588_CLOCK_OCP is not set
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_PINMUX=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_AMD is not set
+# CONFIG_PINCTRL_CY8C95X0 is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+CONFIG_PINCTRL_SINGLE=y
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_AMDPT is not set
+# CONFIG_GPIO_CADENCE is not set
+CONFIG_GPIO_DWAPB=y
+# CONFIG_GPIO_EXAR is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HISI is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_LOGICVC is not set
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SIFIVE is not set
+CONFIG_GPIO_SYSCON=y
+CONFIG_GPIO_XGENE=y
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_MAX7300 is not set
+CONFIG_GPIO_MAX732X=y
+# CONFIG_GPIO_MAX732X_IRQ is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+# CONFIG_GPIO_PCA9570 is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_TPIC2810 is not set
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+# end of MFD GPIO expanders
+
+#
+# PCI GPIO expanders
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_PCI_IDIO_16 is not set
+# CONFIG_GPIO_PCIE_IDIO_24 is not set
+# CONFIG_GPIO_RDC321X is not set
+# end of PCI GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+# CONFIG_W1 is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_BRCMSTB is not set
+CONFIG_POWER_RESET_GPIO=y
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_VEXPRESS is not set
+# CONFIG_POWER_RESET_XGENE is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+# CONFIG_SYSCON_REBOOT_MODE is not set
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PDA_POWER=m
+CONFIG_GENERIC_ADC_BATTERY=m
+# CONFIG_IP5XXX_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+CONFIG_BATTERY_SBS=m
+CONFIG_CHARGER_SBS=m
+CONFIG_MANAGER_SBS=m
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_BQ256XX is not set
+CONFIG_CHARGER_RK817=y
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_BATTERY_UG3105 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DRIVETEMP is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FTSTEUTATES is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+CONFIG_SENSORS_GPIO_FAN=y
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IBMAEM is not set
+# CONFIG_SENSORS_IBMPEX is not set
+# CONFIG_SENSORS_IIO_HWMON is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX31760 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT6775_I2C is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+CONFIG_SENSORS_PWM_FAN=y
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC2305 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP464 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_VEXPRESS is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_XGENE is not set
+
+#
+# ACPI drivers
+#
+# CONFIG_SENSORS_ACPI_POWER is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG_SYSFS=y
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_GPIO_WATCHDOG is not set
+# CONFIG_WDAT_WDT is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_ARM_SBSA_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_HP_WATCHDOG is not set
+# CONFIG_MEN_A21_WDT is not set
+# CONFIG_XEN_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77714 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6370 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_OCELOT is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_SY7636A is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RT5120 is not set
+# CONFIG_MFD_RC5T583 is not set
+CONFIG_MFD_RK808=y
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# CONFIG_MFD_KHADAS_MCU is not set
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_MFD_VEXPRESS_SYSREG is not set
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+CONFIG_REGULATOR_FAN53555=y
+# CONFIG_REGULATOR_FAN53880 is not set
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_MT6315 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT5190A is not set
+# CONFIG_REGULATOR_RT5759 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_VCTRL=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_RC_CORE=m
+# CONFIG_LIRC is not set
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+# CONFIG_IR_IMON_DECODER is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_MCE_KBD_DECODER is not set
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_RCMM_DECODER is not set
+# CONFIG_IR_SANYO_DECODER is not set
+# CONFIG_IR_SHARP_DECODER is not set
+# CONFIG_IR_SONY_DECODER is not set
+# CONFIG_IR_XMP_DECODER is not set
+CONFIG_RC_DEVICES=y
+# CONFIG_IR_ENE is not set
+# CONFIG_IR_FINTEK is not set
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_IR_HIX5HD2 is not set
+# CONFIG_IR_IGORPLUGUSB is not set
+# CONFIG_IR_IGUANA is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_IMON_RAW is not set
+# CONFIG_IR_ITE_CIR is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_NUVOTON is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_SERIAL is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_IR_TOY is not set
+# CONFIG_IR_TTUSBIR is not set
+# CONFIG_RC_ATI_REMOTE is not set
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_RC_XBOX_DVD is not set
+CONFIG_CEC_CORE=y
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_PIN=y
+
+#
+# CEC support
+#
+# CONFIG_CEC_PIN_ERROR_INJ is not set
+CONFIG_MEDIA_CEC_SUPPORT=y
+# CONFIG_CEC_CH7322 is not set
+CONFIG_CEC_GPIO=y
+# CONFIG_USB_PULSE8_CEC is not set
+# CONFIG_USB_RAINSHADOW_CEC is not set
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+# CONFIG_MEDIA_RADIO_SUPPORT is not set
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+# CONFIG_MEDIA_TEST_SUPPORT is not set
+# end of Media device types
+
+CONFIG_VIDEO_DEV=m
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=m
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_ASYNC=m
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+# CONFIG_MEDIA_CONTROLLER_DVB is not set
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+# CONFIG_DVB_MMAP is not set
+# CONFIG_DVB_NET is not set
+CONFIG_DVB_MAX_ADAPTERS=16
+CONFIG_DVB_DYNAMIC_MINORS=y
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+
+#
+# Drivers filtered as selected at 'Filter media drivers'
+#
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_DTCS033 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STK1135 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TOUPTEK is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_VIDEO_USBTV is not set
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+
+#
+# Analog TV USB devices
+#
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_STK1160_COMMON is not set
+
+#
+# Analog/digital TV USB devices
+#
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_CX231XX is not set
+
+#
+# Digital TV USB devices
+#
+# CONFIG_DVB_AS102 is not set
+# CONFIG_DVB_B2C2_FLEXCOP_USB is not set
+# CONFIG_DVB_USB_V2 is not set
+# CONFIG_DVB_USB is not set
+# CONFIG_SMS_USB_DRV is not set
+# CONFIG_DVB_TTUSB_BUDGET is not set
+# CONFIG_DVB_TTUSB_DEC is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+# CONFIG_VIDEO_EM28XX is not set
+
+#
+# Software defined radio USB devices
+#
+# CONFIG_USB_AIRSPY is not set
+# CONFIG_USB_HACKRF is not set
+# CONFIG_USB_MSI2500 is not set
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SDR_PLATFORM_DRIVERS=y
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+# CONFIG_VIDEO_MUX is not set
+
+#
+# Allegro DVT media platform drivers
+#
+
+#
+# Amlogic media platform drivers
+#
+
+#
+# Amphion drivers
+#
+
+#
+# Aspeed media platform drivers
+#
+# CONFIG_VIDEO_ASPEED is not set
+
+#
+# Atmel media platform drivers
+#
+
+#
+# Cadence media platform drivers
+#
+# CONFIG_VIDEO_CADENCE_CSI2RX is not set
+# CONFIG_VIDEO_CADENCE_CSI2TX is not set
+
+#
+# Chips&Media media platform drivers
+#
+
+#
+# Intel media platform drivers
+#
+
+#
+# Marvell media platform drivers
+#
+# CONFIG_VIDEO_CAFE_CCIC is not set
+
+#
+# Mediatek media platform drivers
+#
+
+#
+# NVidia media platform drivers
+#
+
+#
+# NXP media platform drivers
+#
+
+#
+# Qualcomm media platform drivers
+#
+
+#
+# Renesas media platform drivers
+#
+
+#
+# Rockchip media platform drivers
+#
+# CONFIG_VIDEO_ROCKCHIP_RGA is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+
+#
+# Samsung media platform drivers
+#
+
+#
+# STMicroelectronics media platform drivers
+#
+
+#
+# Sunxi media platform drivers
+#
+
+#
+# Texas Instruments drivers
+#
+
+#
+# Verisilicon media platform drivers
+#
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+
+#
+# VIA media platform drivers
+#
+
+#
+# Xilinx media platform drivers
+#
+# CONFIG_VIDEO_XILINX is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+# end of Media drivers
+
+CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_AR0521 is not set
+# CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
+# CONFIG_VIDEO_HI847 is not set
+# CONFIG_VIDEO_IMX208 is not set
+# CONFIG_VIDEO_IMX214 is not set
+CONFIG_VIDEO_IMX219=m
+# CONFIG_VIDEO_IMX258 is not set
+# CONFIG_VIDEO_IMX274 is not set
+# CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX319 is not set
+# CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
+# CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
+# CONFIG_VIDEO_MT9M001 is not set
+# CONFIG_VIDEO_MT9M032 is not set
+# CONFIG_VIDEO_MT9M111 is not set
+# CONFIG_VIDEO_MT9P031 is not set
+# CONFIG_VIDEO_MT9T001 is not set
+# CONFIG_VIDEO_MT9T112 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_MT9V032 is not set
+# CONFIG_VIDEO_MT9V111 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_OG01A1B is not set
+# CONFIG_VIDEO_OV02A10 is not set
+# CONFIG_VIDEO_OV08D10 is not set
+# CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
+# CONFIG_VIDEO_OV2640 is not set
+# CONFIG_VIDEO_OV2659 is not set
+# CONFIG_VIDEO_OV2680 is not set
+# CONFIG_VIDEO_OV2685 is not set
+# CONFIG_VIDEO_OV2740 is not set
+# CONFIG_VIDEO_OV5640 is not set
+CONFIG_VIDEO_OV5645=m
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV5648 is not set
+# CONFIG_VIDEO_OV5670 is not set
+# CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
+# CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV6650 is not set
+# CONFIG_VIDEO_OV7251 is not set
+# CONFIG_VIDEO_OV7640 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_OV772X is not set
+# CONFIG_VIDEO_OV7740 is not set
+# CONFIG_VIDEO_OV8856 is not set
+# CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9282 is not set
+# CONFIG_VIDEO_OV9640 is not set
+# CONFIG_VIDEO_OV9650 is not set
+# CONFIG_VIDEO_OV9734 is not set
+# CONFIG_VIDEO_RDACM20 is not set
+# CONFIG_VIDEO_RDACM21 is not set
+# CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# CONFIG_VIDEO_S5K4ECGX is not set
+# CONFIG_VIDEO_S5K5BAF is not set
+# CONFIG_VIDEO_S5K6A3 is not set
+# CONFIG_VIDEO_S5K6AA is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_CCS is not set
+# CONFIG_VIDEO_ET8EK8 is not set
+# CONFIG_VIDEO_M5MOLS is not set
+# end of Camera sensor devices
+
+#
+# Lens drivers
+#
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# end of Lens drivers
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# end of Flash devices
+
+#
+# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers'
+#
+
+#
+# Video and audio decoders
+#
+
+#
+# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers'
+#
+
+#
+# Media SPI Adapters
+#
+# CONFIG_CXD2880_SPI_DRV is not set
+# CONFIG_VIDEO_GS1662 is not set
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=m
+
+#
+# Tuner drivers auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+
+#
+# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers'
+#
+
+#
+# Multistandard (satellite) frontends
+#
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+
+#
+# DVB-S (satellite) frontends
+#
+
+#
+# DVB-T (terrestrial) frontends
+#
+
+#
+# DVB-C (cable) frontends
+#
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+
+#
+# ISDB-T (terrestrial) frontends
+#
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+
+#
+# Digital terrestrial only tuners/PLL
+#
+
+#
+# SEC control devices for DVB-S
+#
+
+#
+# Common Interface (EN50221) controller drivers
+#
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_APERTURE_HELPERS=y
+CONFIG_DRM=y
+CONFIG_DRM_MIPI_DSI=y
+# CONFIG_DRM_DEBUG_MM is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+CONFIG_DRM_DP_AUX_BUS=m
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_SCHED=y
+
+#
+# I2C encoder or helper chips
+#
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_HDLCD is not set
+CONFIG_DRM_MALI_DISPLAY=m
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_AMDGPU is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_ROCKCHIP_VOP2=y
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_CDN_DP is not set
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+# CONFIG_ROCKCHIP_RGB is not set
+# CONFIG_ROCKCHIP_RK3066_HDMI is not set
+# CONFIG_DRM_VMWGFX is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_DRM_VIRTIO_GPU is not set
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
+# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
+# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
+# CONFIG_DRM_PANEL_DSI_CM is not set
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_EDP=m
+# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
+# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
+# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
+# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
+# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
+# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
+# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
+# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
+# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
+# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9211 is not set
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611UXC=m
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+CONFIG_DRM_NWL_MIPI_DSI=m
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+CONFIG_DRM_SII902X=m
+# CONFIG_DRM_SII9234 is not set
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TI_DLPC3433 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+CONFIG_DRM_TI_SN65DSI86=m
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+CONFIG_DRM_DW_HDMI=y
+# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+CONFIG_DRM_DW_HDMI_CEC=y
+CONFIG_DRM_DW_MIPI_DSI=y
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_HISI_HIBMC is not set
+# CONFIG_DRM_HISI_KIRIN is not set
+# CONFIG_DRM_LOGICVC is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_IMX_LCDIF is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_BOCHS is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_PANEL_MIPI_DBI is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+CONFIG_DRM_PL111=m
+# CONFIG_DRM_XEN_FRONTEND is not set
+# CONFIG_DRM_LIMA is not set
+CONFIG_DRM_PANFROST=y
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_SSD130X is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_EFI is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_XEN_FBDEV_FRONTEND is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_SIMPLE=y
+# CONFIG_FB_SSD1307 is not set
+# CONFIG_FB_SM712 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+CONFIG_BACKLIGHT_PWM=m
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_LM3630A=y
+# CONFIG_BACKLIGHT_LM3639 is not set
+CONFIG_BACKLIGHT_LP855X=m
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_LED is not set
+# end of Backlight & LCD device support
+
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_OSSEMUL is not set
+CONFIG_SND_PCM_TIMER=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_CTL_FAST_LOOKUP=y
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_CTL_INPUT_VALIDATION is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_SERIAL_GENERIC is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SE6X is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+
+#
+# HD-Audio
+#
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_INTEL=y
+# CONFIG_SND_HDA_HWDEP is not set
+# CONFIG_SND_HDA_RECONFIG is not set
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
+# CONFIG_SND_HDA_CODEC_REALTEK is not set
+# CONFIG_SND_HDA_CODEC_ANALOG is not set
+# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
+# CONFIG_SND_HDA_CODEC_VIA is not set
+CONFIG_SND_HDA_CODEC_HDMI=y
+# CONFIG_SND_HDA_CODEC_CIRRUS is not set
+# CONFIG_SND_HDA_CODEC_CS8409 is not set
+# CONFIG_SND_HDA_CODEC_CONEXANT is not set
+# CONFIG_SND_HDA_CODEC_CA0110 is not set
+# CONFIG_SND_HDA_CODEC_CA0132 is not set
+# CONFIG_SND_HDA_CODEC_CMEDIA is not set
+# CONFIG_SND_HDA_CODEC_SI3054 is not set
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
+# end of HD-Audio
+
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_USB_HIFACE is not set
+# CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_USB_POD is not set
+# CONFIG_SND_USB_PODHD is not set
+# CONFIG_SND_USB_TONEPORT is not set
+# CONFIG_SND_USB_VARIAX is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_ADI is not set
+# CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+CONFIG_SND_SOC_FSL_ASRC=m
+CONFIG_SND_SOC_FSL_SAI=m
+# CONFIG_SND_SOC_FSL_MQS is not set
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_ESAI=m
+CONFIG_SND_SOC_FSL_MICFIL=m
+CONFIG_SND_SOC_FSL_EASRC=m
+# CONFIG_SND_SOC_FSL_XCVR is not set
+CONFIG_SND_SOC_FSL_UTILS=m
+CONFIG_SND_SOC_IMX_AUDMUX=m
+# end of SoC Audio for Freescale CPUs
+
+# CONFIG_SND_I2S_HI6210_I2S is not set
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+CONFIG_SND_SOC_ROCKCHIP=y
+CONFIG_SND_SOC_ROCKCHIP_I2S=y
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
+CONFIG_SND_SOC_ROCKCHIP_PDM=y
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
+CONFIG_SND_SOC_ROCKCHIP_RT5645=y
+CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
+CONFIG_SND_SOC_RK3399_GRU_SOUND=y
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+
+#
+# CODEC drivers
+#
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+CONFIG_SND_SOC_AK4613=m
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_AW8738 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+# CONFIG_SND_SOC_BT_SCO is not set
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS35L45_SPI is not set
+# CONFIG_SND_SOC_CS35L45_I2C is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS42L83 is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+CONFIG_SND_SOC_DA7219=y
+CONFIG_SND_SOC_DMIC=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+# CONFIG_SND_SOC_ES8316 is not set
+# CONFIG_SND_SOC_ES8326 is not set
+CONFIG_SND_SOC_ES8328=y
+CONFIG_SND_SOC_ES8328_I2C=y
+CONFIG_SND_SOC_ES8328_SPI=y
+CONFIG_SND_SOC_GTM601=m
+# CONFIG_SND_SOC_HDA is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+CONFIG_SND_SOC_MAX98090=y
+CONFIG_SND_SOC_MAX98357A=y
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+CONFIG_SND_SOC_MAX98927=m
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98373_SDW is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX98396 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM5102A is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+CONFIG_SND_SOC_RK3328=y
+CONFIG_SND_SOC_RK817=y
+CONFIG_SND_SOC_RL6231=y
+# CONFIG_SND_SOC_RT1308_SDW is not set
+# CONFIG_SND_SOC_RT1316_SDW is not set
+CONFIG_SND_SOC_RT5514=y
+CONFIG_SND_SOC_RT5514_SPI=y
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+CONFIG_SND_SOC_RT5645=y
+CONFIG_SND_SOC_RT5659=m
+# CONFIG_SND_SOC_RT5682_SDW is not set
+# CONFIG_SND_SOC_RT700_SDW is not set
+# CONFIG_SND_SOC_RT711_SDW is not set
+# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT715_SDW is not set
+# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT9120 is not set
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
+CONFIG_SND_SOC_SIMPLE_MUX=y
+CONFIG_SND_SOC_SPDIF=y
+# CONFIG_SND_SOC_SRC4XXX_I2C is not set
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS2780 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+CONFIG_SND_SOC_TAS571X=m
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS5805M is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+CONFIG_SND_SOC_TS3A227E=y
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WCD938X_SDW is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731_I2C is not set
+# CONFIG_SND_SOC_WM8731_SPI is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+CONFIG_SND_SOC_WM8904=m
+# CONFIG_SND_SOC_WM8940 is not set
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8962=m
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+CONFIG_SND_SOC_WSA881X=m
+# CONFIG_SND_SOC_WSA883X is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+# CONFIG_SND_XEN_FRONTEND is not set
+# CONFIG_SND_VIRTIO is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_ASUS is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_BIGBEN_FF is not set
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+# CONFIG_HID_CORSAIR is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+CONFIG_HID_CYPRESS=y
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELAN is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_GLORIOUS is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_VRC2 is not set
+# CONFIG_HID_XIAOMI is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LED is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_HIDPP=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_MEGAWORLD_FF is not set
+CONFIG_HID_REDRAGON=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=y
+# CONFIG_HID_NINTENDO is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PXRC is not set
+# CONFIG_HID_RAZER is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SEMITEK is not set
+# CONFIG_HID_SIGMAMICRO is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_TOPRE is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_U2FZERO is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# CONFIG_HID_MCP2221 is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+# end of USB HID support
+
+#
+# I2C HID support
+#
+CONFIG_I2C_HID_ACPI=m
+CONFIG_I2C_HID_OF=m
+# CONFIG_I2C_HID_OF_ELAN is not set
+CONFIG_I2C_HID_OF_GOODIX=m
+# end of I2C HID support
+
+CONFIG_I2C_HID_CORE=m
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_OTG_FSM is not set
+CONFIG_USB_LEDS_TRIGGER_USBPORT=y
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+CONFIG_USB_MON=m
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+# CONFIG_USB_XEN_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_MUSB_HDRC is not set
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_ULPI is not set
+# CONFIG_USB_DWC3_HOST is not set
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+#
+# Platform Glue Driver Support
+#
+CONFIG_USB_DWC3_PCI=y
+CONFIG_USB_DWC3_HAPS=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC2=y
+# CONFIG_USB_DWC2_HOST is not set
+
+#
+# Gadget/Dual-role mode requires USB Gadget support to be enabled
+#
+# CONFIG_USB_DWC2_PERIPHERAL is not set
+CONFIG_USB_DWC2_DUAL_ROLE=y
+# CONFIG_USB_DWC2_PCI is not set
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+CONFIG_USB_SERIAL_CH341=m
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+CONFIG_USB_SERIAL_CP210X=m
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=m
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_F81232 is not set
+# CONFIG_USB_SERIAL_F8153X is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_METRO is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MXUPORT is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_XSENS_MT is not set
+# CONFIG_USB_SERIAL_WISHBONE is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_QT2 is not set
+# CONFIG_USB_SERIAL_UPD78F0730 is not set
+# CONFIG_USB_SERIAL_XR is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_ONBOARD_HUB is not set
+
+#
+# USB Physical Layer drivers
+#
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# end of USB Physical Layer drivers
+
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_U_SERIAL_CONSOLE is not set
+
+#
+# USB Peripheral Controller
+#
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MV_U3D is not set
+CONFIG_USB_SNP_CORE=y
+CONFIG_USB_SNP_UDC_PLAT=y
+# CONFIG_USB_M66592 is not set
+CONFIG_USB_BDC_UDC=y
+# CONFIG_USB_AMD5536UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_NET2280 is not set
+# CONFIG_USB_GOKU is not set
+# CONFIG_USB_EG20T is not set
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_DUMMY_HCD is not set
+# end of USB Peripheral Controller
+
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_F_SERIAL=y
+CONFIG_USB_F_OBEX=y
+CONFIG_USB_F_NCM=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_F_SUBSET=y
+CONFIG_USB_F_RNDIS=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_F_FS=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+# CONFIG_USB_CONFIGFS_F_LB_SS is not set
+CONFIG_USB_CONFIGFS_F_FS=y
+# CONFIG_USB_CONFIGFS_F_UAC1 is not set
+# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
+# CONFIG_USB_CONFIGFS_F_UAC2 is not set
+# CONFIG_USB_CONFIGFS_F_MIDI is not set
+# CONFIG_USB_CONFIGFS_F_HID is not set
+# CONFIG_USB_CONFIGFS_F_UVC is not set
+# CONFIG_USB_CONFIGFS_F_PRINTER is not set
+
+#
+# USB Gadget precomposed configurations
+#
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_USB_RAW_GADGET is not set
+# end of USB Gadget precomposed configurations
+
+CONFIG_TYPEC=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+# CONFIG_TYPEC_RT1711H is not set
+# CONFIG_TYPEC_TCPCI_MAXIM is not set
+CONFIG_TYPEC_FUSB302=y
+CONFIG_TYPEC_UCSI=y
+# CONFIG_UCSI_CCG is not set
+# CONFIG_UCSI_ACPI is not set
+# CONFIG_UCSI_STM32G0 is not set
+CONFIG_TYPEC_TPS6598X=m
+# CONFIG_TYPEC_ANX7411 is not set
+# CONFIG_TYPEC_RT1719 is not set
+CONFIG_TYPEC_HD3SS3220=m
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_WUSB3801=y
+
+#
+# USB Type-C Multiplexer/DeMultiplexer Switch support
+#
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# end of USB Type-C Multiplexer/DeMultiplexer Switch support
+
+#
+# USB Type-C Alternate Mode drivers
+#
+# CONFIG_TYPEC_DP_ALTMODE is not set
+# end of USB Type-C Alternate Mode drivers
+
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_STM32_SDMMC=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_OF_AT91 is not set
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_CADENCE is not set
+CONFIG_MMC_SDHCI_F_SDH30=y
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_HSQ=y
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MMC_SDHCI_XENON is not set
+# CONFIG_MMC_SDHCI_OMAP is not set
+# CONFIG_MMC_SDHCI_AM654 is not set
+CONFIG_SCSI_UFSHCD=y
+# CONFIG_SCSI_UFS_BSG is not set
+# CONFIG_SCSI_UFS_HPB is not set
+# CONFIG_SCSI_UFS_HWMON is not set
+# CONFIG_SCSI_UFSHCD_PCI is not set
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
+# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+# CONFIG_LEDS_CLASS_FLASH is not set
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_EL15203000 is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_REGULATOR=y
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+CONFIG_LEDS_SYSCON=y
+# CONFIG_LEDS_MLXREG is not set
+CONFIG_LEDS_USER=y
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+
+#
+# Flash and Torch LED drivers
+#
+
+#
+# RGB LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PATTERN=y
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_TTY=y
+
+#
+# Simple LED drivers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_GHES=y
+# CONFIG_EDAC_THUNDERX is not set
+# CONFIG_EDAC_XGENE is not set
+# CONFIG_EDAC_DMC520 is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_NCT3018Y is not set
+CONFIG_RTC_DRV_RK808=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+CONFIG_RTC_DRV_PCF85063=y
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+CONFIG_RTC_DRV_EFI=y
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_OPTEE is not set
+# CONFIG_RTC_DRV_ZYNQMP is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+CONFIG_AMBA_PL08X=y
+# CONFIG_BCM_SBA_RAID is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_HISI_DMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_MV_XOR_V2 is not set
+CONFIG_PL330_DMA=y
+# CONFIG_PLX_DMA is not set
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+CONFIG_DW_DMAC_CORE=m
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_PCI=m
+CONFIG_DW_EDMA=m
+CONFIG_DW_EDMA_PCIE=m
+# CONFIG_SF_PDMA is not set
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_MF624 is not set
+CONFIG_VFIO=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VFIO_NOIOMMU=y
+CONFIG_VFIO_PCI_CORE=y
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=y
+# CONFIG_HISI_ACC_VFIO_PCI is not set
+# CONFIG_VFIO_PLATFORM is not set
+# CONFIG_VFIO_MDEV is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+# CONFIG_VDPA is not set
+CONFIG_VHOST_MENU=y
+# CONFIG_VHOST_NET is not set
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_HYPERV is not set
+# end of Microsoft Hyper-V guest support
+
+#
+# Xen driver support
+#
+# CONFIG_XEN_BALLOON is not set
+# CONFIG_XEN_DEV_EVTCHN is not set
+# CONFIG_XEN_BACKEND is not set
+# CONFIG_XENFS is not set
+# CONFIG_XEN_SYS_HYPERVISOR is not set
+CONFIG_XEN_XENBUS_FRONTEND=y
+# CONFIG_XEN_GNTDEV is not set
+# CONFIG_XEN_GRANT_DEV_ALLOC is not set
+# CONFIG_XEN_GRANT_DMA_ALLOC is not set
+CONFIG_SWIOTLB_XEN=y
+# CONFIG_XEN_PVCALLS_FRONTEND is not set
+CONFIG_XEN_PRIVCMD=m
+CONFIG_XEN_EFI=y
+CONFIG_XEN_AUTO_XLATE=y
+# CONFIG_XEN_VIRTIO is not set
+# end of Xen driver support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+# CONFIG_PRISM2_USB is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8723BS=m
+CONFIG_R8712U=m
+CONFIG_R8188EU=m
+# CONFIG_RTS5208 is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16240 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7816 is not set
+# end of Analog to digital converters
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+# end of Analog digital bi-direction converters
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# end of Direct Digital Synthesis
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+# end of Network Analyzer, Impedance Converters
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7854 is not set
+# end of Active energy metering IC
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S1210 is not set
+# end of Resolver to digital converters
+# end of IIO staging drivers
+
+# CONFIG_FB_SM750 is not set
+CONFIG_STAGING_MEDIA=y
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+# CONFIG_STAGING_MEDIA_DEPRECATED is not set
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_KS7010 is not set
+# CONFIG_PI433 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_QLGE is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# CONFIG_CLK_VEXPRESS_OSC is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+CONFIG_COMMON_CLK_PWM=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_VC7 is not set
+CONFIG_COMMON_CLK_FIXED_MMIO=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+# CONFIG_XILINX_VCU is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+CONFIG_HWSPINLOCK=y
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+# CONFIG_FSL_ERRATUM_A008585 is not set
+# CONFIG_HISILICON_ERRATUM_161010101 is not set
+CONFIG_ARM64_ERRATUM_858921=y
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_PLATFORM_MHU=y
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_PCC=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOASID=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_OF_IOMMU=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_SVA=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SMMU_V3_SVA=y
+# CONFIG_VIRTIO_IOMMU is not set
+
+#
+# Remoteproc drivers
+#
+CONFIG_REMOTEPROC=y
+CONFIG_REMOTEPROC_CDEV=y
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+CONFIG_SOUNDWIRE=m
+
+#
+# SoundWire Devices
+#
+CONFIG_SOUNDWIRE_CADENCE=m
+CONFIG_SOUNDWIRE_INTEL=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# fujitsu SoC drivers
+#
+# CONFIG_A64FX_DIAG is not set
+# end of fujitsu SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# end of Enable LiteX SoC Builder specific drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=m
+CONFIG_DEVFREQ_GOV_POWERSAVE=m
+CONFIG_DEVFREQ_GOV_USERSPACE=m
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3399_DMC_DEVFREQ=m
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+CONFIG_EXTCON_ADC_JACK=y
+# CONFIG_EXTCON_FSA9480 is not set
+CONFIG_EXTCON_GPIO=y
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+CONFIG_EXTCON_USB_GPIO=y
+# CONFIG_EXTCON_USBC_TUSB320 is not set
+CONFIG_MEMORY=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+# CONFIG_IIO_CONFIGFS is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+# CONFIG_IIO_SW_DEVICE is not set
+# CONFIG_IIO_SW_TRIGGER is not set
+# CONFIG_IIO_TRIGGERED_EVENT is not set
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
+# CONFIG_ADXL345_I2C is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
+# CONFIG_ADXL367_SPI is not set
+# CONFIG_ADXL367_I2C is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXL372_I2C is not set
+# CONFIG_BMA180 is not set
+# CONFIG_BMA220 is not set
+# CONFIG_BMA400 is not set
+# CONFIG_BMC150_ACCEL is not set
+# CONFIG_BMI088_ACCEL is not set
+# CONFIG_DA280 is not set
+# CONFIG_DA311 is not set
+# CONFIG_DMARD06 is not set
+# CONFIG_DMARD09 is not set
+# CONFIG_DMARD10 is not set
+# CONFIG_FXLS8962AF_I2C is not set
+# CONFIG_FXLS8962AF_SPI is not set
+CONFIG_IIO_ST_ACCEL_3AXIS=y
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=y
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=y
+# CONFIG_KXSD9 is not set
+# CONFIG_KXCJK1013 is not set
+# CONFIG_MC3230 is not set
+# CONFIG_MMA7455_I2C is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMA7660 is not set
+# CONFIG_MMA8452 is not set
+# CONFIG_MMA9551 is not set
+# CONFIG_MMA9553 is not set
+# CONFIG_MSA311 is not set
+# CONFIG_MXC4005 is not set
+# CONFIG_MXC6255 is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SCA3300 is not set
+# CONFIG_STK8312 is not set
+# CONFIG_STK8BA50 is not set
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7091R5 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7280 is not set
+# CONFIG_AD7291 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606_IFACE_PARALLEL is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD799X is not set
+# CONFIG_ADI_AXI_ADC is not set
+# CONFIG_CC10001_ADC is not set
+# CONFIG_ENVELOPE_DETECTOR is not set
+# CONFIG_HI8435 is not set
+# CONFIG_HX711 is not set
+# CONFIG_INA2XX_ADC is not set
+# CONFIG_LTC2471 is not set
+# CONFIG_LTC2485 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2497 is not set
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX11205 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX1363 is not set
+CONFIG_MAX9611=m
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3422 is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_NAU7802 is not set
+CONFIG_QCOM_VADC_COMMON=m
+# CONFIG_QCOM_SPMI_IADC is not set
+# CONFIG_QCOM_SPMI_VADC is not set
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_ROCKCHIP_SARADC=m
+# CONFIG_RICHTEK_RTQ6056 is not set
+# CONFIG_SD_ADC_MODULATOR is not set
+# CONFIG_TI_ADC081C is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS1015 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS131E08 is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_TI_TSC2046 is not set
+# CONFIG_VF610_ADC is not set
+# CONFIG_XILINX_XADC is not set
+# end of Analog to digital converters
+
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
+# Analog Front Ends
+#
+# CONFIG_IIO_RESCALE is not set
+# end of Analog Front Ends
+
+#
+# Amplifiers
+#
+# CONFIG_AD8366 is not set
+# CONFIG_ADA4250 is not set
+# CONFIG_HMC425 is not set
+# end of Amplifiers
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# CONFIG_AD7746 is not set
+# end of Capacitance to digital converters
+
+#
+# Chemical Sensors
+#
+# CONFIG_ATLAS_PH_SENSOR is not set
+# CONFIG_ATLAS_EZO_SENSOR is not set
+# CONFIG_BME680 is not set
+# CONFIG_CCS811 is not set
+# CONFIG_IAQCORE is not set
+# CONFIG_PMS7003 is not set
+# CONFIG_SCD30_CORE is not set
+# CONFIG_SCD4X is not set
+# CONFIG_SENSIRION_SGP30 is not set
+# CONFIG_SENSIRION_SGP40 is not set
+# CONFIG_SPS30_I2C is not set
+# CONFIG_SPS30_SERIAL is not set
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
+# CONFIG_VZ89X is not set
+# end of Chemical Sensors
+
+#
+# Hid Sensor IIO Common
+#
+# end of Hid Sensor IIO Common
+
+#
+# IIO SCMI Sensors
+#
+# CONFIG_IIO_SCMI is not set
+# end of IIO SCMI Sensors
+
+#
+# SSP Sensor Common
+#
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# end of SSP Sensor Common
+
+CONFIG_IIO_ST_SENSORS_I2C=y
+CONFIG_IIO_ST_SENSORS_SPI=y
+CONFIG_IIO_ST_SENSORS_CORE=y
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD3552R is not set
+# CONFIG_AD5064 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5593R is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_LTC2688 is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5696_I2C is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5766 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_DPOT_DAC is not set
+# CONFIG_DS4424 is not set
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_M62332 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MAX5821 is not set
+# CONFIG_MCP4725 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC5571 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_VF610_DAC is not set
+# end of Digital to analog converters
+
+#
+# IIO dummy driver
+#
+# end of IIO dummy driver
+
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+# CONFIG_AD9523 is not set
+# end of Clock Generator/Distribution
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADMV1014 is not set
+# CONFIG_ADMV4420 is not set
+# CONFIG_ADRF6780 is not set
+# end of Phase-Locked Loop (PLL) frequency synthesizers
+# end of Frequency Synthesizers DDS/PLL
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_BMG160 is not set
+# CONFIG_FXAS21002C is not set
+# CONFIG_MPU3050_I2C is not set
+# CONFIG_IIO_ST_GYRO_3AXIS is not set
+# CONFIG_ITG3200 is not set
+# end of Digital gyroscope sensors
+
+#
+# Health Sensors
+#
+
+#
+# Heart Rate Monitors
+#
+# CONFIG_AFE4403 is not set
+# CONFIG_AFE4404 is not set
+# CONFIG_MAX30100 is not set
+# CONFIG_MAX30102 is not set
+# end of Heart Rate Monitors
+# end of Health Sensors
+
+#
+# Humidity sensors
+#
+# CONFIG_AM2315 is not set
+# CONFIG_DHT11 is not set
+# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
+# CONFIG_HTS221 is not set
+# CONFIG_HTU21 is not set
+# CONFIG_SI7005 is not set
+# CONFIG_SI7020 is not set
+# end of Humidity sensors
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_BMI160_I2C is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_BOSCH_BNO055_SERIAL is not set
+# CONFIG_BOSCH_BNO055_I2C is not set
+# CONFIG_FXOS8700_I2C is not set
+# CONFIG_FXOS8700_SPI is not set
+# CONFIG_KMX61 is not set
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_I2C is not set
+# CONFIG_INV_MPU6050_SPI is not set
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+# CONFIG_IIO_ST_LSM9DS0 is not set
+# end of Inertial measurement units
+
+#
+# Light sensors
+#
+# CONFIG_ACPI_ALS is not set
+# CONFIG_ADJD_S311 is not set
+# CONFIG_ADUX1020 is not set
+# CONFIG_AL3010 is not set
+# CONFIG_AL3320A is not set
+# CONFIG_APDS9300 is not set
+# CONFIG_APDS9960 is not set
+# CONFIG_AS73211 is not set
+# CONFIG_BH1750 is not set
+# CONFIG_BH1780 is not set
+# CONFIG_CM32181 is not set
+# CONFIG_CM3232 is not set
+# CONFIG_CM3323 is not set
+# CONFIG_CM3605 is not set
+# CONFIG_CM36651 is not set
+# CONFIG_GP2AP002 is not set
+# CONFIG_GP2AP020A00F is not set
+CONFIG_SENSORS_ISL29018=m
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_ISL29125 is not set
+# CONFIG_JSA1212 is not set
+# CONFIG_RPR0521 is not set
+# CONFIG_LTR501 is not set
+# CONFIG_LTRF216A is not set
+# CONFIG_LV0104CS is not set
+# CONFIG_MAX44000 is not set
+# CONFIG_MAX44009 is not set
+# CONFIG_NOA1305 is not set
+# CONFIG_OPT3001 is not set
+# CONFIG_PA12203001 is not set
+# CONFIG_SI1133 is not set
+# CONFIG_SI1145 is not set
+# CONFIG_STK3310 is not set
+# CONFIG_ST_UVIS25 is not set
+# CONFIG_TCS3414 is not set
+# CONFIG_TCS3472 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TSL2591 is not set
+# CONFIG_TSL2772 is not set
+# CONFIG_TSL4531 is not set
+# CONFIG_US5182D is not set
+CONFIG_VCNL4000=m
+# CONFIG_VCNL4035 is not set
+# CONFIG_VEML6030 is not set
+# CONFIG_VEML6070 is not set
+# CONFIG_VL6180 is not set
+# CONFIG_ZOPT2201 is not set
+# end of Light sensors
+
+#
+# Magnetometer sensors
+#
+# CONFIG_AK8974 is not set
+# CONFIG_AK8975 is not set
+# CONFIG_AK09911 is not set
+# CONFIG_BMC150_MAGN_I2C is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_MAG3110 is not set
+# CONFIG_MMC35240 is not set
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+# CONFIG_SENSORS_HMC5843_I2C is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_RM3100_I2C is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_YAMAHA_YAS530 is not set
+# end of Magnetometer sensors
+
+#
+# Multiplexers
+#
+# CONFIG_IIO_MUX is not set
+# end of Multiplexers
+
+#
+# Inclinometer sensors
+#
+# end of Inclinometer sensors
+
+#
+# Triggers - standalone
+#
+# CONFIG_IIO_INTERRUPT_TRIGGER is not set
+# CONFIG_IIO_SYSFS_TRIGGER is not set
+# end of Triggers - standalone
+
+#
+# Linear and angular position sensors
+#
+# end of Linear and angular position sensors
+
+#
+# Digital potentiometers
+#
+# CONFIG_AD5110 is not set
+# CONFIG_AD5272 is not set
+# CONFIG_DS1803 is not set
+# CONFIG_MAX5432 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MCP4018 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4531 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_TPL0102 is not set
+# end of Digital potentiometers
+
+#
+# Digital potentiostats
+#
+# CONFIG_LMP91000 is not set
+# end of Digital potentiostats
+
+#
+# Pressure sensors
+#
+# CONFIG_ABP060MG is not set
+# CONFIG_BMP280 is not set
+# CONFIG_DLHL60D is not set
+# CONFIG_DPS310 is not set
+# CONFIG_HP03 is not set
+# CONFIG_ICP10100 is not set
+# CONFIG_MPL115_I2C is not set
+# CONFIG_MPL115_SPI is not set
+CONFIG_MPL3115=m
+# CONFIG_MS5611 is not set
+# CONFIG_MS5637 is not set
+# CONFIG_IIO_ST_PRESS is not set
+# CONFIG_T5403 is not set
+# CONFIG_HP206C is not set
+# CONFIG_ZPA2326 is not set
+# end of Pressure sensors
+
+#
+# Lightning sensors
+#
+# CONFIG_AS3935 is not set
+# end of Lightning sensors
+
+#
+# Proximity and distance sensors
+#
+# CONFIG_ISL29501 is not set
+# CONFIG_LIDAR_LITE_V2 is not set
+# CONFIG_MB1232 is not set
+# CONFIG_PING is not set
+# CONFIG_RFD77402 is not set
+# CONFIG_SRF04 is not set
+# CONFIG_SX9310 is not set
+# CONFIG_SX9324 is not set
+# CONFIG_SX9360 is not set
+# CONFIG_SX9500 is not set
+# CONFIG_SRF08 is not set
+# CONFIG_VCNL3020 is not set
+# CONFIG_VL53L0X_I2C is not set
+# end of Proximity and distance sensors
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1200 is not set
+# end of Resolver to digital converters
+
+#
+# Temperature sensors
+#
+# CONFIG_LTC2983 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MLX90614 is not set
+# CONFIG_MLX90632 is not set
+# CONFIG_TMP006 is not set
+# CONFIG_TMP007 is not set
+# CONFIG_TMP117 is not set
+# CONFIG_TSYS01 is not set
+# CONFIG_TSYS02D is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX31865 is not set
+# end of Temperature sensors
+
+# CONFIG_NTB is not set
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_DWC is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+# CONFIG_PWM_XILINX is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+# CONFIG_AL_FIC is not set
+# CONFIG_XILINX_INTC is not set
+CONFIG_PARTITION_PERCPU=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+# CONFIG_RESET_TI_SYSCON is not set
+# CONFIG_RESET_TI_TPS380X is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+
+#
+# PHY drivers for Broadcom platforms
+#
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_QCOM_USB_HS is not set
+# CONFIG_PHY_QCOM_USB_HSIC is not set
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+# CONFIG_PHY_SAMSUNG_USB2 is not set
+# CONFIG_PHY_TUSB1210 is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# CONFIG_ARM_CCI_PMU is not set
+# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PMU_ACPI=y
+CONFIG_ARM_SMMU_V3_PMU=m
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_SPE_PMU is not set
+# CONFIG_ARM_DMC620_PMU is not set
+# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
+# CONFIG_HISI_PMU is not set
+# CONFIG_HISI_PCIE_PMU is not set
+# CONFIG_HNS3_PMU is not set
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_USB4 is not set
+
+#
+# Android
+#
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+# CONFIG_DAX is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_RMEM=m
+# CONFIG_NVMEM_ROCKCHIP_EFUSE is not set
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+# CONFIG_NVMEM_U_BOOT_ENV is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# CONFIG_HISI_PTT is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_MULTIPLEXER=y
+
+#
+# Multiplexer drivers
+#
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_ADGS1408 is not set
+# CONFIG_MUX_GPIO is not set
+CONFIG_MUX_MMIO=y
+# end of Multiplexer drivers
+
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+CONFIG_INTERCONNECT=y
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# CONFIG_PECI is not set
+# CONFIG_HTE is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+# CONFIG_F2FS_FS_SECURITY is not set
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+# CONFIG_F2FS_FS_COMPRESSION is not set
+CONFIG_F2FS_IOSTAT=y
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+# CONFIG_VIRTIO_FS is not set
+CONFIG_OVERLAY_FS=m
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_INDEX is not set
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+# CONFIG_OVERLAY_FS_METACOPY is not set
+
+#
+# Caches
+#
+CONFIG_NETFS_SUPPORT=y
+# CONFIG_NETFS_STATS is not set
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_EXFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+CONFIG_NTFS3_FS=y
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+CONFIG_NTFS3_LZX_XPRESS=y
+# CONFIG_NTFS3_FS_POSIX_ACL is not set
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_VMCORE=y
+# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_INODE64 is not set
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+# CONFIG_SQUASHFS_XATTR is not set
+CONFIG_SQUASHFS_ZLIB=y
+# CONFIG_SQUASHFS_LZ4 is not set
+# CONFIG_SQUASHFS_LZO is not set
+# CONFIG_SQUASHFS_XZ is not set
+# CONFIG_SQUASHFS_ZSTD is not set
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_PSTORE=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE_DEFLATE_COMPRESS=y
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
+# CONFIG_PSTORE_842_COMPRESS is not set
+# CONFIG_PSTORE_ZSTD_COMPRESS is not set
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
+CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
+# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_PMSG is not set
+# CONFIG_PSTORE_FTRACE is not set
+# CONFIG_PSTORE_RAM is not set
+# CONFIG_PSTORE_BLK is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=y
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_NFS_V4_SECURITY_LABEL=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+# CONFIG_NFSD is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+CONFIG_SMB_SERVER=y
+CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_SMBFS_COMMON=y
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_9P_FS=y
+# CONFIG_9P_FS_POSIX_ACL is not set
+# CONFIG_9P_FS_SECURITY is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+CONFIG_UNICODE=y
+# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_TRUSTED_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_SECURITY_LOADPIN is not set
+# CONFIG_SECURITY_YAMA is not set
+# CONFIG_SECURITY_SAFESETID is not set
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
+# CONFIG_SECURITY_LANDLOCK is not set
+CONFIG_INTEGRITY=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
+CONFIG_INTEGRITY_AUDIT=y
+# CONFIG_IMA is not set
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+# CONFIG_EVM is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+
+CONFIG_RANDSTRUCT_NONE=y
+# CONFIG_RANDSTRUCT_FULL is not set
+# CONFIG_RANDSTRUCT_PERFORMANCE is not set
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_ENGINE=m
+# end of Crypto core or helper
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_DH=m
+# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+CONFIG_CRYPTO_CURVE25519=m
+# end of Public-key cryptography
+
+#
+# Block ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARIA is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_SM4=m
+# CONFIG_CRYPTO_SM4_GENERIC is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# end of Block ciphers
+
+#
+# Length-preserving ciphers and modes
+#
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_HCTR2 is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_XTS=m
+# end of Length-preserving ciphers and modes
+
+#
+# AEAD (authenticated encryption with associated data) ciphers
+#
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_ECHAINIV=y
+# CONFIG_CRYPTO_ESSIV is not set
+# end of AEAD (authenticated encryption with associated data) ciphers
+
+#
+# Hashes, digests, and MACs
+#
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SM3=m
+# CONFIG_CRYPTO_SM3_GENERIC is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+CONFIG_CRYPTO_XXHASH=m
+# end of Hashes, digests, and MACs
+
+#
+# CRCs (cyclic redundancy checks)
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+# end of CRCs (cyclic redundancy checks)
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+CONFIG_CRYPTO_ZSTD=y
+# end of Compression
+
+#
+# Random number generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# end of Random number generation
+
+#
+# Userspace interface
+#
+CONFIG_CRYPTO_USER_API=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_USER_API_RNG=m
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+# end of Userspace interface
+
+CONFIG_CRYPTO_HASH_INFO=y
+# CONFIG_CRYPTO_NHPOLY1305_NEON is not set
+CONFIG_CRYPTO_CHACHA20_NEON=m
+
+#
+# Accelerated Cryptographic Algorithms for CPU (arm64)
+#
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+# CONFIG_CRYPTO_POLY1305_NEON is not set
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=m
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+# CONFIG_CRYPTO_SM4_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+# end of Accelerated Cryptographic Algorithms for CPU (arm64)
+
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+# CONFIG_CRYPTO_DEV_CCP is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_C62X is not set
+# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_DEV_VIRTIO is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+CONFIG_CRYPTO_DEV_CCREE=m
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_QM=m
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
+CONFIG_CRYPTO_DEV_HISI_TRNG=m
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+CONFIG_PACKING=y
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_INDIRECT_PIO=y
+# CONFIG_TRACE_MMIO_ACCESS is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+# CONFIG_CRYPTO_LIB_CURVE25519 is not set
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+# CONFIG_CRYPTO_LIB_POLY1305 is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC64=y
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=y
+CONFIG_XXHASH=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+# CONFIG_XZ_DEC_MICROLZMA is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_RESTRICTED_POOL is not set
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+# CONFIG_FORCE_NR_CPUS is not set
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+CONFIG_CLZ_TAB=y
+CONFIG_IRQ_POLL=y
+CONFIG_MPILIB=y
+CONFIG_DIMLIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_UCS2_STRING=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_STACKDEPOT=y
+CONFIG_SBITMAP=y
+# end of Library routines
+
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_PLDMFW=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_AS_HAS_NON_CONST_LEB128=y
+CONFIG_DEBUG_INFO_NONE=y
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_DEBUG_INFO_DWARF5 is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# CONFIG_DEBUG_NET is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_PAGE_REF is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SHRINKER_DEBUG is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_INFO=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+CONFIG_DEBUG_PREEMPT=y
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_DEBUG_MAPLE_TREE is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
+CONFIG_RCU_TRACE=y
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+CONFIG_BOOTTIME_TRACING=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FUNCTION_GRAPH_TRACER=y
+CONFIG_DYNAMIC_FTRACE=y
+CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_FUNCTION_PROFILER=y
+# CONFIG_STACK_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_OSNOISE_TRACER is not set
+# CONFIG_TIMERLAT_TRACER is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_UPROBE_EVENTS=y
+CONFIG_DYNAMIC_EVENTS=y
+CONFIG_PROBE_EVENTS=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y
+# CONFIG_SYNTH_EVENTS is not set
+# CONFIG_HIST_TRIGGERS is not set
+# CONFIG_TRACE_EVENT_INJECT is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_TRACE_EVAL_MAP_FILE is not set
+# CONFIG_FTRACE_RECORD_RECURSION is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+# CONFIG_RV is not set
+# CONFIG_SAMPLES is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+
+#
+# arm64 Debugging
+#
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_CORESIGHT is not set
+# end of arm64 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_LKDTM is not set
+# CONFIG_TEST_MIN_HEAP is not set
+# CONFIG_TEST_DIV64 is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_STRING_SELFTEST is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_SCANF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_XARRAY is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_SIPHASH is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_BITOPS is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_FREE_PAGES is not set
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_MEMTEST=y
+# end of Kernel Testing and Coverage
+
+#
+# Rust hacking
+#
+# end of Rust hacking
+# end of Kernel hacking
diff --git a/nongnu/configs/quartz64b_defconfig b/nongnu/configs/quartz64b_defconfig
new file mode 100644
index 0000000..ddf719a
--- /dev/null
+++ b/nongnu/configs/quartz64b_defconfig
@@ -0,0 +1,9690 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm64 5.19.0-rc1-0.1 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 12.1.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=120100
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=23800
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=23800
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_PAHOLE_VERSION=0
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION="-MANJARO-ARM-Q64"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT=y
+# CONFIG_BPF_JIT_ALWAYS_ON is not set
+CONFIG_BPF_JIT_DEFAULT_ON=y
+# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
+CONFIG_USERMODE_DRIVER=y
+# CONFIG_BPF_PRELOAD is not set
+# end of BPF subsystem
+
+CONFIG_PREEMPT_BUILD=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+# CONFIG_SCHED_CORE is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_SCHED_AVG_IRQ=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+# CONFIG_CGROUP_MISC is not set
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SYSFS_DEPRECATED is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_ZSTD=y
+CONFIG_BOOT_CONFIG=y
+# CONFIG_BOOT_CONFIG_EMBED is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+# CONFIG_DEBUG_RSEQ is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_GUEST_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_PROFILING=y
+# end of General setup
+
+CONFIG_ARM64=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_SMP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+
+#
+# Platform selection
+#
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_BCM2835 is not set
+# CONFIG_ARCH_BCM4908 is not set
+# CONFIG_ARCH_BCM_IPROC is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_S32 is not set
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# end of Platform selection
+
+#
+# Kernel Features
+#
+
+#
+# ARM errata workarounds via the alternatives framework
+#
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
+# CONFIG_ARM64_ERRATUM_2051678 is not set
+# CONFIG_ARM64_ERRATUM_2077057 is not set
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+# end of ARM errata workarounds via the alternatives framework
+
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SCHED_MC=y
+# CONFIG_SCHED_CLUSTER is not set
+CONFIG_SCHED_SMT=y
+CONFIG_NR_CPUS=8
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_NUMA is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_PARAVIRT=y
+CONFIG_PARAVIRT_TIME_ACCOUNTING=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_SIG is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_TRANS_TABLE=y
+# CONFIG_XEN is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_COMPAT=y
+CONFIG_KUSER_HELPERS=y
+# CONFIG_ARMV8_DEPRECATED is not set
+
+#
+# ARMv8.1 architectural features
+#
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_PAN=y
+CONFIG_AS_HAS_LDAPR=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+# end of ARMv8.1 architectural features
+
+#
+# ARMv8.2 architectural features
+#
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
+# CONFIG_ARM64_PMEM is not set
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+# end of ARMv8.2 architectural features
+
+#
+# ARMv8.3 architectural features
+#
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_AS_HAS_PAC=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+# end of ARMv8.3 architectural features
+
+#
+# ARMv8.4 architectural features
+#
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_AS_HAS_ARMV8_4=y
+CONFIG_ARM64_TLB_RANGE=y
+# end of ARMv8.4 architectural features
+
+#
+# ARMv8.5 architectural features
+#
+CONFIG_AS_HAS_ARMV8_5=y
+CONFIG_ARM64_BTI=y
+CONFIG_ARM64_BTI_KERNEL=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARCH_RANDOM=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_MTE=y
+# end of ARMv8.5 architectural features
+
+#
+# ARMv8.7 architectural features
+#
+CONFIG_ARM64_EPAN=y
+# end of ARMv8.7 architectural features
+
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_MODULE_PLTS=y
+# CONFIG_ARM64_PSEUDO_NMI is not set
+CONFIG_RELOCATABLE=y
+# CONFIG_RANDOMIZE_BASE is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_ARCH_NR_GPIO=0
+# end of Kernel Features
+
+#
+# Boot options
+#
+CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
+CONFIG_CMDLINE="console=ttyAMA0"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_FORCE is not set
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+CONFIG_DMI=y
+# end of Boot options
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SUSPEND_SKIP_SYNC is not set
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_PM_SLEEP_DEBUG=y
+# CONFIG_DPM_WATCHDOG is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_IDLE_GOV_TEO is not set
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DT_IDLE_GENPD=y
+
+#
+# ARM CPU Idle Drivers
+#
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# end of ARM CPU Idle Drivers
+# end of CPU Idle
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_ACPI_CPPC_CPUFREQ=y
+CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+# end of CPU Frequency scaling
+# end of CPU Power Management
+
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ACPI=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_CCA_REQUIRED=y
+# CONFIG_ACPI_DEBUGGER is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_EC_DEBUGFS=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_CPPC_LIB=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_CUSTOM_METHOD=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_HAVE_ACPI_APEI=y
+# CONFIG_ACPI_APEI is not set
+CONFIG_ACPI_CONFIGFS=m
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_GTDT=y
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PCC=y
+CONFIG_PMIC_OPREGION=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_KVM_MMIO=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=y
+CONFIG_CRYPTO_SHA3_ARM64=y
+CONFIG_CRYPTO_SM3_ARM64_CE=y
+CONFIG_CRYPTO_SM4_ARM64_CE=y
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_POLY1305_NEON=m
+CONFIG_CRYPTO_NHPOLY1305_NEON=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+
+#
+# General architecture-dependent options
+#
+CONFIG_CRASH_CORE=y
+CONFIG_KEXEC_CORE=y
+CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
+# CONFIG_SHADOW_CALL_STACK is not set
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_COMPILER_H=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_HAS_RELR=y
+CONFIG_HAVE_PREEMPT_DYNAMIC=y
+CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS_NONE is not set
+CONFIG_MODULE_COMPRESS_GZIP=y
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_DECOMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_SED_OPAL=y
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_AIX_PARTITION=y
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+# end of Partition Types
+
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BLK_MQ_STACKING=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+# CONFIG_BFQ_CGROUP_DEBUG is not set
+# end of IO Schedulers
+
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PADATA=y
+CONFIG_ASN1=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ELFCORE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_ZPOOL=y
+CONFIG_SWAP=y
+CONFIG_ZSWAP=y
+# CONFIG_ZSWAP_DEFAULT_ON is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
+CONFIG_ZBUD=y
+CONFIG_Z3FOLD=y
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+
+#
+# SLAB allocator options
+#
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# end of SLAB allocator options
+
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_FRONTSWAP=y
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+CONFIG_CMA_DEBUGFS=y
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMA_AREAS=7
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
+# CONFIG_USERFAULTFD is not set
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_REDIRECT=y
+CONFIG_SKB_EXTENSIONS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_UNIX_DIAG=m
+CONFIG_TLS=m
+# CONFIG_TLS_DEVICE is not set
+# CONFIG_TLS_TOE is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_INTERFACE is not set
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_AH=m
+CONFIG_XFRM_ESP=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_NET_UDP_TUNNEL=m
+CONFIG_NET_FOU=m
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+# CONFIG_INET_ESP_OFFLOAD is not set
+# CONFIG_INET_ESPINTCP is not set
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_RAW_DIAG=m
+# CONFIG_INET_DIAG_DESTROY is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_TCP_CONG_CDG=m
+CONFIG_TCP_CONG_BBR=m
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+# CONFIG_INET6_ESP_OFFLOAD is not set
+# CONFIG_INET6_ESPINTCP is not set
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_ILA=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_FOU=m
+CONFIG_IPV6_FOU_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+CONFIG_IPV6_SEG6_BPF=y
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+CONFIG_NETLABEL=y
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=m
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+# CONFIG_NETFILTER_NETLINK_HOOK is not set
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_NETLINK_OSF=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NETFILTER_CONNCOUNT=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_OBJREF=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_FIB_INET=m
+CONFIG_NFT_XFRM=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+# CONFIG_NFT_SYNPROXY is not set
+CONFIG_NF_DUP_NETDEV=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+# CONFIG_NFT_REJECT_NETDEV is not set
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XTABLES_COMPAT=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPMARK=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_IPMAC=m
+CONFIG_IP_SET_HASH_MAC=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_OVF=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_MH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+# CONFIG_IP_VS_TWOS is not set
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_PE_SIP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_DUP_IPV4=m
+CONFIG_NF_LOG_ARP=m
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=y
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_DUP_IPV6=m
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_TABLES_BRIDGE=m
+# CONFIG_NFT_BRIDGE_META is not set
+CONFIG_NFT_BRIDGE_REJECT=m
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BPFILTER=y
+CONFIG_BPFILTER_UMH=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_TFRC_LIB=y
+# end of DCCP CCIDs Configuration
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+# end of DCCP Kernel Hacking
+
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_INET_SCTP_DIAG=m
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+# CONFIG_RDS_DEBUG is not set
+CONFIG_TIPC=m
+CONFIG_TIPC_MEDIA_UDP=y
+CONFIG_TIPC_CRYPTO=y
+CONFIG_TIPC_DIAG=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+# CONFIG_ATM_MPOA is not set
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_MRP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_CFM is not set
+CONFIG_NET_DSA=m
+# CONFIG_NET_DSA_TAG_AR9331 is not set
+CONFIG_NET_DSA_TAG_BRCM_COMMON=m
+CONFIG_NET_DSA_TAG_BRCM=m
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
+# CONFIG_NET_DSA_TAG_HELLCREEK is not set
+# CONFIG_NET_DSA_TAG_GSWIP is not set
+CONFIG_NET_DSA_TAG_DSA_COMMON=m
+CONFIG_NET_DSA_TAG_DSA=m
+CONFIG_NET_DSA_TAG_EDSA=m
+# CONFIG_NET_DSA_TAG_MTK is not set
+# CONFIG_NET_DSA_TAG_KSZ is not set
+# CONFIG_NET_DSA_TAG_OCELOT is not set
+# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
+CONFIG_NET_DSA_TAG_QCA=m
+# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_RTL8_4 is not set
+# CONFIG_NET_DSA_TAG_LAN9303 is not set
+# CONFIG_NET_DSA_TAG_SJA1105 is not set
+CONFIG_NET_DSA_TAG_TRAILER=m
+# CONFIG_NET_DSA_TAG_XRS700X is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+CONFIG_6LOWPAN=m
+# CONFIG_6LOWPAN_DEBUGFS is not set
+CONFIG_6LOWPAN_NHC=m
+CONFIG_6LOWPAN_NHC_DEST=m
+CONFIG_6LOWPAN_NHC_FRAGMENT=m
+CONFIG_6LOWPAN_NHC_HOP=m
+CONFIG_6LOWPAN_NHC_IPV6=m
+CONFIG_6LOWPAN_NHC_MOBILITY=m
+CONFIG_6LOWPAN_NHC_ROUTING=m
+CONFIG_6LOWPAN_NHC_UDP=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
+CONFIG_6LOWPAN_GHC_UDP=m
+CONFIG_6LOWPAN_GHC_ICMPV6=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
+CONFIG_IEEE802154=m
+# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
+CONFIG_IEEE802154_SOCKET=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_CBS=m
+# CONFIG_NET_SCH_ETF is not set
+# CONFIG_NET_SCH_TAPRIO is not set
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+# CONFIG_NET_SCH_SKBPRIO is not set
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=y
+# CONFIG_NET_SCH_CAKE is not set
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+# CONFIG_NET_SCH_FQ_PIE is not set
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+# CONFIG_NET_SCH_ETS is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_CANID=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_EMATCH_IPT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_SAMPLE=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+# CONFIG_NET_ACT_MPLS is not set
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
+# CONFIG_NET_ACT_CTINFO is not set
+CONFIG_NET_ACT_SKBMOD=m
+CONFIG_NET_ACT_IFE=m
+CONFIG_NET_ACT_TUNNEL_KEY=m
+# CONFIG_NET_ACT_CT is not set
+# CONFIG_NET_ACT_GATE is not set
+CONFIG_NET_IFE_SKBMARK=m
+CONFIG_NET_IFE_SKBPRIO=m
+CONFIG_NET_IFE_SKBTCINDEX=m
+# CONFIG_NET_TC_SKB_EXT is not set
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+# CONFIG_BATMAN_ADV_BATMAN_V is not set
+CONFIG_BATMAN_ADV_BLA=y
+CONFIG_BATMAN_ADV_DAT=y
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_BATMAN_ADV_MCAST=y
+# CONFIG_BATMAN_ADV_DEBUG is not set
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH_VXLAN=m
+CONFIG_OPENVSWITCH_GENEVE=m
+CONFIG_VSOCKETS=m
+CONFIG_VSOCKETS_DIAG=m
+CONFIG_VSOCKETS_LOOPBACK=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS_COMMON=m
+CONFIG_NETLINK_DIAG=m
+CONFIG_MPLS=y
+CONFIG_NET_MPLS_GSO=m
+CONFIG_MPLS_ROUTING=m
+# CONFIG_MPLS_IPTUNNEL is not set
+CONFIG_NET_NSH=m
+# CONFIG_HSR is not set
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_L3_MASTER_DEV=y
+CONFIG_QRTR=m
+CONFIG_QRTR_SMD=m
+CONFIG_QRTR_TUN=m
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# end of Network testing
+# end of Networking options
+
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+CONFIG_AX25=m
+CONFIG_AX25_DAMA_SLAVE=y
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+
+#
+# AX.25 network device drivers
+#
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_YAM=m
+# end of AX.25 network device drivers
+
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_GW=m
+# CONFIG_CAN_J1939 is not set
+# CONFIG_CAN_ISOTP is not set
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_DEV=m
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_FLEXCAN is not set
+# CONFIG_CAN_GRCAN is not set
+# CONFIG_CAN_KVASER_PCIEFD is not set
+# CONFIG_CAN_XILINXCAN is not set
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_CAN_C_CAN_PCI=m
+CONFIG_CAN_CC770=m
+# CONFIG_CAN_CC770_ISA is not set
+CONFIG_CAN_CC770_PLATFORM=m
+# CONFIG_CAN_CTUCANFD_PCI is not set
+# CONFIG_CAN_CTUCANFD_PLATFORM is not set
+# CONFIG_CAN_IFI_CANFD is not set
+CONFIG_CAN_M_CAN=m
+# CONFIG_CAN_M_CAN_PCI is not set
+# CONFIG_CAN_M_CAN_PLATFORM is not set
+# CONFIG_CAN_M_CAN_TCAN4X5X is not set
+# CONFIG_CAN_PEAK_PCIEFD is not set
+CONFIG_CAN_SJA1000=m
+CONFIG_CAN_EMS_PCI=m
+# CONFIG_CAN_F81601 is not set
+CONFIG_CAN_KVASER_PCI=m
+CONFIG_CAN_PEAK_PCI=m
+CONFIG_CAN_PEAK_PCIEC=y
+CONFIG_CAN_PLX_PCI=m
+# CONFIG_CAN_SJA1000_ISA is not set
+CONFIG_CAN_SJA1000_PLATFORM=m
+CONFIG_CAN_SOFTING=m
+
+#
+# CAN SPI interfaces
+#
+# CONFIG_CAN_HI311X is not set
+# CONFIG_CAN_MCP251X is not set
+# CONFIG_CAN_MCP251XFD is not set
+# end of CAN SPI interfaces
+
+#
+# CAN USB interfaces
+#
+CONFIG_CAN_8DEV_USB=m
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_USB2=m
+# CONFIG_CAN_ETAS_ES58X is not set
+CONFIG_CAN_GS_USB=m
+CONFIG_CAN_KVASER_USB=m
+# CONFIG_CAN_MCBA_USB is not set
+CONFIG_CAN_PEAK_USB=m
+# CONFIG_CAN_UCAN is not set
+# end of CAN USB interfaces
+
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# end of CAN Device Drivers
+
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_6LOWPAN=m
+# CONFIG_BT_LEDS is not set
+# CONFIG_BT_MSFTEXT is not set
+# CONFIG_BT_AOSPEXT is not set
+# CONFIG_BT_DEBUGFS is not set
+# CONFIG_BT_SELFTEST is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_QCA=m
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+CONFIG_BT_HCIBTUSB_BCM=y
+# CONFIG_BT_HCIBTUSB_MTK is not set
+CONFIG_BT_HCIBTUSB_RTL=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_NOKIA is not set
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
+# CONFIG_BT_HCIUART_AG6XX is not set
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+# CONFIG_BT_MTKSDIO is not set
+# CONFIG_BT_MTKUART is not set
+CONFIG_BT_HCIRSI=m
+# CONFIG_BT_VIRTIO is not set
+# end of Bluetooth device drivers
+
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+CONFIG_STREAM_PARSER=y
+# CONFIG_MCTP is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_CERTIFICATION_ONUS=y
+# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set
+# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set
+# CONFIG_CFG80211_REG_RELAX_NO_IR is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P_VIRTIO=m
+# CONFIG_NET_9P_DEBUG is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+CONFIG_NFC=m
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_NCI=m
+# CONFIG_NFC_NCI_SPI is not set
+# CONFIG_NFC_NCI_UART is not set
+CONFIG_NFC_HCI=m
+CONFIG_NFC_SHDLC=y
+
+#
+# Near Field Communication (NFC) devices
+#
+# CONFIG_NFC_TRF7970A is not set
+CONFIG_NFC_SIM=m
+CONFIG_NFC_PORT100=m
+# CONFIG_NFC_VIRTUAL_NCI is not set
+# CONFIG_NFC_FDP is not set
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PN544_I2C=m
+# CONFIG_NFC_PN533_USB is not set
+# CONFIG_NFC_PN533_I2C is not set
+# CONFIG_NFC_PN532_UART is not set
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_USB=m
+# CONFIG_NFC_MRVL_I2C is not set
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST21NFCA_I2C=m
+# CONFIG_NFC_ST_NCI_I2C is not set
+# CONFIG_NFC_ST_NCI_SPI is not set
+# CONFIG_NFC_NXP_NCI is not set
+# CONFIG_NFC_S3FWRN5_I2C is not set
+# CONFIG_NFC_S3FWRN82_UART is not set
+# CONFIG_NFC_ST95HF is not set
+# end of Near Field Communication (NFC) devices
+
+CONFIG_PSAMPLE=m
+CONFIG_NET_IFE=m
+CONFIG_LWTUNNEL=y
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SOCK_MSG=y
+CONFIG_NET_DEVLINK=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PAGE_POOL_STATS is not set
+CONFIG_FAILOVER=m
+CONFIG_ETHTOOL_NETLINK=y
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+CONFIG_PCI_STUB=y
+# CONFIG_PCI_PF_STUB is not set
+CONFIG_PCI_ATS=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_LABEL=y
+# CONFIG_PCIE_BUS_TUNE_OFF is not set
+CONFIG_PCIE_BUS_DEFAULT=y
+# CONFIG_PCIE_BUS_SAFE is not set
+# CONFIG_PCIE_BUS_PERFORMANCE is not set
+# CONFIG_PCIE_BUS_PEER2PEER is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# PCI controller drivers
+#
+# CONFIG_PCI_FTPCI100 is not set
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCIE_XILINX is not set
+CONFIG_PCI_XGENE=y
+CONFIG_PCI_XGENE_MSI=y
+# CONFIG_PCIE_ALTERA is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+# CONFIG_PCIE_MICROCHIP_HOST is not set
+
+#
+# DesignWare PCI Core Support
+#
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCI_HISI=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+# CONFIG_PCIE_KIRIN is not set
+CONFIG_PCI_MESON=y
+# CONFIG_PCIE_AL is not set
+# end of DesignWare PCI Core Support
+
+#
+# Mobiveil PCIe Core Support
+#
+# end of Mobiveil PCIe Core Support
+
+#
+# Cadence PCIe controllers support
+#
+# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
+# CONFIG_PCI_J721E_HOST is not set
+# end of Cadence PCIe controllers support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_CXL_BUS is not set
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_AUXILIARY_BUS=y
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FW_LOADER_USER_HELPER=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
+CONFIG_FW_CACHE=y
+# CONFIG_FW_UPLOAD is not set
+# end of Firmware loader
+
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+CONFIG_DEBUG_DEVRES=y
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
+CONFIG_VEXPRESS_CONFIG=y
+# CONFIG_MHI_BUS is not set
+# CONFIG_MHI_BUS_EP is not set
+# end of Bus devices
+
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+# CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_ISCSI_IBFT=y
+# CONFIG_FW_CFG_SYSFS is not set
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+# CONFIG_ARM_FFA_TRANSPORT is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+# CONFIG_EFI_TEST is not set
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+
+#
+# Partition parsers
+#
+# CONFIG_MTD_AR7_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_OF_PARTS=m
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# end of Partition parsers
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_BLOCK_RO is not set
+
+#
+# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
+#
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_PARTITIONED_MASTER is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# end of RAM/ROM/Flash chip drivers
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PHYSMAP_VERSATILE is not set
+# CONFIG_MTD_PHYSMAP_GEMINI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+# end of Mapping drivers for chip access
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_MCHP48L640 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# end of Self-contained MTD device drivers
+
+#
+# NAND
+#
+CONFIG_MTD_NAND_CORE=y
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_RAW_NAND=y
+
+#
+# Raw/parallel NAND flash controllers
+#
+# CONFIG_MTD_NAND_DENALI_PCI is not set
+# CONFIG_MTD_NAND_DENALI_DT is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_BRCMNAND is not set
+# CONFIG_MTD_NAND_MXIC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_CADENCE is not set
+# CONFIG_MTD_NAND_ARASAN is not set
+# CONFIG_MTD_NAND_INTEL_LGM is not set
+# CONFIG_MTD_NAND_ROCKCHIP is not set
+
+#
+# Misc
+#
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_SPI_NAND=m
+
+#
+# ECC engine support
+#
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
+# CONFIG_MTD_NAND_ECC_SW_BCH is not set
+# CONFIG_MTD_NAND_ECC_MXIC is not set
+# end of ECC engine support
+# end of NAND
+
+#
+# LPDDR & LPDDR2 PCM memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# end of LPDDR & LPDDR2 PCM memory drivers
+
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
+CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
+# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_BLOCK is not set
+# CONFIG_MTD_HYPERBUS is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_NULL_BLK=m
+CONFIG_CDROM=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+CONFIG_ZRAM=m
+CONFIG_ZRAM_DEF_COMP_LZORLE=y
+# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
+# CONFIG_ZRAM_DEF_COMP_LZO is not set
+# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
+# CONFIG_ZRAM_DEF_COMP_842 is not set
+CONFIG_ZRAM_DEF_COMP="lzo-rle"
+# CONFIG_ZRAM_WRITEBACK is not set
+# CONFIG_ZRAM_MEMORY_TRACKING is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
+CONFIG_BLK_DEV_DRBD=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_BLK_DEV_RBD=m
+
+#
+# NVME Support
+#
+CONFIG_NVME_CORE=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+CONFIG_NVME_HWMON=y
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+CONFIG_SENSORS_LIS3LV02D=m
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+CONFIG_TIFM_CORE=y
+CONFIG_TIFM_7XX1=m
+# CONFIG_ICS932S401 is not set
+CONFIG_ENCLOSURE_SERVICES=m
+# CONFIG_HI6421V600_IRQ is not set
+# CONFIG_HP_ILO is not set
+CONFIG_APDS9802ALS=m
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_BH1770=m
+CONFIG_SENSORS_APDS990X=m
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_SRAM=y
+# CONFIG_DW_XDATA_PCIE is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_OPEN_DICE is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+# CONFIG_EEPROM_AT25 is not set
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+CONFIG_CB710_CORE=y
+# CONFIG_CB710_DEBUG is not set
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_ALTERA_STAPL=m
+# CONFIG_VMWARE_VMCI is not set
+# CONFIG_GENWQE is not set
+CONFIG_ECHO=m
+# CONFIG_BCM_VK is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_HABANA_AI is not set
+# CONFIG_UACCE is not set
+# CONFIG_PVPANIC is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+CONFIG_RAID_ATTRS=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SRP_ATTRS=m
+# end of SCSI Transports
+
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=y
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_BE2ISCSI=m
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+CONFIG_SCSI_HPSA=m
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_HISI_SAS is not set
+CONFIG_SCSI_MVSAS=m
+# CONFIG_SCSI_MVSAS_DEBUG is not set
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+# CONFIG_SCSI_ADVANSYS is not set
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_SAS=m
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_MPI3MR is not set
+# CONFIG_SCSI_SMARTPQI is not set
+CONFIG_SCSI_HPTIOP=m
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_FCOE=m
+CONFIG_SCSI_SNIC=m
+# CONFIG_SCSI_SNIC_DEBUG_FS is not set
+CONFIG_SCSI_DMX3191D=m
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_IPS is not set
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPR_DUMP=y
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_QLA_FC=m
+CONFIG_TCM_QLA2XXX=m
+# CONFIG_TCM_QLA2XXX_DEBUG is not set
+CONFIG_SCSI_QLA_ISCSI=m
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_EFCT is not set
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_PMCRAID=m
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_BFA_FC is not set
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_ALUA=m
+# end of SCSI device support
+
+CONFIG_HAVE_PATA_PLATFORM=y
+CONFIG_ATA=y
+CONFIG_SATA_HOST=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_ACPI=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_CEVA is not set
+CONFIG_AHCI_XGENE=y
+# CONFIG_AHCI_QORIQ is not set
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+CONFIG_PDC_ADMA=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SX4=m
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+CONFIG_ATA_PIIX=y
+# CONFIG_SATA_DWC is not set
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+
+#
+# PATA SFF controllers with BMDMA
+#
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATIIXP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_CYPRESS=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3=m
+# CONFIG_PATA_HPT3X3_DMA is not set
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OLDPIIX=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+# CONFIG_PATA_RADISYS is not set
+CONFIG_PATA_RDC=m
+CONFIG_PATA_SCH=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PATA_TRIFLEX=m
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
+
+#
+# PIO-only SFF controllers
+#
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_MPIIX=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_PATA_ACPI is not set
+CONFIG_ATA_GENERIC=m
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_MD_CLUSTER=m
+CONFIG_BCACHE=m
+# CONFIG_BCACHE_DEBUG is not set
+# CONFIG_BCACHE_CLOSURES_DEBUG is not set
+# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_BUFIO=y
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_PERSISTENT_DATA=m
+# CONFIG_DM_UNSTRIPED is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_WRITECACHE=m
+# CONFIG_DM_EBS is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_CLONE is not set
+CONFIG_DM_MIRROR=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_ZERO=y
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+# CONFIG_DM_MULTIPATH_HST is not set
+# CONFIG_DM_MULTIPATH_IOA is not set
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_INIT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_SWITCH=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_INTEGRITY=m
+CONFIG_DM_ZONED=m
+CONFIG_DM_AUDIT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_USER2=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_TCM_FC=m
+CONFIG_ISCSI_TARGET=m
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+CONFIG_FIREWIRE_NOSY=m
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=m
+CONFIG_NET_CORE=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+CONFIG_EQUALIZER=m
+CONFIG_NET_FC=y
+CONFIG_IFB=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_VXLAN=m
+CONFIG_GENEVE=m
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+# CONFIG_AMT is not set
+# CONFIG_MACSEC is not set
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_TUN=m
+CONFIG_TAP=m
+# CONFIG_TUN_VNET_CROSS_LE is not set
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=m
+CONFIG_NLMON=m
+CONFIG_NET_VRF=m
+# CONFIG_VSOCKMON is not set
+# CONFIG_ARCNET is not set
+# CONFIG_ATM_DRIVERS is not set
+
+#
+# Distributed Switch Architecture drivers
+#
+CONFIG_B53=m
+# CONFIG_B53_SPI_DRIVER is not set
+# CONFIG_B53_MDIO_DRIVER is not set
+# CONFIG_B53_MMAP_DRIVER is not set
+# CONFIG_B53_SRAB_DRIVER is not set
+# CONFIG_B53_SERDES is not set
+CONFIG_NET_DSA_BCM_SF2=m
+# CONFIG_NET_DSA_LOOP is not set
+# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
+# CONFIG_NET_DSA_MT7530 is not set
+CONFIG_NET_DSA_MV88E6060=m
+# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
+CONFIG_NET_DSA_MV88E6XXX=m
+CONFIG_NET_DSA_MV88E6XXX_PTP=y
+# CONFIG_NET_DSA_MSCC_SEVILLE is not set
+# CONFIG_NET_DSA_AR9331 is not set
+# CONFIG_NET_DSA_SJA1105 is not set
+# CONFIG_NET_DSA_XRS700X_I2C is not set
+# CONFIG_NET_DSA_XRS700X_MDIO is not set
+CONFIG_NET_DSA_QCA8K=m
+# CONFIG_NET_DSA_REALTEK is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_MDIO=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_ET131X=m
+CONFIG_NET_VENDOR_ALACRITECH=y
+# CONFIG_SLICOSS is not set
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_ACENIC=m
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+CONFIG_ALTERA_TSE=m
+CONFIG_NET_VENDOR_AMAZON=y
+# CONFIG_ENA_ETHERNET is not set
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_AMD8111_ETH=m
+CONFIG_PCNET32=m
+CONFIG_AMD_XGBE=m
+# CONFIG_AMD_XGBE_DCB is not set
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_AQTION=m
+CONFIG_NET_VENDOR_ARC=y
+# CONFIG_EMAC_ROCKCHIP is not set
+CONFIG_NET_VENDOR_ASIX=y
+# CONFIG_SPI_AX88796C is not set
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_ATL2=m
+CONFIG_ATL1=m
+CONFIG_ATL1E=m
+CONFIG_ATL1C=m
+CONFIG_ALX=m
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_B44=m
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI=y
+CONFIG_BCMGENET=m
+CONFIG_BNX2=m
+CONFIG_CNIC=m
+CONFIG_TIGON3=m
+CONFIG_TIGON3_HWMON=y
+CONFIG_BNX2X=m
+CONFIG_BNX2X_SRIOV=y
+# CONFIG_SYSTEMPORT is not set
+# CONFIG_BNXT is not set
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_MACB=m
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MACB_PCI is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_GEMINI_ETHERNET is not set
+CONFIG_NET_VENDOR_DAVICOM=y
+# CONFIG_DM9051 is not set
+CONFIG_DNET=m
+# CONFIG_NET_VENDOR_DEC is not set
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_DL2K=m
+CONFIG_SUNDANCE=m
+# CONFIG_SUNDANCE_MMIO is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+CONFIG_NET_VENDOR_ENGLEDER=y
+# CONFIG_TSNEP is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+CONFIG_NET_VENDOR_FUNGIBLE=y
+# CONFIG_FUN_ETH is not set
+CONFIG_NET_VENDOR_GOOGLE=y
+# CONFIG_GVE is not set
+CONFIG_NET_VENDOR_HISILICON=y
+CONFIG_HIX5HD2_GMAC=m
+# CONFIG_HISI_FEMAC is not set
+CONFIG_HIP04_ETH=m
+# CONFIG_HI13X1_GMAC is not set
+CONFIG_HNS_MDIO=m
+CONFIG_HNS=m
+CONFIG_HNS_DSAF=m
+CONFIG_HNS_ENET=m
+# CONFIG_HNS3 is not set
+CONFIG_NET_VENDOR_HUAWEI=y
+# CONFIG_HINIC is not set
+# CONFIG_NET_VENDOR_I825XX is not set
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGB_HWMON=y
+CONFIG_IGBVF=m
+CONFIG_IXGB=m
+CONFIG_IXGBE=m
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBEVF=m
+CONFIG_I40E=m
+# CONFIG_I40E_DCB is not set
+CONFIG_IAVF=m
+CONFIG_I40EVF=m
+# CONFIG_ICE is not set
+CONFIG_FM10K=m
+# CONFIG_IGC is not set
+CONFIG_JME=m
+CONFIG_NET_VENDOR_LITEX=y
+# CONFIG_LITEX_LITEETH is not set
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_MVMDIO=m
+CONFIG_SKGE=m
+# CONFIG_SKGE_DEBUG is not set
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+# CONFIG_SKY2_DEBUG is not set
+# CONFIG_OCTEONTX2_AF is not set
+# CONFIG_OCTEONTX2_PF is not set
+# CONFIG_OCTEON_EP is not set
+# CONFIG_PRESTERA is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_CORE=m
+CONFIG_MLX4_DEBUG=y
+CONFIG_MLX4_CORE_GEN2=y
+# CONFIG_MLX5_CORE is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLXFW is not set
+# CONFIG_MLXBF_GIGE is not set
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_KSZ884X_PCI=m
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCX24J600 is not set
+# CONFIG_LAN743X is not set
+# CONFIG_LAN966X_SWITCH is not set
+CONFIG_NET_VENDOR_MICROSEMI=y
+# CONFIG_MSCC_OCELOT_SWITCH is not set
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_MYRI10GE=m
+CONFIG_FEALNX=m
+CONFIG_NET_VENDOR_NI=y
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NATSEMI=m
+CONFIG_NS83820=m
+CONFIG_NET_VENDOR_NETERION=y
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+CONFIG_NET_VENDOR_NETRONOME=y
+# CONFIG_NFP is not set
+CONFIG_NET_VENDOR_8390=y
+CONFIG_NE2K_PCI=m
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_FORCEDETH=m
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_ETHOC=m
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_HAMACHI=m
+CONFIG_YELLOWFIN=m
+CONFIG_NET_VENDOR_PENSANDO=y
+# CONFIG_IONIC is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_R6040=m
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+CONFIG_8139TOO_8129=y
+# CONFIG_8139_OLD_RX_RESET is not set
+CONFIG_R8169=m
+# CONFIG_NET_VENDOR_RENESAS is not set
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_ROCKER=m
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_SC92031=m
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_SIS900=m
+CONFIG_SIS190=m
+CONFIG_NET_VENDOR_SOLARFLARE=y
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
+# CONFIG_SFC_SIENA is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=m
+CONFIG_EPIC100=m
+CONFIG_SMSC911X=m
+CONFIG_SMSC9420=m
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=m
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=m
+CONFIG_DWMAC_DWC_QOS_ETH=m
+CONFIG_DWMAC_GENERIC=m
+CONFIG_DWMAC_ROCKCHIP=m
+# CONFIG_DWMAC_INTEL_PLAT is not set
+# CONFIG_DWMAC_LOONGSON is not set
+# CONFIG_STMMAC_PCI is not set
+# CONFIG_NET_VENDOR_SUN is not set
+CONFIG_NET_VENDOR_SYNOPSYS=y
+# CONFIG_DWC_XLGMAC is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_TEHUTI=m
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VERTEXCOM=y
+# CONFIG_MSE102X is not set
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_VELOCITY=m
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_NET_VENDOR_XILINX=y
+# CONFIG_XILINX_EMACLITE is not set
+# CONFIG_XILINX_AXI_EMAC is not set
+# CONFIG_XILINX_LL_TEMAC is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_NET_SB1000=y
+CONFIG_PHYLINK=m
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_SFP=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_AMD_PHY=m
+# CONFIG_ADIN_PHY is not set
+# CONFIG_ADIN1100_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+CONFIG_AX88796B_PHY=m
+CONFIG_BROADCOM_PHY=m
+# CONFIG_BCM54140_PHY is not set
+CONFIG_BCM7XXX_PHY=m
+# CONFIG_BCM84881_PHY is not set
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_CICADA_PHY=m
+# CONFIG_CORTINA_PHY is not set
+CONFIG_DAVICOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_LXT_PHY=m
+# CONFIG_INTEL_XWAY_PHY is not set
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+CONFIG_MICREL_PHY=m
+CONFIG_MICROCHIP_PHY=m
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_NATIONAL_PHY=m
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+CONFIG_AT803X_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_REALTEK_PHY=m
+# CONFIG_RENESAS_PHY is not set
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_SMSC_PHY=m
+CONFIG_STE10XP=m
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+CONFIG_DP83848_PHY=m
+CONFIG_DP83867_PHY=m
+# CONFIG_DP83869_PHY is not set
+# CONFIG_DP83TD510_PHY is not set
+CONFIG_VITESSE_PHY=m
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_OF_MDIO=y
+CONFIG_ACPI_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=m
+CONFIG_MDIO_BCM_UNIMAC=m
+# CONFIG_MDIO_GPIO is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+CONFIG_MDIO_I2C=m
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+# CONFIG_MDIO_THUNDER is not set
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=m
+CONFIG_MDIO_BUS_MUX_GPIO=m
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+CONFIG_MDIO_BUS_MUX_MMIOREG=m
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=m
+# end of PCS device drivers
+
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLHC=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+# CONFIG_SLIP_MODE_SLIP6 is not set
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_USB_NET_CH9200=m
+# CONFIG_USB_NET_AQC111 is not set
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_WLAN=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_ADM8211=m
+CONFIG_ATH_COMMON=m
+CONFIG_WLAN_VENDOR_ATH=y
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set
+CONFIG_ATH5K=m
+CONFIG_ATH5K_DEBUG=y
+CONFIG_ATH5K_PCI=y
+# CONFIG_ATH5K_TEST_CHANNELS is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_COMMON_DEBUG=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_DEBUGFS=y
+# CONFIG_ATH9K_STATION_STATISTICS is not set
+# CONFIG_ATH9K_TX99 is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_DYNACK is not set
+# CONFIG_ATH9K_WOW is not set
+CONFIG_ATH9K_RFKILL=y
+# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
+CONFIG_ATH9K_PCOEM=y
+# CONFIG_ATH9K_PCI_NO_EEPROM is not set
+CONFIG_ATH9K_HTC=m
+# CONFIG_ATH9K_HTC_DEBUGFS is not set
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K_COMMON_SPECTRAL=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+# CONFIG_CARL9170_DEBUGFS is not set
+CONFIG_CARL9170_WPC=y
+# CONFIG_CARL9170_HWRNG is not set
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_ATH6KL_DEBUG=y
+# CONFIG_ATH6KL_REGDOMAIN is not set
+CONFIG_AR5523=m
+CONFIG_WIL6210=m
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_WIL6210_DEBUGFS=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K_PCI=m
+# CONFIG_ATH10K_AHB is not set
+# CONFIG_ATH10K_SDIO is not set
+# CONFIG_ATH10K_USB is not set
+# CONFIG_ATH10K_DEBUG is not set
+CONFIG_ATH10K_DEBUGFS=y
+# CONFIG_ATH10K_SPECTRAL is not set
+# CONFIG_ATH10K_DFS_CERTIFIED is not set
+CONFIG_WCN36XX=m
+# CONFIG_WCN36XX_DEBUGFS is not set
+# CONFIG_ATH11K is not set
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_ATMEL=m
+CONFIG_PCI_ATMEL=m
+CONFIG_AT76C50X_USB=m
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_B43=m
+CONFIG_B43_BCMA=y
+CONFIG_B43_SSB=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+# CONFIG_B43_BUSES_BCMA is not set
+# CONFIG_B43_BUSES_SSB is not set
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_PIO=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_HWRNG=y
+CONFIG_B43_DEBUG=y
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_PCI_AUTOSELECT=y
+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_DEBUG=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
+CONFIG_BRCMUTIL=m
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMSMAC_LEDS=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMFMAC_PCIE=y
+# CONFIG_BRCM_TRACING is not set
+# CONFIG_BRCMDBG is not set
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+# CONFIG_IPW2100_DEBUG is not set
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+# CONFIG_IPW2200_DEBUG is not set
+CONFIG_LIBIPW=m
+# CONFIG_LIBIPW_DEBUG is not set
+CONFIG_IWLEGACY=m
+CONFIG_IWL4965=m
+CONFIG_IWL3945=m
+
+#
+# iwl3945 / iwl4965 Debugging Options
+#
+CONFIG_IWLEGACY_DEBUG=y
+CONFIG_IWLEGACY_DEBUGFS=y
+# end of iwl3945 / iwl4965 Debugging Options
+
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLDVM=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+
+#
+# Debugging Options
+#
+CONFIG_IWLWIFI_DEBUG=y
+CONFIG_IWLWIFI_DEBUGFS=y
+# end of Debugging Options
+
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOSTAP_PCI=m
+CONFIG_HERMES=m
+CONFIG_HERMES_PRISM=y
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_PLX_HERMES=m
+CONFIG_TMD_HERMES=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_PCI_HERMES=m
+CONFIG_ORINOCO_USB=m
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+CONFIG_P54_PCI=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_MT7601U=m
+# CONFIG_MT76x0U is not set
+# CONFIG_MT76x0E is not set
+# CONFIG_MT76x2E is not set
+# CONFIG_MT76x2U is not set
+# CONFIG_MT7603E is not set
+# CONFIG_MT7615E is not set
+# CONFIG_MT7663U is not set
+# CONFIG_MT7663S is not set
+# CONFIG_MT7915E is not set
+# CONFIG_MT7921E is not set
+# CONFIG_MT7921S is not set
+# CONFIG_MT7921U is not set
+CONFIG_WLAN_VENDOR_MICROCHIP=y
+# CONFIG_WILC1000_SDIO is not set
+# CONFIG_WILC1000_SPI is not set
+CONFIG_WLAN_VENDOR_PURELIFI=y
+# CONFIG_PLFXLC is not set
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_RT2X00=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT61PCI=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB_DEBUGFS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL_CARDS=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192DE=m
+# CONFIG_RTL8723AE is not set
+# CONFIG_RTL8723BE is not set
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTLWIFI_DEBUG=y
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL8XXXU=m
+# CONFIG_RTL8XXXU_UNTESTED is not set
+# CONFIG_RTW88 is not set
+# CONFIG_RTW89 is not set
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_RSI_91X=m
+CONFIG_RSI_DEBUGFS=y
+CONFIG_RSI_SDIO=m
+CONFIG_RSI_USB=m
+CONFIG_RSI_COEX=y
+CONFIG_WLAN_VENDOR_SILABS=y
+# CONFIG_WFX is not set
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+# CONFIG_CW1200_WLAN_SPI is not set
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WILINK_PLATFORM_DATA=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_USB_ZD1201=m
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_MAC80211_HWSIM=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+CONFIG_IEEE802154_DRIVERS=m
+CONFIG_IEEE802154_FAKELB=m
+# CONFIG_IEEE802154_AT86RF230 is not set
+# CONFIG_IEEE802154_MRF24J40 is not set
+# CONFIG_IEEE802154_CC2520 is not set
+CONFIG_IEEE802154_ATUSB=m
+# CONFIG_IEEE802154_ADF7242 is not set
+# CONFIG_IEEE802154_CA8210 is not set
+# CONFIG_IEEE802154_MCR20A is not set
+# CONFIG_IEEE802154_HWSIM is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+# CONFIG_VMXNET3 is not set
+# CONFIG_FUJITSU_ES is not set
+# CONFIG_NETDEVSIM is not set
+CONFIG_NET_FAILOVER=m
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ADC=m
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
+CONFIG_MOUSE_PS2_SENTELIC=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+CONFIG_MOUSE_CYAPA=m
+CONFIG_MOUSE_ELAN_I2C=y
+CONFIG_MOUSE_ELAN_I2C_I2C=y
+CONFIG_MOUSE_ELAN_I2C_SMBUS=y
+CONFIG_MOUSE_VSXXXAA=m
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_SYNAPTICS_I2C=m
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADC is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_ZHENHUA=m
+# CONFIG_JOYSTICK_AS5011 is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+# CONFIG_JOYSTICK_PSXPAD_SPI is not set
+# CONFIG_JOYSTICK_PXRC is not set
+# CONFIG_JOYSTICK_QWIIC is not set
+# CONFIG_JOYSTICK_FSIA6B is not set
+# CONFIG_JOYSTICK_SENSEHAT is not set
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_PEGASUS=m
+CONFIG_TABLET_SERIAL_WACOM4=m
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ADC is not set
+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_BU21029 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+CONFIG_TOUCHSCREEN_DYNAPRO=m
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+CONFIG_TOUCHSCREEN_EETI=m
+CONFIG_TOUCHSCREEN_EGALAX=m
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
+# CONFIG_TOUCHSCREEN_EXC3000 is not set
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX=y
+# CONFIG_TOUCHSCREEN_HIDEEP is not set
+# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
+CONFIG_TOUCHSCREEN_ILI210X=m
+# CONFIG_TOUCHSCREEN_ILITEK is not set
+# CONFIG_TOUCHSCREEN_S6SY761 is not set
+CONFIG_TOUCHSCREEN_GUNZE=m
+# CONFIG_TOUCHSCREEN_EKTF2127 is not set
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+CONFIG_TOUCHSCREEN_MCS5000=m
+CONFIG_TOUCHSCREEN_MMS114=m
+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
+# CONFIG_TOUCHSCREEN_MSG2638 is not set
+CONFIG_TOUCHSCREEN_MTOUCH=m
+# CONFIG_TOUCHSCREEN_IMAGIS is not set
+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_MK712=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+CONFIG_TOUCHSCREEN_TSC2007=m
+# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
+# CONFIG_TOUCHSCREEN_RM_TS is not set
+# CONFIG_TOUCHSCREEN_SILEAD is not set
+# CONFIG_TOUCHSCREEN_SIS_I2C is not set
+CONFIG_TOUCHSCREEN_ST1232=m
+# CONFIG_TOUCHSCREEN_STMFTS is not set
+# CONFIG_TOUCHSCREEN_SUR40 is not set
+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZET6223 is not set
+CONFIG_TOUCHSCREEN_ZFORCE=m
+# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
+# CONFIG_TOUCHSCREEN_IQS5XX is not set
+# CONFIG_TOUCHSCREEN_ZINITIX is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+CONFIG_INPUT_E3X0_BUTTON=m
+CONFIG_INPUT_MMA8450=m
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_KXTJ9=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_CM109=m
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+CONFIG_INPUT_PWM_BEEPER=m
+# CONFIG_INPUT_PWM_VIBRA is not set
+CONFIG_INPUT_RK805_PWRKEY=y
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_IQS7222 is not set
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CMA3000_I2C=m
+# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_RMI4_CORE=m
+# CONFIG_RMI4_I2C is not set
+# CONFIG_RMI4_SPI is not set
+# CONFIG_RMI4_SMB is not set
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+# CONFIG_RMI4_F34 is not set
+# CONFIG_RMI4_F3A is not set
+# CONFIG_RMI4_F54 is not set
+# CONFIG_RMI4_F55 is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_AMBAKMI=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_ALTERA_PS2=m
+# CONFIG_SERIO_PS2MULT is not set
+CONFIG_SERIO_ARC_PS2=m
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_GPIO_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LDISC_AUTOLOAD=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_PNP=y
+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=m
+CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
+# CONFIG_SERIAL_KGDB_NMI is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_CONSOLE_POLL=y
+CONFIG_SERIAL_JSM=m
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+# CONFIG_SERIAL_RP2 is not set
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+CONFIG_SYNCLINK_GT=m
+CONFIG_N_HDLC=m
+CONFIG_N_GSM=m
+CONFIG_NOZOMI=m
+# CONFIG_NULL_TTY is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_HVC_DCC is not set
+# CONFIG_RPMSG_TTY is not set
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+# CONFIG_TTY_PRINTK is not set
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_PLAT_DATA=y
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+# CONFIG_IPMI_IPMB is not set
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+# CONFIG_IPMB_DEVICE_INTERFACE is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+# CONFIG_HW_RANDOM_BA431 is not set
+CONFIG_HW_RANDOM_VIRTIO=m
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+CONFIG_HW_RANDOM_CN10K=y
+# CONFIG_APPLICOM is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+CONFIG_TCG_TPM=y
+CONFIG_HW_RANDOM_TPM=y
+# CONFIG_TCG_TIS is not set
+# CONFIG_TCG_TIS_SPI is not set
+# CONFIG_TCG_TIS_I2C_CR50 is not set
+# CONFIG_TCG_TIS_I2C_ATMEL is not set
+CONFIG_TCG_TIS_I2C_INFINEON=y
+# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+CONFIG_TCG_ATMEL=m
+# CONFIG_TCG_INFINEON is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_VTPM_PROXY is not set
+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
+# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# CONFIG_RANDOM_TRUST_CPU is not set
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_GPMUX=m
+# CONFIG_I2C_MUX_LTC4306 is not set
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_DEMUX_PINCTRL=m
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# end of Multiplexer I2C Chip support
+
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+CONFIG_I2C_CCGX_UCSI=m
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_AMD_MP2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NVIDIA_GPU=m
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# ACPI drivers
+#
+CONFIG_I2C_SCMI=y
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CADENCE is not set
+# CONFIG_I2C_CBUS_GPIO is not set
+CONFIG_I2C_DESIGNWARE_CORE=y
+# CONFIG_I2C_DESIGNWARE_SLAVE is not set
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PCI=m
+# CONFIG_I2C_EMEV2 is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
+# CONFIG_I2C_HISI is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SIMTEC=m
+# CONFIG_I2C_THUNDERX is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+CONFIG_I2C_DIOLAN_U2C=m
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+CONFIG_I2C_TINY_USB=m
+CONFIG_I2C_VIPERBOARD=m
+
+#
+# Other I2C/SMBus bus drivers
+#
+CONFIG_I2C_CROS_EC_TUNNEL=y
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+CONFIG_I2C_STUB=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=m
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_CADENCE_XSPI is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_HISI_KUNPENG is not set
+# CONFIG_SPI_HISI_SFC_V3XX is not set
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_SPI_GPIO=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_PL022=y
+# CONFIG_SPI_PXA2XX is not set
+CONFIG_SPI_ROCKCHIP=y
+# CONFIG_SPI_ROCKCHIP_SFC is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+# CONFIG_SPI_MUX is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_HSI is not set
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_GPIO=m
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_DP83640_PHY=m
+# CONFIG_PTP_1588_CLOCK_INES is not set
+CONFIG_PTP_1588_CLOCK_KVM=y
+# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
+# CONFIG_PTP_1588_CLOCK_IDTCM is not set
+# CONFIG_PTP_1588_CLOCK_OCP is not set
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_PINMUX=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+CONFIG_PINCTRL_AMD=y
+CONFIG_PINCTRL_AXP209=y
+CONFIG_PINCTRL_MAX77620=y
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+CONFIG_PINCTRL_SINGLE=y
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_AMDPT is not set
+# CONFIG_GPIO_CADENCE is not set
+CONFIG_GPIO_DWAPB=y
+# CONFIG_GPIO_EXAR is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HISI is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_LOGICVC is not set
+# CONFIG_GPIO_MB86S7X is not set
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SAMA5D2_PIOBU is not set
+# CONFIG_GPIO_SIFIVE is not set
+CONFIG_GPIO_SYSCON=y
+CONFIG_GPIO_XGENE=y
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+# CONFIG_GPIO_PCA9570 is not set
+CONFIG_GPIO_PCF857X=m
+# CONFIG_GPIO_TPIC2810 is not set
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+CONFIG_GPIO_MAX77620=y
+# end of MFD GPIO expanders
+
+#
+# PCI GPIO expanders
+#
+# CONFIG_GPIO_PCI_IDIO_16 is not set
+# CONFIG_GPIO_PCIE_IDIO_24 is not set
+# CONFIG_GPIO_RDC321X is not set
+# end of PCI GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+CONFIG_GPIO_VIPERBOARD=m
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+CONFIG_W1=m
+CONFIG_W1_CON=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_MATROX is not set
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS1WM=m
+CONFIG_W1_MASTER_GPIO=m
+# CONFIG_W1_MASTER_SGI is not set
+# end of 1-wire Bus Masters
+
+#
+# 1-wire Slaves
+#
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_W1_SLAVE_SMEM=m
+# CONFIG_W1_SLAVE_DS2405 is not set
+CONFIG_W1_SLAVE_DS2408=m
+# CONFIG_W1_SLAVE_DS2408_READBACK is not set
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2423=m
+# CONFIG_W1_SLAVE_DS2805 is not set
+# CONFIG_W1_SLAVE_DS2430 is not set
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+# CONFIG_W1_SLAVE_DS2438 is not set
+# CONFIG_W1_SLAVE_DS250X is not set
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS28E04=m
+# CONFIG_W1_SLAVE_DS28E17 is not set
+# end of 1-wire Slaves
+
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_BRCMSTB is not set
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_REBOOT_MODE=y
+CONFIG_SYSCON_REBOOT_MODE=y
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_GENERIC_ADC_BATTERY is not set
+# CONFIG_IP5XXX_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+CONFIG_BATTERY_CW2015=m
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+CONFIG_BATTERY_SBS=m
+CONFIG_CHARGER_SBS=m
+CONFIG_MANAGER_SBS=m
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_CHARGER_AXP20X is not set
+CONFIG_BATTERY_AXP20X=m
+CONFIG_AXP20X_POWER=m
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BATTERY_MAX1721X is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+CONFIG_CHARGER_GPIO=m
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_BQ256XX is not set
+CONFIG_CHARGER_SMB347=m
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_RT9455 is not set
+CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_CROS_PCHG=y
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_BATTERY_UG3105 is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+# CONFIG_SENSORS_ADM1177 is not set
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADT7X10=m
+# CONFIG_SENSORS_ADT7310 is not set
+CONFIG_SENSORS_ADT7410=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+CONFIG_SENSORS_ASC7621=m
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+# CONFIG_SENSORS_ARM_SCMI is not set
+CONFIG_SENSORS_ARM_SCPI=y
+# CONFIG_SENSORS_ASPEED is not set
+CONFIG_SENSORS_ATXP1=m
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+CONFIG_SENSORS_DRIVETEMP=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_DS1621=m
+# CONFIG_SENSORS_I5K_AMB is not set
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+# CONFIG_SENSORS_FTSTEUTATES is not set
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_G762=m
+CONFIG_SENSORS_GPIO_FAN=m
+# CONFIG_SENSORS_HIH6130 is not set
+CONFIG_SENSORS_IBMAEM=m
+CONFIG_SENSORS_IBMPEX=m
+CONFIG_SENSORS_IIO_HWMON=m
+CONFIG_SENSORS_IT87=m
+# CONFIG_SENSORS_JC42 is not set
+CONFIG_SENSORS_POWR1220=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LTC2945=m
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4222=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4260=m
+CONFIG_SENSORS_LTC4261=m
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX197=m
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6642=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_MAX6697=m
+# CONFIG_SENSORS_MAX31790 is not set
+CONFIG_SENSORS_MCP3021=m
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_ADCXX is not set
+CONFIG_SENSORS_LM63=m
+# CONFIG_SENSORS_LM70 is not set
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LM95234=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_NCT6683=m
+CONFIG_SENSORS_NCT6775_CORE=m
+CONFIG_SENSORS_NCT6775=m
+# CONFIG_SENSORS_NCT6775_I2C is not set
+CONFIG_SENSORS_NCT7802=m
+CONFIG_SENSORS_NCT7904=m
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_PMBUS=m
+# CONFIG_SENSORS_ADM1266 is not set
+CONFIG_SENSORS_ADM1275=m
+# CONFIG_SENSORS_BEL_PFE is not set
+# CONFIG_SENSORS_BPA_RS600 is not set
+# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
+# CONFIG_SENSORS_FSP_3Y is not set
+# CONFIG_SENSORS_IBM_CFFPS is not set
+# CONFIG_SENSORS_DPS920AB is not set
+# CONFIG_SENSORS_INSPUR_IPSPS is not set
+# CONFIG_SENSORS_IR35221 is not set
+# CONFIG_SENSORS_IR36021 is not set
+# CONFIG_SENSORS_IR38064 is not set
+# CONFIG_SENSORS_IRPS5401 is not set
+# CONFIG_SENSORS_ISL68137 is not set
+CONFIG_SENSORS_LM25066=m
+# CONFIG_SENSORS_LM25066_REGULATOR is not set
+CONFIG_SENSORS_LTC2978=m
+# CONFIG_SENSORS_LTC2978_REGULATOR is not set
+# CONFIG_SENSORS_LTC3815 is not set
+# CONFIG_SENSORS_MAX15301 is not set
+CONFIG_SENSORS_MAX16064=m
+# CONFIG_SENSORS_MAX16601 is not set
+# CONFIG_SENSORS_MAX20730 is not set
+# CONFIG_SENSORS_MAX20751 is not set
+# CONFIG_SENSORS_MAX31785 is not set
+CONFIG_SENSORS_MAX34440=m
+CONFIG_SENSORS_MAX8688=m
+# CONFIG_SENSORS_MP2888 is not set
+# CONFIG_SENSORS_MP2975 is not set
+# CONFIG_SENSORS_MP5023 is not set
+# CONFIG_SENSORS_PIM4328 is not set
+# CONFIG_SENSORS_PLI1209BC is not set
+# CONFIG_SENSORS_PM6764TR is not set
+# CONFIG_SENSORS_PXE1610 is not set
+# CONFIG_SENSORS_Q54SJ108A2 is not set
+# CONFIG_SENSORS_STPDDC60 is not set
+CONFIG_SENSORS_TPS40422=m
+# CONFIG_SENSORS_TPS53679 is not set
+CONFIG_SENSORS_UCD9000=m
+CONFIG_SENSORS_UCD9200=m
+# CONFIG_SENSORS_XDPE152 is not set
+# CONFIG_SENSORS_XDPE122 is not set
+CONFIG_SENSORS_ZL6100=m
+CONFIG_SENSORS_PWM_FAN=m
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SHT3x=m
+# CONFIG_SENSORS_SHT4x is not set
+CONFIG_SENSORS_SHTC1=m
+CONFIG_SENSORS_SIS5595=m
+# CONFIG_SENSORS_SY7636A is not set
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_EMC1403=m
+# CONFIG_SENSORS_EMC2103 is not set
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SCH56XX_COMMON=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+CONFIG_SENSORS_ADC128D818=m
+CONFIG_SENSORS_ADS7828=m
+# CONFIG_SENSORS_ADS7871 is not set
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_INA209=m
+CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
+CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_TC74=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP103=m
+CONFIG_SENSORS_TMP108=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+# CONFIG_SENSORS_TMP464 is not set
+# CONFIG_SENSORS_TMP513 is not set
+CONFIG_SENSORS_VEXPRESS=m
+CONFIG_SENSORS_VIA686A=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_VT8231=m
+# CONFIG_SENSORS_W83773G is not set
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+# CONFIG_SENSORS_W83795_FANCTRL is not set
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83627EHF=m
+# CONFIG_SENSORS_XGENE is not set
+
+#
+# ACPI drivers
+#
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_NETLINK is not set
+# CONFIG_THERMAL_STATISTICS is not set
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+# CONFIG_THERMAL_MMIO is not set
+CONFIG_MAX77620_THERMAL=m
+CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_KHADAS_MCU_FAN_THERMAL=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+# CONFIG_WATCHDOG_SYSFS is not set
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_GPIO_WATCHDOG=m
+# CONFIG_WDAT_WDT is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+CONFIG_ARM_SP805_WATCHDOG=m
+CONFIG_ARM_SBSA_WATCHDOG=m
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=m
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_MAX77620_WATCHDOG=m
+# CONFIG_ARM_SMC_WATCHDOG is not set
+CONFIG_ALIM7101_WDT=m
+CONFIG_I6300ESB_WDT=m
+# CONFIG_MEN_A21_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_WDTPCI=m
+
+#
+# USB-based Watchdog Cards
+#
+CONFIG_USBPCWATCHDOG=m
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_BCMA=m
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+# CONFIG_BCMA_HOST_SOC is not set
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+# CONFIG_BCMA_DEBUG is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_CROS_EC_DEV=y
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+CONFIG_MFD_MAX77620=y
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77714 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+CONFIG_MFD_VIPERBOARD=m
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+CONFIG_MFD_RK808=y
+# CONFIG_MFD_RN5T618 is not set
+CONFIG_MFD_SEC_CORE=y
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SM501_GPIO=y
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+CONFIG_MFD_WL1273_CORE=m
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+CONFIG_MFD_VX855=m
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+CONFIG_MFD_KHADAS_MCU=m
+# CONFIG_MFD_QCOM_PM8008 is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+CONFIG_REGULATOR_AXP20X=y
+# CONFIG_REGULATOR_CROS_EC is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+CONFIG_REGULATOR_FAN53555=y
+# CONFIG_REGULATOR_FAN53880 is not set
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+CONFIG_REGULATOR_MAX77620=y
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_MT6315 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT5190A is not set
+# CONFIG_REGULATOR_RT5759 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+# CONFIG_REGULATOR_S5M8767 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY7636A is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_REGULATOR_VEXPRESS=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_RC_CORE=m
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_RC_DEVICES=y
+CONFIG_IR_ENE=m
+CONFIG_IR_FINTEK=m
+CONFIG_IR_GPIO_CIR=m
+CONFIG_IR_GPIO_TX=m
+CONFIG_IR_HIX5HD2=m
+CONFIG_IR_IGORPLUGUSB=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_IMON=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_ITE_CIR=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_NUVOTON=m
+CONFIG_IR_PWM_TX=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_SERIAL=m
+CONFIG_IR_SERIAL_TRANSMITTER=y
+CONFIG_IR_SPI=m
+CONFIG_IR_STREAMZAP=m
+# CONFIG_IR_TOY is not set
+CONFIG_IR_TTUSBIR=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_RC_XBOX_DVD is not set
+CONFIG_CEC_CORE=m
+CONFIG_CEC_NOTIFIER=y
+
+#
+# CEC support
+#
+CONFIG_MEDIA_CEC_RC=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+# CONFIG_CEC_CH7322 is not set
+# CONFIG_CEC_CROS_EC is not set
+# CONFIG_CEC_GPIO is not set
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_RAINSHADOW_CEC=m
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_SUPPORT_FILTER is not set
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+# end of Media device types
+
+#
+# Media core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=y
+# end of Media core support
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_TUNER=m
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+# CONFIG_V4L2_FLASH_LED_CLASS is not set
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_ASYNC=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_VMALLOC=m
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+# CONFIG_DVB_MMAP is not set
+CONFIG_DVB_NET=y
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_VIDEO_CPIA2=m
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_S2255=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_ZR364XX=m
+
+#
+# Analog TV USB devices
+#
+CONFIG_VIDEO_GO7007=m
+CONFIG_VIDEO_GO7007_USB=m
+CONFIG_VIDEO_GO7007_LOADER=m
+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_STK1160_COMMON=m
+CONFIG_VIDEO_STK1160=m
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_AS102=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB=m
+# CONFIG_DVB_USB_CXUSB_ANALOG is not set
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=m
+
+#
+# Software defined radio USB devices
+#
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_HACKRF=m
+# CONFIG_USB_MSI2500 is not set
+CONFIG_MEDIA_PCI_SUPPORT=y
+
+#
+# Media capture support
+#
+CONFIG_VIDEO_SOLO6X10=m
+# CONFIG_VIDEO_TW5864 is not set
+CONFIG_VIDEO_TW68=m
+# CONFIG_VIDEO_TW686X is not set
+
+#
+# Media capture/analog TV support
+#
+CONFIG_VIDEO_DT3155=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_MXB=m
+
+#
+# Media capture/analog/hybrid TV support
+#
+CONFIG_VIDEO_BT848=m
+CONFIG_DVB_BT8XX=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX18_ALSA=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_VIDEO_CX25821=m
+CONFIG_VIDEO_CX25821_ALSA=m
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134_GO7007=m
+CONFIG_VIDEO_SAA7164=m
+
+#
+# Media digital TV PCI Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
+CONFIG_DVB_DDBRIDGE=m
+# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
+CONFIG_DVB_DM1105=m
+CONFIG_MANTIS_CORE=m
+CONFIG_DVB_MANTIS=m
+CONFIG_DVB_HOPPER=m
+# CONFIG_DVB_NETUP_UNIDVB is not set
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+CONFIG_DVB_PT3=m
+CONFIG_DVB_SMIPCIE=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_AV=m
+CONFIG_RADIO_ADAPTERS=y
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SI4713=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_KEENE=m
+CONFIG_USB_MA901=m
+CONFIG_USB_MR800=m
+CONFIG_USB_RAREMONO=m
+CONFIG_RADIO_SI470X=m
+CONFIG_USB_SI470X=m
+CONFIG_I2C_SI470X=m
+CONFIG_USB_SI4713=m
+CONFIG_PLATFORM_SI4713=m
+CONFIG_I2C_SI4713=m
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+# CONFIG_SDR_PLATFORM_DRIVERS is not set
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+# CONFIG_VIDEO_MUX is not set
+
+#
+# Allegro DVT media platform drivers
+#
+
+#
+# Amlogic media platform drivers
+#
+
+#
+# Amphion drivers
+#
+
+#
+# Aspeed media platform drivers
+#
+# CONFIG_VIDEO_ASPEED is not set
+
+#
+# Atmel media platform drivers
+#
+
+#
+# Cadence media platform drivers
+#
+# CONFIG_VIDEO_CADENCE_CSI2RX is not set
+# CONFIG_VIDEO_CADENCE_CSI2TX is not set
+
+#
+# Chips&Media media platform drivers
+#
+
+#
+# Intel media platform drivers
+#
+
+#
+# Marvell media platform drivers
+#
+# CONFIG_VIDEO_CAFE_CCIC is not set
+
+#
+# Mediatek media platform drivers
+#
+
+#
+# NVidia media platform drivers
+#
+
+#
+# NXP media platform drivers
+#
+
+#
+# Qualcomm media platform drivers
+#
+
+#
+# Renesas media platform drivers
+#
+
+#
+# Rockchip media platform drivers
+#
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+CONFIG_VIDEO_ROCKCHIP_ISP1=m
+
+#
+# Samsung media platform drivers
+#
+
+#
+# STMicroelectronics media platform drivers
+#
+
+#
+# Sunxi media platform drivers
+#
+
+#
+# Texas Instruments drivers
+#
+
+#
+# VIA media platform drivers
+#
+
+#
+# Xilinx media platform drivers
+#
+# CONFIG_VIDEO_XILINX is not set
+
+#
+# MMC/SDIO DVB adapters
+#
+CONFIG_SMS_SDIO_DRV=m
+# CONFIG_V4L_TEST_DRIVERS is not set
+# CONFIG_DVB_TEST_DRIVERS is not set
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+# CONFIG_SMS_SIANO_DEBUGFS is not set
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+# end of Media drivers
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
+# CONFIG_VIDEO_HI847 is not set
+# CONFIG_VIDEO_IMX208 is not set
+# CONFIG_VIDEO_IMX214 is not set
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_IMX258 is not set
+# CONFIG_VIDEO_IMX274 is not set
+# CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX319 is not set
+# CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
+# CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
+# CONFIG_VIDEO_MT9M001 is not set
+# CONFIG_VIDEO_MT9M032 is not set
+# CONFIG_VIDEO_MT9M111 is not set
+# CONFIG_VIDEO_MT9P031 is not set
+# CONFIG_VIDEO_MT9T001 is not set
+# CONFIG_VIDEO_MT9T112 is not set
+CONFIG_VIDEO_MT9V011=m
+# CONFIG_VIDEO_MT9V032 is not set
+# CONFIG_VIDEO_MT9V111 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_OG01A1B is not set
+# CONFIG_VIDEO_OV02A10 is not set
+# CONFIG_VIDEO_OV08D10 is not set
+# CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
+CONFIG_VIDEO_OV2640=m
+# CONFIG_VIDEO_OV2659 is not set
+# CONFIG_VIDEO_OV2680 is not set
+# CONFIG_VIDEO_OV2685 is not set
+# CONFIG_VIDEO_OV2740 is not set
+CONFIG_VIDEO_OV5640=m
+# CONFIG_VIDEO_OV5645 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV5648 is not set
+# CONFIG_VIDEO_OV5670 is not set
+# CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
+# CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV6650 is not set
+# CONFIG_VIDEO_OV7251 is not set
+CONFIG_VIDEO_OV7640=m
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_OV772X is not set
+# CONFIG_VIDEO_OV7740 is not set
+# CONFIG_VIDEO_OV8856 is not set
+# CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9282 is not set
+# CONFIG_VIDEO_OV9640 is not set
+# CONFIG_VIDEO_OV9650 is not set
+CONFIG_VIDEO_OV9734=m
+# CONFIG_VIDEO_RDACM20 is not set
+# CONFIG_VIDEO_RDACM21 is not set
+# CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# CONFIG_VIDEO_S5K4ECGX is not set
+# CONFIG_VIDEO_S5K5BAF is not set
+# CONFIG_VIDEO_S5K6A3 is not set
+# CONFIG_VIDEO_S5K6AA is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_CCS is not set
+# CONFIG_VIDEO_ET8EK8 is not set
+# CONFIG_VIDEO_M5MOLS is not set
+# end of Camera sensor devices
+
+#
+# Lens drivers
+#
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# end of Lens drivers
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# end of Flash devices
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+# CONFIG_VIDEO_TDA1997X is not set
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+# CONFIG_VIDEO_TLV320AIC23B is not set
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+# end of Audio decoders, processors and mixers
+
+#
+# RDS decoders
+#
+CONFIG_VIDEO_SAA6588=m
+# end of RDS decoders
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_ADV748X is not set
+# CONFIG_VIDEO_ADV7604 is not set
+# CONFIG_VIDEO_ADV7842 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_ISL7998X is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_MAX9286 is not set
+# CONFIG_VIDEO_ML86V7667 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+CONFIG_VIDEO_SAA711X=m
+# CONFIG_VIDEO_TC358743 is not set
+# CONFIG_VIDEO_TVP514X is not set
+CONFIG_VIDEO_TVP5150=m
+# CONFIG_VIDEO_TVP7002 is not set
+CONFIG_VIDEO_TW2804=m
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+# CONFIG_VIDEO_TW9910 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_CX25840=m
+# end of Video decoders
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_AD9389B is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_AK881X is not set
+CONFIG_VIDEO_SAA7127=m
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_THS8200 is not set
+# end of Video encoders
+
+#
+# Video improvement chips
+#
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+# end of Video improvement chips
+
+#
+# Audio/Video compression chips
+#
+CONFIG_VIDEO_SAA6752HS=m
+# end of Audio/Video compression chips
+
+#
+# SDR tuner chips
+#
+# CONFIG_SDR_MAX2175 is not set
+# end of SDR tuner chips
+
+#
+# Miscellaneous helper chips
+#
+# CONFIG_VIDEO_I2C is not set
+CONFIG_VIDEO_M52790=m
+# CONFIG_VIDEO_ST_MIPID02 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# end of Miscellaneous helper chips
+
+#
+# Media SPI Adapters
+#
+# CONFIG_CXD2880_SPI_DRV is not set
+# CONFIG_VIDEO_GS1662 is not set
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=y
+
+#
+# Customize TV tuners
+#
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=y
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_XC5000=y
+# end of Customize TV tuners
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+# CONFIG_DVB_DIB9000 is not set
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+# CONFIG_DVB_S5H1432 is not set
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10353=m
+# CONFIG_DVB_CXD2880 is not set
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_VES1820=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_S921=m
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_MN88443X is not set
+CONFIG_DVB_TC90522=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9033=m
+# CONFIG_DVB_ASCOT2E is not set
+CONFIG_DVB_ATBM8830=m
+# CONFIG_DVB_HELENE is not set
+# CONFIG_DVB_HORUS3A is not set
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+# CONFIG_DVB_LGS8GL5 is not set
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+# CONFIG_DVB_LNBH29 is not set
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_DRX39XYJ=m
+
+#
+# Common Interface (EN50221) controller drivers
+#
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_SP2=m
+# end of Customise DVB Frontends
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_DRM=m
+CONFIG_DRM_MIPI_DSI=y
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=m
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_DP_AUX_BUS=m
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_TTM=m
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_GEM_CMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_SCHED=m
+
+#
+# I2C encoder or helper chips
+#
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+CONFIG_DRM_HDLCD=m
+# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
+CONFIG_DRM_MALI_DISPLAY=m
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_AMDGPU is not set
+# CONFIG_DRM_NOUVEAU is not set
+CONFIG_DRM_VGEM=m
+# CONFIG_DRM_VKMS is not set
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_ROCKCHIP_RGB=y
+# CONFIG_ROCKCHIP_RK3066_HDMI is not set
+# CONFIG_DRM_VMWGFX is not set
+CONFIG_DRM_UDL=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_MGAG200=m
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
+CONFIG_DRM_QXL=m
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
+# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
+# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
+# CONFIG_DRM_PANEL_DSI_CM is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_EDP=m
+# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
+# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
+# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
+# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
+# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
+# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
+# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_CROS_EC_ANX7688 is not set
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+# CONFIG_DRM_FSL_LDB is not set
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9211 is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+CONFIG_DRM_NXP_PTN3460=m
+CONFIG_DRM_PARADE_PS8622=m
+CONFIG_DRM_PARADE_PS8640=m
+CONFIG_DRM_SIL_SII8620=m
+CONFIG_DRM_SII902X=m
+# CONFIG_DRM_SII9234 is not set
+CONFIG_DRM_SIMPLE_BRIDGE=m
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+CONFIG_DRM_TOSHIBA_TC358767=m
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+CONFIG_DRM_TI_TFP410=m
+# CONFIG_DRM_TI_SN65DSI83 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+CONFIG_DRM_ANALOGIX_ANX7625=m
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+CONFIG_DRM_DW_HDMI=m
+# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_DW_MIPI_DSI=m
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_HISI_HIBMC is not set
+CONFIG_DRM_HISI_KIRIN=m
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_ARCPGU is not set
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_CIRRUS_QEMU=m
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_PANEL_MIPI_DBI is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+CONFIG_DRM_PL111=m
+CONFIG_DRM_LIMA=m
+CONFIG_DRM_PANFROST=m
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_SSD130X is not set
+CONFIG_DRM_LEGACY=y
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_SAVAGE is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_DDC=m
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+CONFIG_FB_EFI=y
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_NVIDIA=m
+CONFIG_FB_NVIDIA_I2C=y
+# CONFIG_FB_NVIDIA_DEBUG is not set
+CONFIG_FB_NVIDIA_BACKLIGHT=y
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SM501 is not set
+# CONFIG_FB_SMSCUFX is not set
+CONFIG_FB_UDL=m
+# CONFIG_FB_IBM_GXT4500 is not set
+CONFIG_FB_VIRTUAL=m
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SSD1307=m
+# CONFIG_FB_SM712 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI922X is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=m
+# CONFIG_LCD_AMS369FG06 is not set
+# CONFIG_LCD_LMS501KF03 is not set
+# CONFIG_LCD_HX8357 is not set
+# CONFIG_LCD_OTM3225A is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+CONFIG_BACKLIGHT_PWM=m
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_GPIO=m
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+CONFIG_BACKLIGHT_LED=m
+# end of Backlight & LCD device support
+
+CONFIG_VGASTATE=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_CTL_LED=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_SERIAL_U16550=m
+# CONFIG_SND_SERIAL_GENERIC is not set
+CONFIG_SND_MPU401=m
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_PCI=y
+CONFIG_SND_AD1889=m
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+CONFIG_SND_BT87X=m
+# CONFIG_SND_BT87X_OVERCLOCK is not set
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_GINA20=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MIA=m
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INDIGODJX=m
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+CONFIG_SND_FM801=m
+CONFIG_SND_FM801_TEA575X_BOOL=y
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+# CONFIG_SND_ICE1712 is not set
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INTEL8X0=m
+CONFIG_SND_INTEL8X0M=m
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LOLA=m
+CONFIG_SND_LX6464ES=m
+# CONFIG_SND_MAESTRO3 is not set
+CONFIG_SND_MIXART=m
+CONFIG_SND_NM256=m
+CONFIG_SND_PCXHR=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME96=m
+CONFIG_SND_RME9652=m
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+CONFIG_SND_VIA82XX=m
+CONFIG_SND_VIA82XX_MODEM=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VX222=m
+CONFIG_SND_YMFPCI=m
+
+#
+# HD-Audio
+#
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=0
+CONFIG_SND_HDA_PATCH_LOADER=y
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+# CONFIG_SND_HDA_CODEC_CS8409 is not set
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
+# end of HD-Audio
+
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_PREALLOC_SIZE=4096
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+# CONFIG_SND_BCD2000 is not set
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_ADI is not set
+CONFIG_SND_SOC_AMD_ACP=m
+# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set
+# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_AUDMIX is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_FSL_MICFIL is not set
+# CONFIG_SND_SOC_FSL_XCVR is not set
+# CONFIG_SND_SOC_FSL_RPMSG is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# end of SoC Audio for Freescale CPUs
+
+CONFIG_SND_I2S_HI6210_I2S=m
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_I2S=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
+CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+
+#
+# CODEC drivers
+#
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4613 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_AW8738 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+# CONFIG_SND_SOC_BT_SCO is not set
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS35L45_SPI is not set
+# CONFIG_SND_SOC_CS35L45_I2C is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+# CONFIG_SND_SOC_ES7134 is not set
+# CONFIG_SND_SOC_ES7241 is not set
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328_SPI=m
+# CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98357A=m
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+# CONFIG_SND_SOC_MAX98927 is not set
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98373_SDW is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX98396 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM5102A is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+CONFIG_SND_SOC_RK3328=m
+CONFIG_SND_SOC_RK817=m
+CONFIG_SND_SOC_RL6231=m
+# CONFIG_SND_SOC_RT1308_SDW is not set
+# CONFIG_SND_SOC_RT1316_SDW is not set
+CONFIG_SND_SOC_RT5514=m
+CONFIG_SND_SOC_RT5514_SPI=m
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+# CONFIG_SND_SOC_RT5659 is not set
+# CONFIG_SND_SOC_RT5682_SDW is not set
+# CONFIG_SND_SOC_RT700_SDW is not set
+# CONFIG_SND_SOC_RT711_SDW is not set
+# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT715_SDW is not set
+# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SDW_MOCKUP is not set
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+# CONFIG_SND_SOC_SIMPLE_MUX is not set
+CONFIG_SND_SOC_SPDIF=m
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+CONFIG_SND_SOC_STA350=m
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS5805M is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+CONFIG_SND_SOC_TS3A227E=m
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WCD938X_SDW is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731_I2C is not set
+# CONFIG_SND_SOC_WM8731_SPI is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+CONFIG_SND_SOC_WM8753=m
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+CONFIG_SND_SOC_WM8903=m
+# CONFIG_SND_SOC_WM8904 is not set
+# CONFIG_SND_SOC_WM8940 is not set
+# CONFIG_SND_SOC_WM8960 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+# CONFIG_SND_SOC_WSA881X is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+# CONFIG_SND_VIRTIO is not set
+CONFIG_AC97_BUS=m
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACCUTOUCH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+# CONFIG_HID_ASUS is not set
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BETOP_FF=m
+# CONFIG_HID_BIGBEN_FF is not set
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CORSAIR=m
+CONFIG_HID_COUGAR=m
+CONFIG_HID_MACALLY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CMEDIA=m
+CONFIG_HID_CP2112=m
+# CONFIG_HID_CREATIVE_SB0540 is not set
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+# CONFIG_HID_ELAN is not set
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_FT260 is not set
+CONFIG_HID_GEMBIRD=m
+CONFIG_HID_GFRM=m
+# CONFIG_HID_GLORIOUS is not set
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+# CONFIG_HID_GOOGLE_HAMMER is not set
+# CONFIG_HID_VIVALDI is not set
+CONFIG_HID_GT683R=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_VIEWSONIC=m
+# CONFIG_HID_XIAOMI is not set
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_ITE=m
+CONFIG_HID_JABRA=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LED=m
+CONFIG_HID_LENOVO=m
+# CONFIG_HID_LETSKETCH is not set
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MALTRON=m
+CONFIG_HID_MAYFLASH=m
+# CONFIG_HID_MEGAWORLD_FF is not set
+CONFIG_HID_REDRAGON=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=y
+# CONFIG_HID_NINTENDO is not set
+CONFIG_HID_NTI=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LCD=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PLANTRONICS=m
+# CONFIG_HID_RAZER is not set
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_RETRODE=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+# CONFIG_HID_SEMITEK is not set
+# CONFIG_HID_SIGMAMICRO is not set
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEAM=m
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_UDRAW_PS3=m
+CONFIG_HID_U2FZERO=m
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
+CONFIG_HID_ALPS=m
+# CONFIG_HID_MCP2221 is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+# end of USB HID support
+
+#
+# I2C HID support
+#
+CONFIG_I2C_HID_ACPI=y
+# CONFIG_I2C_HID_OF is not set
+CONFIG_I2C_HID_OF_GOODIX=m
+# end of I2C HID support
+
+CONFIG_I2C_HID_CORE=y
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_OTG_FSM is not set
+# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+CONFIG_USB_MAX3421_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_U132_HCD=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SL811_HCD_ISO=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_BCMA is not set
+# CONFIG_USB_HCD_SSB is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=y
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_STORAGE_ENE_UB6250=y
+CONFIG_USB_UAS=y
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VUDC=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+CONFIG_USB_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_GADGET is not set
+CONFIG_USB_MUSB_DUAL_ROLE=y
+
+#
+# Platform Glue Layer
+#
+
+#
+# MUSB DMA mode
+#
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_ULPI=y
+# CONFIG_USB_DWC3_HOST is not set
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+#
+# Platform Glue Driver Support
+#
+CONFIG_USB_DWC3_PCI=y
+CONFIG_USB_DWC3_HAPS=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC2=y
+# CONFIG_USB_DWC2_HOST is not set
+
+#
+# Gadget/Dual-role mode requires USB Gadget support to be enabled
+#
+# CONFIG_USB_DWC2_PERIPHERAL is not set
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2_PCI=y
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_PCI=y
+CONFIG_USB_CHIPIDEA_MSM=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_GENERIC=y
+CONFIG_USB_CHIPIDEA_TEGRA=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1761_UDC=y
+# CONFIG_USB_ISP1760_HOST_ROLE is not set
+# CONFIG_USB_ISP1760_GADGET_ROLE is not set
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_UPD78F0730=m
+# CONFIG_USB_SERIAL_XR is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_FTDI_ELAN=m
+CONFIG_USB_APPLEDISPLAY=m
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_EZUSB_FX2=m
+# CONFIG_USB_HUB_USB251XB is not set
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_USB_HSIC_USB4604=y
+# CONFIG_USB_LINK_LAYER_TEST is not set
+CONFIG_USB_CHAOSKEY=m
+CONFIG_USB_ATM=m
+# CONFIG_USB_SPEEDTOUCH is not set
+CONFIG_USB_CXACRU=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_XUSBATM=m
+
+#
+# USB Physical Layer drivers
+#
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_ISP1301=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# end of USB Physical Layer drivers
+
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_U_SERIAL_CONSOLE is not set
+
+#
+# USB Peripheral Controller
+#
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_SNP_UDC_PLAT is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_BDC_UDC is not set
+# CONFIG_USB_AMD5536UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_NET2280 is not set
+# CONFIG_USB_GOKU is not set
+# CONFIG_USB_EG20T is not set
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_DUMMY_HCD is not set
+# end of USB Peripheral Controller
+
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC1_LEGACY=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_F_UVC=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_TCM=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+# CONFIG_USB_CONFIGFS_F_LB_SS is not set
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+
+#
+# USB Gadget precomposed configurations
+#
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_AUDIO=m
+CONFIG_GADGET_UAC1=y
+# CONFIG_GADGET_UAC1_LEGACY is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_HID=m
+# CONFIG_USB_G_DBGP is not set
+CONFIG_USB_G_WEBCAM=m
+# CONFIG_USB_RAW_GADGET is not set
+# end of USB Gadget precomposed configurations
+
+CONFIG_TYPEC=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+# CONFIG_TYPEC_RT1711H is not set
+# CONFIG_TYPEC_TCPCI_MAXIM is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_UCSI is not set
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_WUSB3801=m
+
+#
+# USB Type-C Multiplexer/DeMultiplexer Switch support
+#
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# end of USB Type-C Multiplexer/DeMultiplexer Switch support
+
+#
+# USB Type-C Alternate Mode drivers
+#
+CONFIG_TYPEC_DP_ALTMODE=m
+# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
+# end of USB Type-C Alternate Mode drivers
+
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_ARMMMCI=y
+# CONFIG_MMC_STM32_SDMMC is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+# CONFIG_MMC_SDHCI_OF_ASPEED is not set
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+CONFIG_MMC_TIFM_SD=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_CB710=y
+CONFIG_MMC_VIA_SDMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+CONFIG_MMC_DW_EXYNOS=y
+# CONFIG_MMC_DW_HI3798CV200 is not set
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_PCI=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_USDHI6ROL0=y
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_HSQ is not set
+CONFIG_MMC_TOSHIBA_PCI=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_SDHCI_XENON=y
+# CONFIG_MMC_SDHCI_OMAP is not set
+# CONFIG_MMC_SDHCI_AM654 is not set
+CONFIG_SCSI_UFSHCD=y
+# CONFIG_SCSI_UFS_BSG is not set
+# CONFIG_SCSI_UFS_HPB is not set
+# CONFIG_SCSI_UFS_HWMON is not set
+CONFIG_SCSI_UFSHCD_PCI=m
+# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
+# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
+CONFIG_MEMSTICK=m
+# CONFIG_MEMSTICK_DEBUG is not set
+
+#
+# MemoryStick drivers
+#
+# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
+CONFIG_MSPRO_BLOCK=m
+# CONFIG_MS_BLOCK is not set
+
+#
+# MemoryStick Host Controller Drivers
+#
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_EL15203000 is not set
+CONFIG_LEDS_LM3530=m
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_LP3944=m
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8860 is not set
+CONFIG_LEDS_PCA955X=m
+# CONFIG_LEDS_PCA955X_GPIO is not set
+CONFIG_LEDS_PCA963X=m
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=m
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_LT3593=m
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_SYSCON=y
+# CONFIG_LEDS_MLXREG is not set
+CONFIG_LEDS_USER=m
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+
+#
+# Flash and Torch LED drivers
+#
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+CONFIG_LEDS_SGM3140=m
+
+#
+# RGB LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_AUDIO=m
+# CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
+CONFIG_ACCESSIBILITY=y
+CONFIG_A11Y_BRAILLE_CONSOLE=y
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# end of Speakup console speech
+
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_DEBUG is not set
+# CONFIG_EDAC_THUNDERX is not set
+CONFIG_EDAC_XGENE=m
+# CONFIG_EDAC_DMC520 is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+CONFIG_RTC_DRV_ABX80X=m
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1307_CENTURY is not set
+CONFIG_RTC_DRV_DS1374=m
+CONFIG_RTC_DRV_DS1374_WDT=y
+CONFIG_RTC_DRV_DS1672=m
+# CONFIG_RTC_DRV_HYM8563 is not set
+CONFIG_RTC_DRV_MAX6900=m
+# CONFIG_RTC_DRV_MAX77686 is not set
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_ISL12022=m
+# CONFIG_RTC_DRV_ISL12026 is not set
+CONFIG_RTC_DRV_X1205=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_M41T80=m
+CONFIG_RTC_DRV_M41T80_WDT=y
+CONFIG_RTC_DRV_BQ32K=m
+# CONFIG_RTC_DRV_S35390A is not set
+CONFIG_RTC_DRV_FM3130=m
+# CONFIG_RTC_DRV_RX8010 is not set
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_EM3027=m
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_S5M is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS3232=m
+CONFIG_RTC_DRV_DS3232_HWMON=y
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_RV3029C2=m
+CONFIG_RTC_DRV_RV3029_HWMON=y
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+CONFIG_RTC_DRV_DS1286=m
+CONFIG_RTC_DRV_DS1511=m
+CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+CONFIG_RTC_DRV_DS1685=y
+# CONFIG_RTC_DRV_DS1689 is not set
+# CONFIG_RTC_DRV_DS17285 is not set
+# CONFIG_RTC_DRV_DS17485 is not set
+# CONFIG_RTC_DRV_DS17885 is not set
+CONFIG_RTC_DRV_DS1742=m
+CONFIG_RTC_DRV_DS2404=m
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_STK17TA8=m
+# CONFIG_RTC_DRV_M48T86 is not set
+CONFIG_RTC_DRV_M48T35=m
+CONFIG_RTC_DRV_M48T59=m
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_BQ4802=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_V3020=m
+# CONFIG_RTC_DRV_ZYNQMP is not set
+CONFIG_RTC_DRV_CROS_EC=y
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_BCM_SBA_RAID is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_HISI_DMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+CONFIG_MV_XOR_V2=y
+CONFIG_PL330_DMA=y
+# CONFIG_PLX_DMA is not set
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_DW_DMAC_CORE=m
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_PCI=m
+# CONFIG_DW_EDMA is not set
+# CONFIG_DW_EDMA_PCIE is not set
+# CONFIG_SF_PDMA is not set
+
+#
+# DMA Clients
+#
+CONFIG_ASYNC_TX_DMA=y
+# CONFIG_DMATEST is not set
+CONFIG_DMA_ENGINE_RAID=y
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# end of DMABUF options
+
+CONFIG_AUXDISPLAY=y
+# CONFIG_HD44780 is not set
+# CONFIG_IMG_ASCII_LCD is not set
+# CONFIG_HT16K33 is not set
+# CONFIG_LCD2S is not set
+# CONFIG_CHARLCD_BL_OFF is not set
+# CONFIG_CHARLCD_BL_ON is not set
+CONFIG_CHARLCD_BL_FLASH=y
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+CONFIG_UIO_AEC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UIO_PCI_GENERIC=m
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_MF624 is not set
+CONFIG_VFIO=m
+CONFIG_VFIO_IOMMU_TYPE1=m
+CONFIG_VFIO_VIRQFD=m
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PLATFORM=m
+CONFIG_VFIO_AMBA=m
+CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
+CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
+# CONFIG_VFIO_MDEV is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+# CONFIG_VIRTIO_PMEM is not set
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_MMIO=m
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+# CONFIG_VDPA is not set
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_MENU=y
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_VSOCK=m
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_HYPERV is not set
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+CONFIG_PRISM2_USB=m
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8723BS=m
+CONFIG_R8712U=m
+CONFIG_R8188EU=m
+# CONFIG_RTS5208 is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+CONFIG_ADIS16203=m
+CONFIG_ADIS16240=m
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+CONFIG_AD7816=m
+# end of Analog to digital converters
+
+#
+# Analog digital bi-direction converters
+#
+CONFIG_ADT7316=m
+CONFIG_ADT7316_SPI=m
+CONFIG_ADT7316_I2C=m
+# end of Analog digital bi-direction converters
+
+#
+# Capacitance to digital converters
+#
+CONFIG_AD7746=m
+# end of Capacitance to digital converters
+
+#
+# Direct Digital Synthesis
+#
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+# end of Direct Digital Synthesis
+
+#
+# Network Analyzer, Impedance Converters
+#
+CONFIG_AD5933=m
+# end of Network Analyzer, Impedance Converters
+
+#
+# Active energy metering IC
+#
+CONFIG_ADE7854=m
+CONFIG_ADE7854_I2C=m
+CONFIG_ADE7854_SPI=m
+# end of Active energy metering IC
+
+#
+# Resolver to digital converters
+#
+CONFIG_AD2S1210=m
+# end of Resolver to digital converters
+# end of IIO staging drivers
+
+# CONFIG_FB_SM750 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+# CONFIG_VIDEO_ZORAN is not set
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_BUDGET_PATCH=m
+CONFIG_DVB_SP8870=m
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+CONFIG_FB_TFT=m
+CONFIG_FB_TFT_AGM1264K_FL=m
+CONFIG_FB_TFT_BD663474=m
+CONFIG_FB_TFT_HX8340BN=m
+CONFIG_FB_TFT_HX8347D=m
+CONFIG_FB_TFT_HX8353D=m
+CONFIG_FB_TFT_HX8357D=m
+CONFIG_FB_TFT_ILI9163=m
+CONFIG_FB_TFT_ILI9320=m
+CONFIG_FB_TFT_ILI9325=m
+CONFIG_FB_TFT_ILI9340=m
+CONFIG_FB_TFT_ILI9341=m
+CONFIG_FB_TFT_ILI9481=m
+CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT_PCD8544=m
+CONFIG_FB_TFT_RA8875=m
+CONFIG_FB_TFT_S6D02A1=m
+CONFIG_FB_TFT_S6D1121=m
+# CONFIG_FB_TFT_SEPS525 is not set
+CONFIG_FB_TFT_SH1106=m
+CONFIG_FB_TFT_SSD1289=m
+CONFIG_FB_TFT_SSD1305=m
+CONFIG_FB_TFT_SSD1306=m
+CONFIG_FB_TFT_SSD1331=m
+CONFIG_FB_TFT_SSD1351=m
+CONFIG_FB_TFT_ST7735R=m
+CONFIG_FB_TFT_ST7789V=m
+CONFIG_FB_TFT_TINYLCD=m
+CONFIG_FB_TFT_TLS8204=m
+CONFIG_FB_TFT_UC1611=m
+CONFIG_FB_TFT_UC1701=m
+CONFIG_FB_TFT_UPD161704=m
+# CONFIG_KS7010 is not set
+# CONFIG_PI433 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_QLGE is not set
+
+#
+# VME Device Drivers
+#
+# CONFIG_GOLDFISH is not set
+CONFIG_CHROME_PLATFORMS=y
+# CONFIG_CHROMEOS_ACPI is not set
+CONFIG_CHROMEOS_TBMC=m
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_RPMSG=m
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_PROTO=y
+CONFIG_CROS_KBD_LED_BACKLIGHT=y
+CONFIG_CROS_EC_CHARDEV=y
+CONFIG_CROS_EC_LIGHTBAR=m
+CONFIG_CROS_EC_VBC=m
+CONFIG_CROS_EC_DEBUGFS=m
+CONFIG_CROS_EC_SENSORHUB=y
+CONFIG_CROS_EC_SYSFS=m
+CONFIG_CROS_EC_TYPEC=y
+CONFIG_CROS_USBPD_LOGGER=m
+CONFIG_CROS_USBPD_NOTIFY=y
+# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+CONFIG_SURFACE_PLATFORMS=y
+# CONFIG_SURFACE_3_POWER_OPREGION is not set
+# CONFIG_SURFACE_GPE is not set
+# CONFIG_SURFACE_HOTPLUG is not set
+# CONFIG_SURFACE_PRO3_BUTTON is not set
+# CONFIG_SURFACE_AGGREGATOR is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX77686 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMMON_CLK_PWM=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+# CONFIG_XILINX_VCU is not set
+CONFIG_HWSPINLOCK=y
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_HISILICON_ERRATUM_161010101=y
+CONFIG_ARM64_ERRATUM_858921=y
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_PLATFORM_MHU=y
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_PCC=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_OF_IOMMU=y
+CONFIG_IOMMU_DMA=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+# CONFIG_VIRTIO_IOMMU is not set
+
+#
+# Remoteproc drivers
+#
+CONFIG_REMOTEPROC=y
+# CONFIG_REMOTEPROC_CDEV is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+# CONFIG_RPMSG_CTRL is not set
+# CONFIG_RPMSG_NS is not set
+CONFIG_RPMSG_QCOM_GLINK=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+CONFIG_SOUNDWIRE=y
+
+#
+# SoundWire Devices
+#
+# CONFIG_SOUNDWIRE_INTEL is not set
+# CONFIG_SOUNDWIRE_QCOM is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+CONFIG_SOC_BRCMSTB=y
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# end of Enable LiteX SoC Builder specific drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+CONFIG_EXTCON_ADC_JACK=m
+# CONFIG_EXTCON_FSA9480 is not set
+CONFIG_EXTCON_GPIO=y
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+# CONFIG_EXTCON_USBC_TUSB320 is not set
+CONFIG_MEMORY=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_OMAP_GPMC is not set
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_BUFFER_CB=y
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IIO_CONFIGFS=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+
+#
+# Accelerometers
+#
+CONFIG_ADIS16201=m
+CONFIG_ADIS16209=m
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
+CONFIG_ADXL345=m
+CONFIG_ADXL345_I2C=m
+CONFIG_ADXL345_SPI=m
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
+# CONFIG_ADXL367_SPI is not set
+# CONFIG_ADXL367_I2C is not set
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_BMA180=m
+CONFIG_BMA220=m
+# CONFIG_BMA400 is not set
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL_SPI=m
+# CONFIG_BMI088_ACCEL is not set
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DMARD06=m
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+# CONFIG_FXLS8962AF_I2C is not set
+# CONFIG_FXLS8962AF_SPI is not set
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_KXSD9=m
+CONFIG_KXSD9_SPI=m
+CONFIG_KXSD9_I2C=m
+CONFIG_KXCJK1013=m
+CONFIG_MC3230=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_SCA3000=m
+# CONFIG_SCA3300 is not set
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+# end of Accelerometers
+
+#
+# Analog to digital converters
+#
+CONFIG_AD_SIGMA_DELTA=m
+# CONFIG_AD7091R5 is not set
+CONFIG_AD7124=m
+CONFIG_AD7192=m
+CONFIG_AD7266=m
+CONFIG_AD7280=m
+CONFIG_AD7291=m
+# CONFIG_AD7292 is not set
+CONFIG_AD7298=m
+CONFIG_AD7476=m
+CONFIG_AD7606=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+CONFIG_AD7780=m
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+# CONFIG_ADI_AXI_ADC is not set
+CONFIG_AXP20X_ADC=m
+CONFIG_AXP288_ADC=m
+CONFIG_CC10001_ADC=m
+CONFIG_ENVELOPE_DETECTOR=m
+CONFIG_HI8435=m
+CONFIG_HX711=m
+CONFIG_INA2XX_ADC=m
+CONFIG_LTC2471=m
+CONFIG_LTC2485=m
+# CONFIG_LTC2496 is not set
+CONFIG_LTC2497=m
+CONFIG_MAX1027=m
+CONFIG_MAX11100=m
+CONFIG_MAX1118=m
+# CONFIG_MAX1241 is not set
+CONFIG_MAX1363=m
+CONFIG_MAX9611=m
+CONFIG_MCP320X=m
+CONFIG_MCP3422=m
+CONFIG_MCP3911=m
+CONFIG_NAU7802=m
+CONFIG_QCOM_VADC_COMMON=y
+CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_VADC=y
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_ROCKCHIP_SARADC=m
+CONFIG_SD_ADC_MODULATOR=m
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_ADS8688=m
+CONFIG_TI_ADS124S08=m
+# CONFIG_TI_ADS131E08 is not set
+CONFIG_TI_TLC4541=m
+# CONFIG_TI_TSC2046 is not set
+CONFIG_VF610_ADC=m
+CONFIG_VIPERBOARD_ADC=m
+# CONFIG_XILINX_XADC is not set
+# end of Analog to digital converters
+
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
+# Analog Front Ends
+#
+CONFIG_IIO_RESCALE=m
+# end of Analog Front Ends
+
+#
+# Amplifiers
+#
+CONFIG_AD8366=m
+# CONFIG_ADA4250 is not set
+# CONFIG_HMC425 is not set
+# end of Amplifiers
+
+#
+# Capacitance to digital converters
+#
+CONFIG_AD7150=m
+# end of Capacitance to digital converters
+
+#
+# Chemical Sensors
+#
+CONFIG_ATLAS_PH_SENSOR=m
+# CONFIG_ATLAS_EZO_SENSOR is not set
+CONFIG_BME680=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680_SPI=m
+CONFIG_CCS811=m
+CONFIG_IAQCORE=m
+CONFIG_PMS7003=m
+# CONFIG_SCD30_CORE is not set
+# CONFIG_SCD4X is not set
+CONFIG_SENSIRION_SGP30=m
+# CONFIG_SENSIRION_SGP40 is not set
+# CONFIG_SPS30_I2C is not set
+# CONFIG_SPS30_SERIAL is not set
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
+CONFIG_VZ89X=m
+# end of Chemical Sensors
+
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+# CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE is not set
+
+#
+# Hid Sensor IIO Common
+#
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+# end of Hid Sensor IIO Common
+
+CONFIG_IIO_MS_SENSORS_I2C=m
+
+#
+# IIO SCMI Sensors
+#
+# CONFIG_IIO_SCMI is not set
+# end of IIO SCMI Sensors
+
+#
+# SSP Sensor Common
+#
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# end of SSP Sensor Common
+
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD3552R is not set
+CONFIG_AD5064=m
+CONFIG_AD5360=m
+CONFIG_AD5380=m
+CONFIG_AD5421=m
+CONFIG_AD5446=m
+CONFIG_AD5449=m
+CONFIG_AD5592R_BASE=m
+CONFIG_AD5592R=m
+CONFIG_AD5593R=m
+CONFIG_AD5504=m
+CONFIG_AD5624R_SPI=m
+# CONFIG_LTC2688 is not set
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+CONFIG_AD5755=m
+CONFIG_AD5758=m
+CONFIG_AD5761=m
+CONFIG_AD5764=m
+# CONFIG_AD5766 is not set
+# CONFIG_AD5770R is not set
+CONFIG_AD5791=m
+# CONFIG_AD7293 is not set
+CONFIG_AD7303=m
+CONFIG_AD8801=m
+CONFIG_DPOT_DAC=m
+CONFIG_DS4424=m
+CONFIG_LTC1660=m
+CONFIG_LTC2632=m
+CONFIG_M62332=m
+CONFIG_MAX517=m
+CONFIG_MAX5821=m
+CONFIG_MCP4725=m
+CONFIG_MCP4922=m
+CONFIG_TI_DAC082S085=m
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+CONFIG_VF610_DAC=m
+# end of Digital to analog converters
+
+#
+# IIO dummy driver
+#
+# CONFIG_IIO_SIMPLE_DUMMY is not set
+# end of IIO dummy driver
+
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+CONFIG_AD9523=m
+# end of Clock Generator/Distribution
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+CONFIG_ADF4350=m
+# CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADMV1014 is not set
+# CONFIG_ADMV4420 is not set
+# CONFIG_ADRF6780 is not set
+# end of Phase-Locked Loop (PLL) frequency synthesizers
+# end of Frequency Synthesizers DDS/PLL
+
+#
+# Digital gyroscope sensors
+#
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16260=m
+# CONFIG_ADXRS290 is not set
+CONFIG_ADXRS450=m
+CONFIG_BMG160=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160_SPI=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_MPU3050=m
+CONFIG_MPU3050_I2C=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_ITG3200=m
+# end of Digital gyroscope sensors
+
+#
+# Health Sensors
+#
+
+#
+# Heart Rate Monitors
+#
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+# end of Heart Rate Monitors
+# end of Health Sensors
+
+#
+# Humidity sensors
+#
+CONFIG_AM2315=m
+CONFIG_DHT11=m
+CONFIG_HDC100X=m
+# CONFIG_HDC2010 is not set
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HTS221=m
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+# end of Humidity sensors
+
+#
+# Inertial measurement units
+#
+CONFIG_ADIS16400=m
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+CONFIG_ADIS16480=m
+CONFIG_BMI160=m
+CONFIG_BMI160_I2C=m
+CONFIG_BMI160_SPI=m
+# CONFIG_FXOS8700_I2C is not set
+# CONFIG_FXOS8700_SPI is not set
+CONFIG_KMX61=m
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+CONFIG_INV_MPU6050_IIO=m
+CONFIG_INV_MPU6050_I2C=m
+CONFIG_INV_MPU6050_SPI=m
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+# CONFIG_IIO_ST_LSM9DS0 is not set
+# end of Inertial measurement units
+
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+
+#
+# Light sensors
+#
+CONFIG_ACPI_ALS=m
+CONFIG_ADJD_S311=m
+# CONFIG_ADUX1020 is not set
+# CONFIG_AL3010 is not set
+CONFIG_AL3320A=m
+CONFIG_APDS9300=m
+CONFIG_APDS9960=m
+# CONFIG_AS73211 is not set
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM3605=m
+CONFIG_CM36651=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+# CONFIG_GP2AP002 is not set
+CONFIG_GP2AP020A00F=m
+CONFIG_SENSORS_ISL29018=m
+CONFIG_SENSORS_ISL29028=m
+CONFIG_ISL29125=m
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_JSA1212=m
+CONFIG_RPR0521=m
+CONFIG_LTR501=m
+CONFIG_LV0104CS=m
+CONFIG_MAX44000=m
+CONFIG_MAX44009=m
+# CONFIG_NOA1305 is not set
+CONFIG_OPT3001=m
+CONFIG_PA12203001=m
+CONFIG_SI1133=m
+CONFIG_SI1145=m
+CONFIG_STK3310=m
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_SENSORS_TSL2563=m
+CONFIG_TSL2583=m
+# CONFIG_TSL2591 is not set
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_US5182D=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
+# CONFIG_VEML6030 is not set
+CONFIG_VEML6070=m
+CONFIG_VL6180=m
+CONFIG_ZOPT2201=m
+# end of Light sensors
+
+#
+# Magnetometer sensors
+#
+CONFIG_AK8974=m
+CONFIG_AK8975=m
+CONFIG_AK09911=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_MAG3110=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_MMC35240=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_SENSORS_HMC5843=m
+CONFIG_SENSORS_HMC5843_I2C=m
+CONFIG_SENSORS_HMC5843_SPI=m
+CONFIG_SENSORS_RM3100=m
+CONFIG_SENSORS_RM3100_I2C=m
+CONFIG_SENSORS_RM3100_SPI=m
+# CONFIG_YAMAHA_YAS530 is not set
+# end of Magnetometer sensors
+
+#
+# Multiplexers
+#
+CONFIG_IIO_MUX=y
+# end of Multiplexers
+
+#
+# Inclinometer sensors
+#
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+# end of Inclinometer sensors
+
+#
+# Triggers - standalone
+#
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+# end of Triggers - standalone
+
+#
+# Linear and angular position sensors
+#
+# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set
+# end of Linear and angular position sensors
+
+#
+# Digital potentiometers
+#
+# CONFIG_AD5110 is not set
+CONFIG_AD5272=m
+CONFIG_DS1803=m
+# CONFIG_MAX5432 is not set
+CONFIG_MAX5481=m
+CONFIG_MAX5487=m
+CONFIG_MCP4018=m
+CONFIG_MCP4131=m
+CONFIG_MCP4531=m
+CONFIG_MCP41010=m
+CONFIG_TPL0102=m
+# end of Digital potentiometers
+
+#
+# Digital potentiostats
+#
+CONFIG_LMP91000=m
+# end of Digital potentiostats
+
+#
+# Pressure sensors
+#
+CONFIG_ABP060MG=m
+CONFIG_BMP280=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280_SPI=m
+CONFIG_IIO_CROS_EC_BARO=m
+# CONFIG_DLHL60D is not set
+# CONFIG_DPS310 is not set
+CONFIG_HID_SENSOR_PRESS=m
+CONFIG_HP03=m
+# CONFIG_ICP10100 is not set
+CONFIG_MPL115=m
+CONFIG_MPL115_I2C=m
+CONFIG_MPL115_SPI=m
+CONFIG_MPL3115=m
+CONFIG_MS5611=m
+CONFIG_MS5611_I2C=m
+CONFIG_MS5611_SPI=m
+CONFIG_MS5637=m
+CONFIG_IIO_ST_PRESS=m
+CONFIG_IIO_ST_PRESS_I2C=m
+CONFIG_IIO_ST_PRESS_SPI=m
+CONFIG_T5403=m
+CONFIG_HP206C=m
+CONFIG_ZPA2326=m
+CONFIG_ZPA2326_I2C=m
+CONFIG_ZPA2326_SPI=m
+# end of Pressure sensors
+
+#
+# Lightning sensors
+#
+CONFIG_AS3935=m
+# end of Lightning sensors
+
+#
+# Proximity and distance sensors
+#
+# CONFIG_CROS_EC_MKBP_PROXIMITY is not set
+CONFIG_ISL29501=m
+CONFIG_LIDAR_LITE_V2=m
+CONFIG_MB1232=m
+# CONFIG_PING is not set
+CONFIG_RFD77402=m
+CONFIG_SRF04=m
+# CONFIG_SX9310 is not set
+# CONFIG_SX9324 is not set
+# CONFIG_SX9360 is not set
+CONFIG_SX9500=m
+CONFIG_SRF08=m
+# CONFIG_VCNL3020 is not set
+CONFIG_VL53L0X_I2C=m
+# end of Proximity and distance sensors
+
+#
+# Resolver to digital converters
+#
+CONFIG_AD2S90=m
+CONFIG_AD2S1200=m
+# end of Resolver to digital converters
+
+#
+# Temperature sensors
+#
+# CONFIG_LTC2983 is not set
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+CONFIG_TMP006=m
+CONFIG_TMP007=m
+# CONFIG_TMP117 is not set
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+CONFIG_MAX31856=m
+# CONFIG_MAX31865 is not set
+# end of Temperature sensors
+
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+CONFIG_PWM_CROS_EC=m
+# CONFIG_PWM_DWC is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+# CONFIG_PWM_XILINX is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+# CONFIG_AL_FIC is not set
+CONFIG_PARTITION_PERCPU=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+# CONFIG_RESET_TI_SYSCON is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_PHY_XGENE=y
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+
+#
+# PHY drivers for Broadcom platforms
+#
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_QCOM_USB_HSIC=y
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+# CONFIG_PHY_SAMSUNG_USB2 is not set
+# CONFIG_PHY_TUSB1210 is not set
+# end of PHY Subsystem
+
+CONFIG_POWERCAP=y
+# CONFIG_IDLE_INJECT is not set
+# CONFIG_DTPM is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+CONFIG_ARM_CCI_PMU=y
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CCI5xx_PMU=y
+CONFIG_ARM_CCN=y
+# CONFIG_ARM_CMN is not set
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PMU_ACPI=y
+# CONFIG_ARM_SMMU_V3_PMU is not set
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_SPE_PMU is not set
+CONFIG_ARM_DMC620_PMU=y
+CONFIG_HISI_PMU=y
+# CONFIG_HISI_PCIE_PMU is not set
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_USB4 is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
+# end of Android
+
+CONFIG_LIBNVDIMM=y
+CONFIG_BLK_DEV_PMEM=m
+CONFIG_ND_CLAIM=y
+CONFIG_ND_BTT=m
+CONFIG_BTT=y
+CONFIG_OF_PMEM=y
+CONFIG_NVDIMM_KEYS=y
+CONFIG_DAX=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_ROCKCHIP_EFUSE=y
+# CONFIG_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_RMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+CONFIG_MULTIPLEXER=y
+
+#
+# Multiplexer drivers
+#
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_ADGS1408 is not set
+CONFIG_MUX_GPIO=y
+# CONFIG_MUX_MMIO is not set
+# end of Multiplexer drivers
+
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+CONFIG_INTERCONNECT=y
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# CONFIG_PECI is not set
+# CONFIG_HTE is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_VALIDATE_FS_PARSER=y
+CONFIG_FS_IOMAP=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+CONFIG_XFS_SUPPORT_V4=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_ONLINE_SCRUB is not set
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
+# CONFIG_OCFS2_DEBUG_MASKLOG is not set
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+CONFIG_NILFS2_FS=m
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+# CONFIG_F2FS_FS_COMPRESSION is not set
+CONFIG_F2FS_IOSTAT=y
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+# CONFIG_ZONEFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+# CONFIG_VIRTIO_FS is not set
+CONFIG_OVERLAY_FS=m
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_INDEX is not set
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+# CONFIG_OVERLAY_FS_METACOPY is not set
+
+#
+# Caches
+#
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NETFS_STATS=y
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+# CONFIG_FSCACHE_DEBUG is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_ERROR_INJECTION is not set
+# CONFIG_CACHEFILES_ONDEMAND is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+CONFIG_EXFAT_FS=m
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+# CONFIG_NTFS3_FS is not set
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_INODE64 is not set
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+# CONFIG_ECRYPT_FS_MESSAGING is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+# CONFIG_BEFS_DEBUG is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=m
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_SECURITY=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+CONFIG_CRAMFS=m
+CONFIG_CRAMFS_BLOCKDEV=y
+# CONFIG_CRAMFS_MTD is not set
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
+CONFIG_SQUASHFS_DECOMP_MULTI=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_ZSTD is not set
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE_DEFLATE_COMPRESS=y
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
+# CONFIG_PSTORE_842_COMPRESS is not set
+# CONFIG_PSTORE_ZSTD_COMPRESS is not set
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
+CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
+# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_PMSG is not set
+CONFIG_PSTORE_RAM=m
+# CONFIG_PSTORE_BLK is not set
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V2 is not set
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=y
+CONFIG_PNFS_FLEXFILE_LAYOUT=y
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_NFS_V4_SECURITY_LABEL=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DEBUG=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+CONFIG_NFSD_V4_2_INTER_SSC=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_SWAP=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_CEPH_FS=m
+CONFIG_CEPH_FSCACHE=y
+CONFIG_CEPH_FS_POSIX_ACL=y
+# CONFIG_CEPH_FS_SECURITY_LABEL is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DEBUG=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
+CONFIG_CIFS_DFS_UPCALL=y
+# CONFIG_CIFS_SWN_UPCALL is not set
+CONFIG_CIFS_FSCACHE=y
+# CONFIG_SMB_SERVER is not set
+CONFIG_SMBFS_COMMON=m
+CONFIG_CODA_FS=m
+# CONFIG_AFS_FS is not set
+CONFIG_9P_FS=m
+CONFIG_9P_FSCACHE=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+CONFIG_DLM_DEBUG=y
+# CONFIG_UNICODE is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_TRUSTED_KEYS=m
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_ENCRYPTED_KEYS=y
+# CONFIG_USER_DECRYPTED_DATA is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+CONFIG_SECURITY_PATH=y
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+# CONFIG_SECURITY_SELINUX is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_SECURITY_APPARMOR=y
+# CONFIG_SECURITY_APPARMOR_HASH is not set
+# CONFIG_SECURITY_APPARMOR_DEBUG is not set
+# CONFIG_SECURITY_LOADPIN is not set
+CONFIG_SECURITY_YAMA=y
+# CONFIG_SECURITY_SAFESETID is not set
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
+# CONFIG_SECURITY_LANDLOCK is not set
+# CONFIG_INTEGRITY is not set
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_STACK_ALL_PATTERN is not set
+# CONFIG_INIT_STACK_ALL_ZERO is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# end of Memory initialization
+
+CONFIG_RANDSTRUCT_NONE=y
+# CONFIG_RANDSTRUCT_FULL is not set
+# CONFIG_RANDSTRUCT_PERFORMANCE is not set
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=m
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_ENGINE=y
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=m
+CONFIG_CRYPTO_DH=m
+# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_AEGIS128=m
+# CONFIG_CRYPTO_AEGIS128_SIMD is not set
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_ECHAINIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_NHPOLY1305=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_ESSIV=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_BLAKE2B=m
+# CONFIG_CRYPTO_BLAKE2S is not set
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_POLY1305=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+# CONFIG_CRYPTO_SM3_GENERIC is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SM4=y
+# CONFIG_CRYPTO_SM4_GENERIC is not set
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_ZSTD=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+# CONFIG_CRYPTO_STATS is not set
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+CONFIG_CRYPTO_DEV_CCP=y
+CONFIG_CRYPTO_DEV_CCP_DD=m
+CONFIG_CRYPTO_DEV_SP_CCP=y
+CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
+# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+CONFIG_CRYPTO_DEV_ROCKCHIP=m
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_CCREE=m
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
+# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
+# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
+# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_CORDIC=m
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+# CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC64=y
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_CRC8=y
+CONFIG_XXHASH=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_COMPAT_GENERIC=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_842_COMPRESS=m
+CONFIG_842_DECOMPRESS=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_COMPRESS=m
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_MICROLZMA is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_BTREE=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_RESTRICTED_POOL is not set
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_CMA=y
+# CONFIG_DMA_PERNUMA_CMA is not set
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+CONFIG_LRU_CACHE=m
+CONFIG_CLZ_TAB=y
+CONFIG_IRQ_POLL=y
+CONFIG_MPILIB=y
+CONFIG_DIMLIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_UCS2_STRING=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_MEMREGION=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACK_HASH_ORDER=20
+CONFIG_SBITMAP=y
+# end of Library routines
+
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_ASN1_ENCODER=m
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DYNAMIC_DEBUG_CORE=y
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO_NONE=y
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_DEBUG_INFO_DWARF5 is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_KGDB=y
+CONFIG_KGDB_HONOUR_BLOCKLIST=y
+CONFIG_KGDB_SERIAL_CONSOLE=y
+CONFIG_KGDB_TESTS=y
+# CONFIG_KGDB_TESTS_ON_BOOT is not set
+# CONFIG_KGDB_KDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# CONFIG_DEBUG_NET is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_VM_VMACACHE is not set
+# CONFIG_DEBUG_VM_RB is not set
+# CONFIG_DEBUG_VM_PGFLAGS is not set
+CONFIG_DEBUG_VM_PGTABLE=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHEDSTATS=y
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_DEBUG_PREEMPT is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+CONFIG_DEBUG_LIST=y
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+CONFIG_TORTURE_TEST=m
+# CONFIG_RCU_SCALE_TEST is not set
+CONFIG_RCU_TORTURE_TEST=m
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+
+#
+# arm64 Debugging
+#
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_CORESIGHT is not set
+# end of arm64 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+CONFIG_FUNCTION_ERROR_INJECTION=y
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_KCOV is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_ARCH_USE_MEMTEST=y
+# CONFIG_MEMTEST is not set
+# end of Kernel Testing and Coverage
+# end of Kernel hacking
diff --git a/nongnu/packages/bootloaders.scm b/nongnu/packages/bootloaders.scm
new file mode 100644
index 0000000..8c20c4f
--- /dev/null
+++ b/nongnu/packages/bootloaders.scm
@@ -0,0 +1,261 @@
+;;; Copyright © 2022 Petr Hodina <phodina@protonmail.com>
+;;;
+;;; This program is free software: you can redistribute it and/or modify
+;;; it under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation, either version 3 of the License, or
+;;; (at your option) any later version.
+;;;
+;;; This program is distributed in the hope that it will be useful,
+;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+(define-module (nongnu packages bootloaders)
+  #:use-module (guix utils)
+  #:use-module (guix packages)
+  #:use-module (gnu bootloader)
+  #:use-module (gnu bootloader extlinux)
+  #:use-module (gnu packages)
+  #:use-module (gnu packages base)
+  #:use-module (gnu packages bash)
+  #:use-module (gnu packages bootloaders)
+  #:use-module (gnu packages compression)
+  #:use-module (gnu packages python)
+  #:use-module (gnu packages python-xyz)
+  #:use-module (gnu packages tls)
+  #:use-module (guix download)
+  #:use-module (guix git-download)
+  #:use-module (ice-9 ftw)
+  #:use-module (guix gexp)
+  #:use-module (nonguix build-system binary)
+  #:use-module ((nonguix licenses)
+                #:prefix license:)
+  #:export (u-boot-quartz64a-rk3566-bootloader
+            u-boot-pinephone-pro-rk3399-bootloader
+            u-boot-pinenote-rk3566-bootloader))
+
+(define %u-boot-quartz64-nvme-configs
+'("CONFIG_CMD_NVME=y"
+  "CONFIG_CMD_PCI=y"
+  "CONFIG_NVME=y"
+  "CONFIG_NVME_PCI=y"
+  "CONFIG_PCI=y"
+  "CONFIG_PCI_PNP=y"
+  "CONFIG_LOG_MAX_LEVEL=7"
+  "CONFIG_LOG=y"
+  "CONFIG_LOG_CONSOLE=y"
+;  "CONFIG_PCI_ENHANCED_ALLOCATION=y"
+  "CONFIG_PCIE_DW_COMMON=y"
+  "CONFIG_PCIE_DW_ROCKCHIP=y"
+  "CONFIG_PHY=y"
+  "CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y"))
+
+(define-public u-boot-pinephone-pro-rk3399
+  (make-u-boot-package "pinephone-pro-rk3399" "aarch64-linux-gnu"))
+
+(define (u-boot-rk3566 board configs)
+  (let ((commit "58040d305147b8608f5766a49d63e863ba163937")
+        (revision "1")
+        (base (make-u-boot-package board "aarch64-linux-gnu"
+#:configs configs)))
+    (package
+      (inherit base)
+      (version "2022.07")
+      (source (origin
+                (method git-fetch)
+                (uri (git-reference
+				;; Using rebased version which is compatible with Guix disable
+				;; OpenSSL patch
+                      (url "https://gitlab.com/phodina/u-boot-quartz64")
+                      (commit commit)))
+    (patches
+  (search-patches "u-boot-allow-disabling-openssl.patch"))
+                (sha256
+                 (base32
+                  "0w2yzvfvvydv26dm043jw24r7qkzc3j8jhcrc487pdm79icgfib8"))))
+      (arguments
+	   (substitute-keyword-arguments (package-arguments base)
+       ((#:phases phases)
+	   #~(modify-phases #$phases
+;	                      (add-after 'configure 'fix-config
+;						    (lambda* _
+;							 (substitute* ".config"
+;							  (("CONFIG_ARM=y")
+;							  "CONFIG_ARM=y\nCONFIG_LOG_MAX_LEVEL=7\nCONFIG_LOG=y\nCONFIG_LOG_CONSOLE=y"))))
+                          (add-after 'unpack 'download-rockchip-firmware
+                            (lambda* _
+                              (let* ((ram-init-dl #$(origin
+                                                  (method url-fetch)
+                                                  (uri
+                                                   "https://github.com/JeffyCN/rockchip_mirrors/raw/47404a141a1acb7555906b5e3b097b5f1045cc21/bin/rk35/rk3568_ddr_1560MHz_v1.11.bin")
+												  (file-name "ram_init.bin")
+                                                  (sha256 (base32
+                                                           "02rj8spdbq250wcrkkscmjz4jmwba8yfmv90kkbd5wspmk9bq0cj"))))
+                                (bl31-dl #$(origin
+                                                  (method url-fetch)
+                                                  (uri
+                                                   "https://github.com/JeffyCN/rockchip_mirrors/raw/6186debcac95553f6b311cee10669e12c9c9963d/bin/rk35/rk3568_bl31_v1.28.elf")
+												  (file-name "rk3568_bl31_v1.28.elf")
+                                                  (sha256 (base32
+                                                           "0ji53ggmmf9qwrvs06ashydvaw8d9w4byzsvypqy4imndxb1kgv7"))))
+                                              (bl31 
+                                                             "rk3568_bl31_v1.28.elf")
+                                              (ram-init 
+                                                             "ram_init.bin"))
+							  (setenv "BL31" "rk3568_bl31_v1.28.elf")
+							  (for-each make-file-writable (find-files "."))
+								(copy-file ram-init-dl ram-init)
+								(copy-file bl31-dl bl31)))))))))))
+
+(define-public u-boot-rk3566-quartz64-downstream
+  (let ((commit "7df3eae9f756665e01016a182d33ddf9dd244b1d")
+        (revision "1")
+        (base (make-u-boot-package "rk3566-quartz64" "aarch64-linux-gnu")))
+    (package
+      (inherit base)
+      (version "2017")
+      (source (origin
+                (method url-fetch)
+                (uri (string-append
+				"https://github.com/JoshuaMulliken/u-boot-rockchip/archive/"
+				commit ".tar.gz"))
+;    (patches
+;     (parameterize
+;         ((%patch-path
+;           (map (lambda (directory)
+;                  (string-append directory "/nongnu/packages/patches"))
+;                %load-path)))
+;				(search-patches ;"u-boot-dont-block-reads-above-32mb.patch"
+;				;"u-boot-pyelftools.patch"
+;				"u-boot-pyelftools.patch")))
+                (sha256
+                 (base32
+                  "0dsi48ay06ciqcvlrbjwm90wvvs3wf65nbgjsc46wkkx9c6r1rj2"))))
+      (arguments
+	   (substitute-keyword-arguments (package-arguments base)
+       ((#:phases phases)
+	   #~(modify-phases #$phases
+                          (add-after 'unpack 'download-rockchip-firmware
+                            (lambda* _
+                              (let* ((rkbin-dl #$(origin
+                                                  (method url-fetch)
+                                                  (uri
+                                                   "https://github.com/JeffyCN/rockchip_mirrors/archive/refs/heads/rkbin.zip")
+												  (file-name "rkbin.zip")
+                                                  (sha256 (base32
+                                                           "0wpli41046kppm873n5h410ljrvzjf219gzb7n0jc3qpghyl9cvw")))))
+							  (invoke "unzip" "-q" rkbin-dl)
+							  (rename-file "rockchip_mirrors-rkbin" "../rkbin")
+;							  (patch-shebang "make.sh")
+							  ;(substitute* "scripts/fit.sh"
+							  ;(("./make.sh loader") "bash -x ./make.sh loader"))
+							  ;(substitute* "scripts/loader.sh"
+							  ;(("set -e") "set -e\nset -x"))
+;							  (("boot_merger") "boot_merger --verbose"))
+							  (substitute* "Makefile"
+							  (("HOSTCC       = cc") (string-append "HOSTCC = "
+							  #$(cc-for-target))))
+							  ;(substitute* "make.sh"
+;(("python") "python3")
+;(("..SCRIPT_LOADER. --ini ..INI_LOADER.") "bash -x ${SCRIPT_LOADER} --ini
+;${INI_LOADER}")
+;(("..SCRIPT_FIT. ..ARG_LIST_FIT.") "bash -x ${SCRIPT_FIT} ${ARG_LIST_FIT}"))
+							  ;(("^make.*") "make HOSTCC=gcc CROSS_COMPILE=aarch64-linux-gnu- all\n"))
+								)))
+						  (delete 'disable-tools-libcrypto)
+						  (delete 'configure)
+           (replace 'build
+             (lambda* (#:key outputs inputs make-flags #:allow-other-keys)
+			; (setenv "PATH" (string-append (dirname (which "sed")) ":" (dirname
+			; (which "grep")) ":" (dirname (which "awk")) ":"
+			; ;#$(this-package-input "coreutils") "/bin" ":"
+			; #$coreutils "/bin" ":"
+			; (getenv "PATH")))
+;	         (setenv "cc=" #$(cc-for-target))
+;			 (setenv "CROSS_COMPILE" "aarch64-linux-gnu-")
+						  (invoke "make" "clean")
+						  (invoke "make" "mrproper")
+						  (invoke "make" "V=1" ;(string-append "CC=" "gcc");#$(cc-for-target))
+						  "rk3566-eink_defconfig")
+						  (invoke "./make.sh")
+						  (invoke "./make.sh" "trust")))
+			  ;(invoke "make" "HOSTCC=gcc" "CROSS_COMPILE=aarch64-linux-gnu-" "rk3566-quartz64_defconfig")))
+           (add-after 'build 'build-binaries
+             (lambda* (#:key outputs make-flags #:allow-other-keys)
+					 ;; Failing at
+;; https://gitlab.com/pgwipeout/u-boot-rockchip/-/blob/quartz64/make.sh#L774
+                     (invoke "bash" "-x" "./make.sh")
+					 (invoke "./tools/resource_tool" "--pack" "arch/arm/dts/rk3566-quartz64.dtb")
+		   ))))))
+	  (native-inputs `(("which" ,which) ("coreutils" ,coreutils) ("dtc" ,dtc)
+	  ("python-pyelftools" ,python-pyelftools) ("bash" ,bash-minimal) ("unzip" ,unzip) ,@(package-native-inputs base))))))
+
+(define-public u-boot-rk3566-evb
+        (u-boot-rk3566 "evb-rk3566" '()))
+
+(define-public u-boot-rk3566-pinenote
+        (u-boot-rk3566 "pinenote-rk3566" '()))
+
+(define-public u-boot-rk3566-quartz64a
+  (u-boot-rk3566 "quartz64-a-rk3566" %u-boot-quartz64-nvme-configs))
+
+(define-public u-boot-rk3566-quartz64b
+  (u-boot-rk3566 "quartz64-b-rk3566" '()))
+
+(define-public u-boot-rk3566-soquartz
+        (u-boot-rk3566 "soquartz-rk3566" '()))
+
+(define install-u-boot
+  #~(lambda (bootloader root-index image)
+      (if bootloader
+        (error "Failed to install U-Boot"))))
+
+(define install-rk3566-u-boot
+  #~(lambda (bootloader root-index image)
+      (let ((idb (string-append bootloader "/libexec/idbloader.img"))
+            (u-boot (string-append bootloader "/libexec/u-boot.itb")))
+        (write-file-on-device idb (stat:size (stat idb))
+                              image (* 64 512))
+        (write-file-on-device u-boot (stat:size (stat u-boot))
+                              image (* 16384 512)))))
+
+(define install-pinephone-pro-rk3399-u-boot
+  #~(lambda (bootloader root-index image)
+      (let ((idb (string-append bootloader "/libexec/idbloader.img"))
+            (u-boot (string-append bootloader "/libexec/u-boot.itb")))
+        (write-file-on-device idb (stat:size (stat idb))
+                              image (* 64 512))
+        (write-file-on-device u-boot (stat:size (stat u-boot))
+                              image (* 16384 512)))))
+
+(define u-boot-bootloader
+  (bootloader
+   (inherit extlinux-bootloader)
+   (name 'u-boot)
+   (package #f)
+   (installer #f)
+   (disk-image-installer install-u-boot)))
+
+(define u-boot-pinephone-pro-rk3399-bootloader
+  ;; SD and eMMC use the same format
+  (bootloader
+   (inherit u-boot-bootloader)
+   (package u-boot-pinephone-pro-rk3399)
+   (disk-image-installer install-pinephone-pro-rk3399-u-boot)))
+
+(define u-boot-quartz64a-rk3566-bootloader
+  ;; SD and eMMC use the same format
+  (bootloader
+   (inherit u-boot-bootloader)
+   (package u-boot-rk3566-quartz64a)
+   (disk-image-installer install-rk3566-u-boot)))
+
+(define u-boot-pinenote-rk3566-bootloader
+  ;; SD and eMMC use the same format
+  (bootloader
+   (inherit u-boot-bootloader)
+   (package u-boot-rk3566-pinenote)
+   (disk-image-installer install-rk3566-u-boot)))
diff --git a/nongnu/packages/firmware.scm b/nongnu/packages/firmware.scm
index a71104c..2bc93f5 100644
--- a/nongnu/packages/firmware.scm
+++ b/nongnu/packages/firmware.scm
@@ -8,6 +8,7 @@
   #:use-module (guix build-system copy)
   #:use-module (guix build-system gnu)
   #:use-module (guix download)
+  #:use-module (guix git-download)
   #:use-module (guix gexp)
   #:use-module (guix git-download)
   #:use-module ((guix licenses) #:prefix guix-license:)
@@ -36,6 +37,32 @@
                                #$output "/libexec")
                 "-Dsupported_build=true"))))))
 
+;; Firmware for Eink display
+(define-public pinenote-firmware
+  (let ((commit "f47f34b968cb6d9385ed4c15c6a7af236227f5f0")
+        (revision "1"))
+    (package
+      (name "pinenote-firmware")
+      (version "")
+      (home-page "https://gitlab.com/phodina/pinenote-firmware")
+      (source (origin
+                (method git-fetch)
+                (uri (git-reference
+                      (url home-page)
+                      (commit commit)))
+                (file-name (git-file-name name version))
+                (sha256
+                 (base32
+                  "06wpqalz57wd6av8yz77gyq4j3hiwx76hanm3bag22b6hda23zgb"))))
+      (build-system copy-build-system)
+      ;; (arguments
+      ;; `(#:install-plan
+      ;; (list (list ".*" "lib/firmware/"))))
+      (synopsis "Firmware for the PineNote")
+      (description
+       "This package contains dump of the firmware from the PineNote.")
+      (license (nonfree (string-append "unknown"))))))
+
 (define-public ov5640-firmware
   (let ((commit "6e8e591e17e207644dfe747e51026967bb1edab5")
         (revision "1"))
diff --git a/nongnu/packages/linux.scm b/nongnu/packages/linux.scm
index f82be7d..917fc86 100644
--- a/nongnu/packages/linux.scm
+++ b/nongnu/packages/linux.scm
@@ -37,6 +37,7 @@
   #:use-module (guix build-system linux-module)
   #:use-module (guix build-system trivial)
   #:use-module (ice-9 match)
+  #:use-module (srfi srfi-1)
   #:use-module (nonguix licenses)
   #:use-module (srfi srfi-1)
   #:export (corrupt-linux))
@@ -47,6 +48,19 @@
                        "/linux/kernel/v" (version-major version) ".x"
                        "/linux-" version ".tar.xz"))
 
+(define (linux-pinenote-urls commit)
+  "Return a list of URLS for Linux VERSION."
+  (list (string-append
+  "https://gitlab.com/pgwipeout/linux-next/-/archive/"
+commit "/linux-next-" commit ".tar.gz")))
+;  "https://github.com/m-weigand/linux/archive/refs/heads/mw/rk35/pinenote-next-t1.tar.gz")))
+
+(define (linux-pinephone-urls version commit)
+  "Return a list of URLS for Linux VERSION."
+  (list (string-append
+  "https://github.com/megous/linux/archive/refs/tags/orange-pi-"
+  (version-major+minor version) "-" commit ".tar.gz")))
+
 (define* (corrupt-linux freedo #:key (name "linux"))
 
   ;; TODO: This very directly depends on guix internals.
@@ -86,6 +100,78 @@
        "The unmodified Linux kernel, including nonfree blobs, for running Guix System
 on hardware which requires nonfree software to function."))))
 
+;; Linux kernel fork for PinePhone and PinePhone Pro
+(define* (pinephone-linux freedo version-megi release defconfig #:key (name "linux"))
+  (package
+   (inherit
+    (customize-linux
+     #:name name
+     #:defconfig defconfig
+     #:source (origin (inherit (package-source freedo))
+                      (method url-fetch)
+					  (file-name (string-append name "-" (version-major+minor
+					  version-megi)
+					  "-guix.tar.gz"))
+                      (uri (linux-pinephone-urls version-megi
+					  release))
+    (patches
+     (parameterize
+         ((%patch-path
+           (map (lambda (directory)
+                  (string-append directory "/nongnu/packages/patches"))
+                %load-path)))
+       (search-patches 
+	   "linux-pinephone-pro-defconfig-guix-fix.patch"))))))
+;	   ;; Port bootsplash patches
+;;;"pinephone-0001-bootsplash.patch"
+;;;"pinephone-0002-bootsplash.patch"
+;;"pinephone-revert-fbcon-remove-now-unusued-softback_lines-cursor-argument.patch"
+;;;"pinephone-0003-bootsplash.patch"
+;;"pinephone-fbcon-remove-no-op-fbcon_set_origin.patch"
+;;;"pinephone-0004-bootsplash.patch"
+;;"pinephone-revert-fbcon-remove-soft-scrollback-code.patch"
+;;;"pinephone-0005-bootsplash.patch"
+;;;"pinephone-0004-bootsplash.patch"
+;;;"pinephone-0006-bootsplash.patch"
+;;;"pinephone-0007-bootsplash.patch"
+;;;"pinephone-0008-bootsplash.patch"
+;;;"pinephone-0009-bootsplash.patch"
+;;;"pinephone-0010-bootsplash.patch"
+;;;"pinephone-0011-bootsplash.patch"
+;;"pinephone-drop-modem-power-node.patch"
+;;"pinephone-pro-add-modem-ri.patch.patch"
+;;"pinephone-pro-remove-modem-node.patch"
+;                       ))))))
+   (version (package-version freedo))
+   (home-page "https://www.kernel.org/")
+   (synopsis "Linux kernel with nonfree binary blobs included")
+   (description
+    "The unmodified Linux kernel, including nonfree blobs, for running Guix
+System on hardware which requires nonfree software to function.")))
+
+; TODO: Power supply fix
+; https://github.com/DorianRudolph/linux/commit/822294664906499682b55264ae0553ee05caa352
+;; Linux kernel fork for PineNote
+(define* (pinenote-linux freedo commit defconfig #:key (name "linux"))
+  (package
+   (inherit
+    (customize-linux
+     #:name name
+     #:defconfig (local-file
+	 (string-append "nongnu/configs/" defconfig))
+     #:source (origin (inherit (package-source freedo))
+                      (method url-fetch)
+					  (file-name (string-append name "-" version
+					  "-guix.tar.gz"))
+                      (uri (linux-pinenote-urls commit))
+                      (patches '()))))
+   (version (package-version freedo))
+   (home-page "https://www.kernel.org/")
+   (synopsis "Linux kernel with nonfree binary blobs included")
+   (description
+    "The unmodified Linux kernel, including nonfree blobs, for running Guix
+System on hardware which requires nonfree software to function.")))
+
 (define-public linux-6.1
   (corrupt-linux linux-libre-6.1))
 
@@ -118,6 +204,25 @@ on hardware which requires nonfree software to function."))))
 
 (define-public linux-arm64-generic-lts linux-arm64-generic-5.15)
 
+(define-public linux-pinephone-pro
+  (pinephone-linux linux-libre-arm64-generic "6.1" "20230104-1712" "pinephone_pro_defconfig"
+#:name "linux-pinephone-pro"))
+
+(define-public linux-pinephone
+  (pinephone-linux linux-libre-arm64-generic "6.1" "20230104-1712" "pinephone_defconfig"
+#:name "linux-pinephone"))
+
+;; pinenote-next-t1 branch
+(define-public linux-pinenote
+  (pinenote-linux linux-arm64-generic
+  "7a28914fbf71b1a04e5484ec04205b20c8abe34c" "pinenote_defconfig"
+#:name "linux-pinenote"))
+
+(define-public linux-quartz64
+  (pinenote-linux linux-arm64-generic
+  "9abf2313adc1ca1b6180c508c25f22f9395cc780" "quartz64_defconfig"
+#:name "linux-quartz64"))
+
 (define-public linux-firmware
   (package
     (name "linux-firmware")
diff --git a/nongnu/packages/patches/0001-Rudimentary-attempt-to-keep-PMIC-usable-after-suspen.patch b/nongnu/packages/patches/0001-Rudimentary-attempt-to-keep-PMIC-usable-after-suspen.patch
new file mode 100644
index 0000000..f380471
--- /dev/null
+++ b/nongnu/packages/patches/0001-Rudimentary-attempt-to-keep-PMIC-usable-after-suspen.patch
@@ -0,0 +1,49 @@
+From 34054942047728627c9f5aad92e85669c4bb34e8 Mon Sep 17 00:00:00 2001
+From: hrdl <7808331-hrdl@users.noreply.gitlab.com>
+Date: Sun, 12 Jun 2022 15:47:20 +0000
+Subject: [PATCH] Rudimentary attempt to keep PMIC usable after suspend
+
+---
+ drivers/regulator/tps65185-regulator.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/regulator/tps65185-regulator.c b/drivers/regulator/tps65185-regulator.c
+index d7730ff98c13..59327f41c8e2 100644
+--- a/drivers/regulator/tps65185-regulator.c
++++ b/drivers/regulator/tps65185-regulator.c
+@@ -664,6 +664,24 @@ static int tps65185_probe(struct i2c_client *client)
+ 	return 0;
+ }
+ 
++static int __maybe_unused tps65185_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++
++	struct tps65185 *tps;
++	int ret;
++
++	tps = i2c_get_clientdata(client);
++
++	ret = tps65185_set_config(dev, tps);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to set config at resume\n");
++
++	return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(tps65185_pm, NULL, tps65185_resume);
++
+ static const struct of_device_id tps65185_of_match[] = {
+ 	{ .compatible = "ti,tps65185" },
+ 	{}
+@@ -674,6 +692,7 @@ static struct i2c_driver tps65185_driver = {
+ 	.probe_new	= tps65185_probe,
+ 	.driver		= {
+ 		.name		= "tps65185",
++		.pm		= &tps65185_pm,
+ 		.of_match_table	= tps65185_of_match,
+ 	},
+ };
+-- 
+2.36.1
+
diff --git a/nongnu/packages/patches/battery-level.patch b/nongnu/packages/patches/battery-level.patch
new file mode 100644
index 0000000..a0df8c3
--- /dev/null
+++ b/nongnu/packages/patches/battery-level.patch
@@ -0,0 +1,62 @@
+From 822294664906499682b55264ae0553ee05caa352 Mon Sep 17 00:00:00 2001
+From: Dorian Rudolph <mail@dorianrudolph.com>
+Date: Sat, 14 May 2022 14:28:37 +0200
+Subject: [PATCH] fix power_supply_temp2resist_simple and
+ power_supply_ocv2cap_simple
+
+---
+ drivers/power/supply/power_supply_core.c | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c
+index ec838c9bcc0a5e..3828ba9d0eab90 100644
+--- a/drivers/power/supply/power_supply_core.c
++++ b/drivers/power/supply/power_supply_core.c
+@@ -801,17 +801,17 @@ int power_supply_temp2resist_simple(struct power_supply_resistance_temp_table *t
+ {
+ 	int i, high, low;
+ 
+-	/* Break loop at table_len - 1 because that is the highest index */
+-	for (i = 0; i < table_len - 1; i++)
++	for (i = 0; i < table_len; i++)
+ 		if (temp > table[i].temp)
+ 			break;
+ 
+ 	/* The library function will deal with high == low */
+-	if ((i == 0) || (i == (table_len - 1)))
+-		high = i;
++	if (i == 0)
++		high = low = i;
++	else if (i == table_len)
++		high = low = i - 1;
+ 	else
+-		high = i - 1;
+-	low = i;
++		high = (low = i) - 1;
+ 
+ 	return fixp_linear_interpolate(table[low].temp,
+ 				       table[low].resistance,
+@@ -838,17 +838,17 @@ int power_supply_ocv2cap_simple(struct power_supply_battery_ocv_table *table,
+ {
+ 	int i, high, low;
+ 
+-	/* Break loop at table_len - 1 because that is the highest index */
+-	for (i = 0; i < table_len - 1; i++)
++	for (i = 0; i < table_len; i++)
+ 		if (ocv > table[i].ocv)
+ 			break;
+ 
+ 	/* The library function will deal with high == low */
+-	if ((i == 0) || (i == (table_len - 1)))
+-		high = i - 1;
++	if (i == 0)
++		high = low = i;
++	else if (i == table_len)
++		high = low = i - 1;
+ 	else
+-		high = i; /* i.e. i == 0 */
+-	low = i;
++		high = (low = i) - 1;
+ 
+ 	return fixp_linear_interpolate(table[low].ocv,
+ 				       table[low].capacity,
diff --git a/nongnu/packages/patches/linux-pinephone-pro-defconfig-guix-fix.patch b/nongnu/packages/patches/linux-pinephone-pro-defconfig-guix-fix.patch
new file mode 100644
index 0000000..a82318e
--- /dev/null
+++ b/nongnu/packages/patches/linux-pinephone-pro-defconfig-guix-fix.patch
@@ -0,0 +1,13 @@
+--- a/arch/arm64/configs/pinephone_pro_defconfig.orig	2023-01-14 08:25:28.004411948 +0100
++++ b/arch/arm64/configs/pinephone_pro_defconfig	2023-01-14 08:47:08.696514744 +0100
+@@ -252,8 +252,8 @@
+ CONFIG_UEVENT_HELPER=y
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+-#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s brcm/brcmfmac43455-sdio.bin brcm/brcmfmac43455-sdio.pine64,pinephone-pro.txt brcm/brcmfmac43455-sdio.clm_blob brcm/BCM4345C0.hcd rockchip/dptx.bin"
+-#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_EXTRA_FIRMWARE_DIR is not set
+ CONFIG_ARM_SCMI_PROTOCOL=y
+ CONFIG_ARM_SCPI_PROTOCOL=y
+ CONFIG_MTD=y
diff --git a/nongnu/packages/patches/pinenote-battery-level.patch b/nongnu/packages/patches/pinenote-battery-level.patch
new file mode 100644
index 0000000..a0df8c3
--- /dev/null
+++ b/nongnu/packages/patches/pinenote-battery-level.patch
@@ -0,0 +1,62 @@
+From 822294664906499682b55264ae0553ee05caa352 Mon Sep 17 00:00:00 2001
+From: Dorian Rudolph <mail@dorianrudolph.com>
+Date: Sat, 14 May 2022 14:28:37 +0200
+Subject: [PATCH] fix power_supply_temp2resist_simple and
+ power_supply_ocv2cap_simple
+
+---
+ drivers/power/supply/power_supply_core.c | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c
+index ec838c9bcc0a5e..3828ba9d0eab90 100644
+--- a/drivers/power/supply/power_supply_core.c
++++ b/drivers/power/supply/power_supply_core.c
+@@ -801,17 +801,17 @@ int power_supply_temp2resist_simple(struct power_supply_resistance_temp_table *t
+ {
+ 	int i, high, low;
+ 
+-	/* Break loop at table_len - 1 because that is the highest index */
+-	for (i = 0; i < table_len - 1; i++)
++	for (i = 0; i < table_len; i++)
+ 		if (temp > table[i].temp)
+ 			break;
+ 
+ 	/* The library function will deal with high == low */
+-	if ((i == 0) || (i == (table_len - 1)))
+-		high = i;
++	if (i == 0)
++		high = low = i;
++	else if (i == table_len)
++		high = low = i - 1;
+ 	else
+-		high = i - 1;
+-	low = i;
++		high = (low = i) - 1;
+ 
+ 	return fixp_linear_interpolate(table[low].temp,
+ 				       table[low].resistance,
+@@ -838,17 +838,17 @@ int power_supply_ocv2cap_simple(struct power_supply_battery_ocv_table *table,
+ {
+ 	int i, high, low;
+ 
+-	/* Break loop at table_len - 1 because that is the highest index */
+-	for (i = 0; i < table_len - 1; i++)
++	for (i = 0; i < table_len; i++)
+ 		if (ocv > table[i].ocv)
+ 			break;
+ 
+ 	/* The library function will deal with high == low */
+-	if ((i == 0) || (i == (table_len - 1)))
+-		high = i - 1;
++	if (i == 0)
++		high = low = i;
++	else if (i == table_len)
++		high = low = i - 1;
+ 	else
+-		high = i; /* i.e. i == 0 */
+-	low = i;
++		high = (low = i) - 1;
+ 
+ 	return fixp_linear_interpolate(table[low].ocv,
+ 				       table[low].capacity,
diff --git a/nongnu/packages/patches/pinenote-rockchip-ebc-patches-mw.patch b/nongnu/packages/patches/pinenote-rockchip-ebc-patches-mw.patch
new file mode 100644
index 0000000..7fcd508
--- /dev/null
+++ b/nongnu/packages/patches/pinenote-rockchip-ebc-patches-mw.patch
@@ -0,0 +1,2852 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/37] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irc from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+ 
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+ 
+-- 
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/37] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+-- 
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/37] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+ 
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+ 
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+ 
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+ 
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+ 
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+ 
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	if (!pm_runtime_status_suspended(dev))
+-- 
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/37] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+-- 
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/37] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+ 
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+-- 
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/37] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+ 
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+ 
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+ 
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+ 
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+-- 
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/37] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/37] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/37] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/37] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+-- 
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/37] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+ 
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+ 
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+ 
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+ 
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+ 
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+ 
+-- 
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/37] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+ 
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+ 
+-- 
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/37] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+ 
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+ 
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+ 
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+ 
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+ 
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+-- 
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/37] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+ 
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+ 
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/37] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+ 
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+ 
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+ 
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+-- 
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/37] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+ 
+ 			// we need four new rokchip_ebc_area entries that we splice into
+-- 
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/37] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+-- 
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/37] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+ 
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+ 
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+ 			*split_counter++;
+-- 
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/37] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+-			*split_counter++;
++			(*split_counter)++;
+ 
+ 			// let the outer loop delete this area
+ 			return false;
+-- 
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/37] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+-- 
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/37] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+ 
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/37] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+ 
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+ 
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+-- 
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/37] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+ 
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+ 
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+-- 
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/37] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-- 
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/37] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+-- 
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/37] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+ 
+ 		// try to split, otherwise continue
+-- 
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/37] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+ 
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+-- 
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/37] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+ 
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+ 
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+ 
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+ 
+-- 
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/37] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-- 
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/37] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/37] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+ 
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+ 
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+ 
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+ 
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+ 
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+-- 
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/37] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+ 
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+ 
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+ 
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+ 
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+ 
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+ 
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+ 
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+ 
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+ 
+-- 
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/37] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+-- 
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/37] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/37] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+ 
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+-- 
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/37] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+ 
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+-- 
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/37] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+ 
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/pinenote-touchscreen-1.patch b/nongnu/packages/patches/pinenote-touchscreen-1.patch
new file mode 100644
index 0000000..20026b4
--- /dev/null
+++ b/nongnu/packages/patches/pinenote-touchscreen-1.patch
@@ -0,0 +1,976 @@
+From a24cb29eca1a72afb1037f5468d3036b34ea1b66 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
+Date: Sun, 9 Jan 2022 21:53:28 +1000
+Subject: [PATCH] Input: Add driver for Cypress Generation 5 touchscreen
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the basic driver for the Cypress TrueTouch Gen5 touchscreen
+controllers. This driver supports only the I2C bus but it uses regmap
+so SPI support could be added later.
+The touchscreen can retrieve some defined zone that are handled as
+buttons (according to the hardware). That is why it handles
+button and multitouch events.
+
+Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
+Tested-by: Andreas Kemnade <andreas@kemnade.info> # Kobo Clara HD
+---
+ drivers/input/touchscreen/Kconfig   |  16 +
+ drivers/input/touchscreen/Makefile  |   1 +
+ drivers/input/touchscreen/cyttsp5.c | 902 ++++++++++++++++++++++++++++
+ 3 files changed, 919 insertions(+)
+ create mode 100644 drivers/input/touchscreen/cyttsp5.c
+
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 2f6adfb7b938..eb4e1b156683 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -284,6 +284,22 @@ config TOUCHSCREEN_CYTTSP4_SPI
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called cyttsp4_spi.
+ 
++config TOUCHSCREEN_CYTTSP5
++	tristate "Cypress TrueTouch Gen5 Touchscreen Driver"
++	depends on I2C
++	select REGMAP_I2C
++	select CRC_ITU_T
++	help
++	  Driver for Parade TrueTouch Standard Product Generation 5
++	  touchscreen controllers. I2C bus interface support only.
++
++	  Say Y here if you have a Cypress Gen5 touchscreen.
++
++	  If unsure, say N.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called cyttsp5.
++
+ config TOUCHSCREEN_DA9034
+ 	tristate "Touchscreen support for Dialog Semiconductor DA9034"
+ 	depends on PMIC_DA903X
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+index 39a8127cf6a5..0ea5c47f7fd9 100644
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -30,6 +30,7 @@ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_SPI)	+= cyttsp_spi.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_CORE)	+= cyttsp4_core.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_I2C)	+= cyttsp4_i2c.o cyttsp_i2c_common.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_SPI)	+= cyttsp4_spi.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP5)	+= cyttsp5.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9034)	+= da9034-ts.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9052)	+= da9052_tsi.o
+ obj-$(CONFIG_TOUCHSCREEN_DYNAPRO)	+= dynapro.o
+diff --git a/drivers/input/touchscreen/cyttsp5.c b/drivers/input/touchscreen/cyttsp5.c
+new file mode 100644
+index 000000000000..3ac45108090c
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp5.c
+@@ -0,0 +1,902 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Parade TrueTouch(TM) Standard Product V5 Module.
++ *
++ * Copyright (C) 2015 Parade Technologies
++ * Copyright (C) 2012-2015 Cypress Semiconductor
++ * Copyright (C) 2018 Bootlin
++ *
++ * Authors: Mylène Josserand <mylene.josserand@bootlin.com>
++ *                Alistair Francis <alistair@alistair23.me>
++ */
++
++#include <linux/crc-itu-t.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/input/mt.h>
++#include <linux/input/touchscreen.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <asm/unaligned.h>
++
++#define CYTTSP5_NAME				"cyttsp5"
++#define CY_I2C_DATA_SIZE			(2 * 256)
++#define HID_VERSION				0x0100
++#define CY_MAX_INPUT				512
++#define CYTTSP5_PREALLOCATED_CMD_BUFFER	32
++#define CY_BITS_PER_BTN			1
++#define CY_NUM_BTN_EVENT_ID			GENMASK(CY_BITS_PER_BTN, 0)
++
++#define MAX_AREA				255
++#define HID_OUTPUT_BL_SOP			0x1
++#define HID_OUTPUT_BL_EOP			0x17
++#define HID_OUTPUT_BL_LAUNCH_APP		0x3B
++#define HID_OUTPUT_BL_LAUNCH_APP_SIZE		11
++#define HID_OUTPUT_GET_SYSINFO			0x2
++#define HID_OUTPUT_GET_SYSINFO_SIZE		5
++#define HID_OUTPUT_MAX_CMD_SIZE		12
++
++#define HID_DESC_REG				0x1
++#define HID_INPUT_REG				0x3
++#define HID_OUTPUT_REG				0x4
++
++#define REPORT_ID_TOUCH			0x1
++#define REPORT_ID_BTN				0x3
++#define REPORT_SIZE_5				5
++#define REPORT_SIZE_8				8
++#define REPORT_SIZE_16				16
++
++/* Touch reports offsets */
++/* Header offsets */
++#define TOUCH_REPORT_DESC_HDR_CONTACTCOUNT	16
++/* Record offsets */
++#define TOUCH_REPORT_DESC_CONTACTID		8
++#define TOUCH_REPORT_DESC_X			16
++#define TOUCH_REPORT_DESC_Y			32
++#define TOUCH_REPORT_DESC_P			48
++#define TOUCH_REPORT_DESC_MAJ			56
++#define TOUCH_REPORT_DESC_MIN			64
++
++/* HID */
++#define HID_TOUCH_REPORT_ID			0x1
++#define HID_BTN_REPORT_ID			0x3
++#define HID_APP_RESPONSE_REPORT_ID		0x1F
++#define HID_APP_OUTPUT_REPORT_ID		0x2F
++#define HID_BL_RESPONSE_REPORT_ID		0x30
++#define HID_BL_OUTPUT_REPORT_ID		0x40
++
++#define HID_OUTPUT_RESPONSE_REPORT_OFFSET	2
++#define HID_OUTPUT_RESPONSE_CMD_OFFSET		4
++#define HID_OUTPUT_RESPONSE_CMD_MASK		GENMASK(6, 0)
++
++#define HID_SYSINFO_SENSING_OFFSET		33
++#define HID_SYSINFO_BTN_OFFSET			48
++#define HID_SYSINFO_BTN_MASK			GENMASK(7, 0)
++#define HID_SYSINFO_MAX_BTN			8
++
++#define CY_HID_OUTPUT_TIMEOUT_MS			200
++#define CY_HID_OUTPUT_GET_SYSINFO_TIMEOUT_MS	3000
++#define CY_HID_GET_HID_DESCRIPTOR_TIMEOUT_MS	4000
++
++/* maximum number of concurrent tracks */
++#define TOUCH_REPORT_SIZE			10
++#define TOUCH_INPUT_HEADER_SIZE		7
++#define BTN_REPORT_SIZE			9
++#define BTN_INPUT_HEADER_SIZE			5
++
++#define MAX_CY_TCH_T_IDS	32
++
++/* All usage pages for Touch Report */
++#define TOUCH_REPORT_USAGE_PG_X		0x00010030
++#define TOUCH_REPORT_USAGE_PG_Y		0x00010031
++#define TOUCH_REPORT_USAGE_PG_P		0x000D0030
++#define TOUCH_REPORT_USAGE_PG_CONTACTID	0x000D0051
++#define TOUCH_REPORT_USAGE_PG_CONTACTCOUNT	0x000D0054
++#define TOUCH_REPORT_USAGE_PG_MAJ		0xFF010062
++#define TOUCH_REPORT_USAGE_PG_MIN		0xFF010063
++#define TOUCH_COL_USAGE_PG			0x000D0022
++
++/* System Information interface definitions */
++struct cyttsp5_sensing_conf_data_dev {
++	u8 electrodes_x;
++	u8 electrodes_y;
++	__le16 len_x;
++	__le16 len_y;
++	__le16 res_x;
++	__le16 res_y;
++	__le16 max_z;
++	u8 origin_x;
++	u8 origin_y;
++	u8 btn;
++	u8 scan_mode;
++	u8 max_num_of_tch_per_refresh_cycle;
++} __packed;
++
++struct cyttsp5_sensing_conf_data {
++	u16 res_x;
++	u16 res_y;
++	u16 max_z;
++	u16 len_x;
++	u16 len_y;
++	u8 origin_x;
++	u8 origin_y;
++	u8 max_tch;
++};
++
++enum cyttsp5_tch_abs {	/* for ordering within the extracted touch data array */
++	CY_TCH_X,	/* X */
++	CY_TCH_Y,	/* Y */
++	CY_TCH_P,	/* P (Z) */
++	CY_TCH_T,	/* TOUCH ID */
++	CY_TCH_MAJ,	/* TOUCH_MAJOR */
++	CY_TCH_MIN,	/* TOUCH_MINOR */
++	CY_TCH_NUM_ABS
++};
++
++struct cyttsp5_tch_abs_params {
++	size_t ofs;	/* abs byte offset */
++	size_t size;	/* size in bits */
++	size_t min;	/* min value */
++	size_t max;	/* max value */
++	size_t bofs;	/* bit offset */
++};
++
++struct cyttsp5_touch {
++	int abs[CY_TCH_NUM_ABS];
++};
++
++struct cyttsp5_sysinfo {
++	struct cyttsp5_sensing_conf_data sensing_conf_data;
++	int num_btns;
++	struct cyttsp5_tch_abs_params tch_hdr;
++	struct cyttsp5_tch_abs_params tch_abs[CY_TCH_NUM_ABS];
++	u32 key_code[HID_SYSINFO_MAX_BTN];
++};
++
++struct cyttsp5_hid_desc {
++	__le16 hid_desc_len;
++	u8 packet_id;
++	u8 reserved_byte;
++	__le16 bcd_version;
++	__le16 report_desc_len;
++	__le16 report_desc_register;
++	__le16 input_register;
++	__le16 max_input_len;
++	__le16 output_register;
++	__le16 max_output_len;
++	__le16 command_register;
++	__le16 data_register;
++	__le16 vendor_id;
++	__le16 product_id;
++	__le16 version_id;
++	u8 reserved[4];
++} __packed;
++
++struct cyttsp5 {
++	struct device *dev;
++	struct completion cmd_done;
++	struct cyttsp5_sysinfo sysinfo;
++	struct cyttsp5_hid_desc hid_desc;
++	u8 cmd_buf[CYTTSP5_PREALLOCATED_CMD_BUFFER];
++	u8 input_buf[CY_MAX_INPUT];
++	u8 response_buf[CY_MAX_INPUT];
++	struct gpio_desc *reset_gpio;
++	struct input_dev *input;
++	char phys[NAME_MAX];
++	int num_prv_rec;
++	struct regmap *regmap;
++	struct touchscreen_properties prop;
++	struct regulator *vdd;
++};
++
++/*
++ * For what is understood in the datasheet, the register does not
++ * matter. For consistency, use the Input Register address
++ * but it does mean anything to the device. The important data
++ * to send is the I2C address
++ */
++static int cyttsp5_read(struct cyttsp5 *ts, u8 *buf, u32 max)
++{
++	int error;
++	u32 size;
++	u8 temp[2];
++
++	/* Read the frame to retrieve the size */
++	error = regmap_bulk_read(ts->regmap, HID_INPUT_REG, temp, sizeof(temp));
++	if (error)
++		return error;
++
++	size = get_unaligned_le16(temp);
++	if (!size || size == 2)
++		return 0;
++
++	if (size > max)
++		return -EINVAL;
++
++	/* Get the real value */
++	return regmap_bulk_read(ts->regmap, HID_INPUT_REG, buf, size);
++}
++
++static int cyttsp5_write(struct cyttsp5 *ts, unsigned int reg, u8 *data,
++			 size_t size)
++{
++	u8 cmd[HID_OUTPUT_MAX_CMD_SIZE];
++
++	if (size + 1 > HID_OUTPUT_MAX_CMD_SIZE)
++		return -E2BIG;
++
++	/* High bytes of register address needed as first byte of cmd */
++	cmd[0] = (reg >> 8) & 0xFF ;
++
++	/* Copy the rest of the data */
++	if (data)
++		memcpy(&cmd[1], data, size);
++
++	/*
++	 * The hardware wants to receive a frame with the address register
++	 * contained in the first two bytes. As the regmap_write function
++	 * add the register adresse in the frame, we use the low byte as
++	 * first frame byte for the address register and the first
++	 * data byte is the high register + left of the cmd to send
++	 */
++	return regmap_bulk_write(ts->regmap, reg & 0xFF, cmd, size + 1);
++}
++
++static void cyttsp5_get_touch_axis(int *axis, int size, int max, u8 *xy_data,
++				   int bofs)
++{
++	int nbyte;
++
++	for (nbyte = 0, *axis = 0; nbyte < size; nbyte++)
++		*axis += ((xy_data[nbyte] >> bofs) << (nbyte * 8));
++
++	*axis &= max - 1;
++}
++
++static void cyttsp5_get_touch_record(struct cyttsp5 *ts,
++				     struct cyttsp5_touch *touch, u8 *xy_data)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	enum cyttsp5_tch_abs abs;
++
++	for (abs = CY_TCH_X; abs < CY_TCH_NUM_ABS; abs++)
++		cyttsp5_get_touch_axis(&touch->abs[abs],
++				       si->tch_abs[abs].size,
++				       si->tch_abs[abs].max,
++				       xy_data + si->tch_abs[abs].ofs,
++				       si->tch_abs[abs].bofs);
++}
++
++static void cyttsp5_get_mt_touches(struct cyttsp5 *ts,
++				   struct cyttsp5_touch *tch, int num_cur_tch)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int i, t = 0, offset = 0;
++	DECLARE_BITMAP(ids, MAX_CY_TCH_T_IDS);
++	u8 *tch_addr;
++	int tmp;
++
++	bitmap_zero(ids, MAX_CY_TCH_T_IDS);
++	memset(tch->abs, 0, sizeof(tch->abs));
++
++	switch (ts->input_buf[2]) {
++	case HID_TOUCH_REPORT_ID:
++		offset = TOUCH_INPUT_HEADER_SIZE;
++		break;
++	case HID_BTN_REPORT_ID:
++		offset = BTN_INPUT_HEADER_SIZE;
++		break;
++	}
++
++	for (i = 0; i < num_cur_tch; i++) {
++		tch_addr = ts->input_buf + offset + (i * TOUCH_REPORT_SIZE);
++		cyttsp5_get_touch_record(ts, tch, tch_addr);
++
++		/* Convert MAJOR/MINOR from mm to resolution */
++		tmp = tch->abs[CY_TCH_MAJ] * 100 * si->sensing_conf_data.res_x;
++		tch->abs[CY_TCH_MAJ] = tmp / si->sensing_conf_data.len_x;
++		tmp = tch->abs[CY_TCH_MIN] * 100 * si->sensing_conf_data.res_x;
++		tch->abs[CY_TCH_MIN] = tmp / si->sensing_conf_data.len_x;
++
++		t = tch->abs[CY_TCH_T];
++		input_mt_slot(ts->input, t);
++		input_mt_report_slot_state(ts->input, MT_TOOL_FINGER, true);
++		__set_bit(t, ids);
++
++		/* position and pressure fields */
++		touchscreen_report_pos(ts->input, &ts->prop,
++				       tch->abs[CY_TCH_X], tch->abs[CY_TCH_Y],
++				       true);
++		input_report_abs(ts->input, ABS_MT_PRESSURE,
++				 tch->abs[CY_TCH_P]);
++
++		/* Get the extended touch fields */
++		input_report_abs(ts->input, ABS_MT_TOUCH_MAJOR,
++				 tch->abs[CY_TCH_MAJ]);
++		input_report_abs(ts->input, ABS_MT_TOUCH_MINOR,
++				 tch->abs[CY_TCH_MIN]);
++	}
++
++	ts->num_prv_rec = num_cur_tch;
++}
++
++static int cyttsp5_mt_attention(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int max_tch = si->sensing_conf_data.max_tch;
++	struct cyttsp5_touch tch;
++	u8 num_cur_tch;
++
++	cyttsp5_get_touch_axis((int *) &num_cur_tch, si->tch_hdr.size,
++			       si->tch_hdr.max,
++			       ts->input_buf + 3 + si->tch_hdr.ofs,
++			       si->tch_hdr.bofs);
++
++	if (num_cur_tch > max_tch) {
++		dev_err(dev, "Num touch err detected (n=%d)\n", num_cur_tch);
++		num_cur_tch = max_tch;
++	}
++
++	if (num_cur_tch == 0 && ts->num_prv_rec == 0)
++		return 0;
++
++	/* extract xy_data for all currently reported touches */
++	if (num_cur_tch)
++		cyttsp5_get_mt_touches(ts, &tch, num_cur_tch);
++
++	input_mt_sync_frame(ts->input);
++	input_sync(ts->input);
++
++	return 0;
++}
++
++static int cyttsp5_setup_input_device(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int max_x, max_y, max_p;
++	int max_x_tmp, max_y_tmp;
++	int error;
++
++	max_x_tmp = si->sensing_conf_data.res_x;
++	max_y_tmp = si->sensing_conf_data.res_y;
++	max_x = max_x_tmp - 1;
++	max_y = max_y_tmp - 1;
++	max_p = si->sensing_conf_data.max_z;
++
++	input_set_abs_params(ts->input, ABS_MT_POSITION_X, 0, max_x, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_POSITION_Y, 0, max_y, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_PRESSURE, 0, max_p, 0, 0);
++
++	input_set_abs_params(ts->input, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_TOUCH_MINOR, 0, MAX_AREA, 0, 0);
++
++	error = input_mt_init_slots(ts->input, si->tch_abs[CY_TCH_T].max,
++		INPUT_MT_DROP_UNUSED | INPUT_MT_DIRECT);
++	if (error < 0)
++		return error;
++
++	error = input_register_device(ts->input);
++	if (error < 0)
++		dev_err(dev, "Error, failed register input device r=%d\n", error);
++
++	return error;
++}
++
++static int cyttsp5_parse_dt_key_code(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++
++	if (!si->num_btns)
++		return 0;
++
++	/* Initialize the button to RESERVED */
++	memset32(si->key_code, KEY_RESERVED,  si->num_btns);
++
++	return device_property_read_u32_array(dev, "linux,keycodes",
++				   si->key_code, si->num_btns);
++}
++
++static int cyttsp5_btn_attention(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int cur_btn, offset = 0;
++	int cur_btn_state;
++
++	switch (ts->input_buf[2]) {
++	case HID_TOUCH_REPORT_ID:
++		offset = TOUCH_INPUT_HEADER_SIZE;
++		break;
++	case HID_BTN_REPORT_ID:
++		offset = BTN_INPUT_HEADER_SIZE;
++		break;
++	}
++
++	if (ts->input_buf[2] != HID_BTN_REPORT_ID || !si->num_btns)
++		return 0;
++
++	/* extract button press/release touch information */
++	for (cur_btn = 0; cur_btn < si->num_btns; cur_btn++) {
++		/* Get current button state */
++		cur_btn_state = (ts->input_buf[offset] >> (cur_btn * CY_BITS_PER_BTN))
++			& CY_NUM_BTN_EVENT_ID;
++
++		input_report_key(ts->input, si->key_code[cur_btn],
++				 cur_btn_state);
++		input_sync(ts->input);
++	}
++
++	return 0;
++}
++
++static int cyttsp5_validate_cmd_response(struct cyttsp5 *ts, u8 code)
++{
++	u16 size, crc;
++	u8 status, report_id;
++	int command_code;
++
++	size = get_unaligned_le16(&ts->response_buf[0]);
++
++	if (!size)
++		return 0;
++
++	report_id = ts->response_buf[HID_OUTPUT_RESPONSE_REPORT_OFFSET];
++
++	switch (report_id) {
++	case HID_BL_RESPONSE_REPORT_ID: {
++		if (ts->response_buf[4] != HID_OUTPUT_BL_SOP) {
++			dev_err(ts->dev, "HID output response, wrong SOP\n");
++			return -EPROTO;
++		}
++
++		if (ts->response_buf[size - 1] != HID_OUTPUT_BL_EOP) {
++			dev_err(ts->dev, "HID output response, wrong EOP\n");
++			return -EPROTO;
++		}
++
++		crc = crc_itu_t(0xFFFF, &ts->response_buf[4], size - 7);
++		if (get_unaligned_le16(&ts->response_buf[size - 3]) != crc) {
++			dev_err(ts->dev, "HID output response, wrong CRC 0x%X\n",
++				crc);
++			return -EPROTO;
++		}
++
++		status = ts->response_buf[5];
++		if (status) {
++			dev_err(ts->dev, "HID output response, ERROR:%d\n",
++				status);
++			return -EPROTO;
++		}
++		break;
++	}
++	case HID_APP_RESPONSE_REPORT_ID: {
++		command_code = ts->response_buf[HID_OUTPUT_RESPONSE_CMD_OFFSET]
++			& HID_OUTPUT_RESPONSE_CMD_MASK;
++		if (command_code != code) {
++			dev_err(ts->dev,
++				"HID output response, wrong command_code:%X\n",
++				command_code);
++			return -EPROTO;
++		}
++		break;
++	}
++	}
++
++	return 0;
++}
++
++static void cyttsp5_si_get_btn_data(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	unsigned int btns = ts->response_buf[HID_SYSINFO_BTN_OFFSET]
++		& HID_SYSINFO_BTN_MASK;
++
++	si->num_btns = hweight8(btns);
++}
++
++static int cyttsp5_get_sysinfo_regs(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sensing_conf_data *scd = &ts->sysinfo.sensing_conf_data;
++	struct cyttsp5_sensing_conf_data_dev *scd_dev =
++		(struct cyttsp5_sensing_conf_data_dev *)
++		&ts->response_buf[HID_SYSINFO_SENSING_OFFSET];
++
++	cyttsp5_si_get_btn_data(ts);
++
++	scd->max_tch = scd_dev->max_num_of_tch_per_refresh_cycle;
++	scd->res_x = get_unaligned_le16(&scd_dev->res_x);
++	scd->res_y = get_unaligned_le16(&scd_dev->res_y);
++	scd->max_z = get_unaligned_le16(&scd_dev->max_z);
++	scd->len_x = get_unaligned_le16(&scd_dev->len_x);
++	scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++
++	return 0;
++}
++
++static int cyttsp5_hid_output_get_sysinfo(struct cyttsp5 *ts)
++{
++	int rc;
++	u8 cmd[HID_OUTPUT_GET_SYSINFO_SIZE];
++
++	/* HI bytes of Output register address */
++	put_unaligned_le16(HID_OUTPUT_GET_SYSINFO_SIZE, cmd);
++	cmd[2] = HID_APP_OUTPUT_REPORT_ID;
++	cmd[3] = 0x0; /* Reserved */
++	cmd[4] = HID_OUTPUT_GET_SYSINFO;
++
++	rc = cyttsp5_write(ts, HID_OUTPUT_REG, cmd,
++			   HID_OUTPUT_GET_SYSINFO_SIZE);
++	if (rc) {
++		dev_err(ts->dev, "Failed to write command %d", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_OUTPUT_GET_SYSINFO_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID output cmd execution timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	rc = cyttsp5_validate_cmd_response(ts, HID_OUTPUT_GET_SYSINFO);
++	if (rc) {
++		dev_err(ts->dev, "Validation of the response failed\n");
++		return rc;
++	}
++
++	return cyttsp5_get_sysinfo_regs(ts);
++}
++
++static int cyttsp5_hid_output_bl_launch_app(struct cyttsp5 *ts)
++{
++	int rc;
++	u8 cmd[HID_OUTPUT_BL_LAUNCH_APP];
++	u16 crc;
++
++	put_unaligned_le16(HID_OUTPUT_BL_LAUNCH_APP_SIZE, cmd);
++	cmd[2] = HID_BL_OUTPUT_REPORT_ID;
++	cmd[3] = 0x0; /* Reserved */
++	cmd[4] = HID_OUTPUT_BL_SOP;
++	cmd[5] = HID_OUTPUT_BL_LAUNCH_APP;
++	put_unaligned_le16(0x00, &cmd[6]);
++	crc = crc_itu_t(0xFFFF, &cmd[4], 4);
++	put_unaligned_le16(crc, &cmd[8]);
++	cmd[10] = HID_OUTPUT_BL_EOP;
++
++	rc = cyttsp5_write(ts, HID_OUTPUT_REG, cmd,
++			   HID_OUTPUT_BL_LAUNCH_APP_SIZE);
++	if (rc) {
++		dev_err(ts->dev, "Failed to write command %d", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_OUTPUT_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID output cmd execution timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	rc = cyttsp5_validate_cmd_response(ts, HID_OUTPUT_BL_LAUNCH_APP);
++	if (rc) {
++		dev_err(ts->dev, "Validation of the response failed\n");
++		return rc;
++	}
++
++	return 0;
++}
++
++static int cyttsp5_get_hid_descriptor(struct cyttsp5 *ts,
++				      struct cyttsp5_hid_desc *desc)
++{
++	struct device *dev = ts->dev;
++	__le16 hid_desc_register = HID_DESC_REG;
++	int rc;
++	u8 cmd[2];
++
++	/* Set HID descriptor register */
++	memcpy(cmd, &hid_desc_register, sizeof(hid_desc_register));
++
++	rc = cyttsp5_write(ts, HID_DESC_REG, NULL, 0);
++	if (rc) {
++		dev_err(dev, "Failed to get HID descriptor, rc=%d\n", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_GET_HID_DESCRIPTOR_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID get descriptor timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	memcpy(desc, ts->response_buf, sizeof(*desc));
++
++	/* Check HID descriptor length and version */
++	if (le16_to_cpu(desc->hid_desc_len) != sizeof(*desc) ||
++	    le16_to_cpu(desc->bcd_version) != HID_VERSION) {
++		dev_err(dev, "Unsupported HID version\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static int fill_tch_abs(struct cyttsp5_tch_abs_params *tch_abs, int report_size,
++			int offset)
++{
++	tch_abs->ofs = offset / 8;
++	tch_abs->size = report_size / 8;
++	if (report_size % 8)
++		tch_abs->size += 1;
++	tch_abs->min = 0;
++	tch_abs->max = 1 << report_size;
++	tch_abs->bofs = offset - (tch_abs->ofs << 3);
++
++	return 0;
++}
++
++static irqreturn_t cyttsp5_handle_irq(int irq, void *handle)
++{
++	struct cyttsp5 *ts = handle;
++	int report_id;
++	int size;
++	int error;
++
++	error = cyttsp5_read(ts, ts->input_buf, CY_MAX_INPUT);
++	if (error)
++		return IRQ_HANDLED;
++
++	size = get_unaligned_le16(&ts->input_buf[0]);
++	if (size == 0) {
++		/* reset */
++		report_id = 0;
++		size = 2;
++	} else {
++		report_id = ts->input_buf[2];
++	}
++
++	switch (report_id) {
++	case HID_TOUCH_REPORT_ID:
++		cyttsp5_mt_attention(ts->dev);
++		break;
++	case HID_BTN_REPORT_ID:
++		cyttsp5_btn_attention(ts->dev);
++		break;
++	default:
++		/* It is not an input but a command response */
++		memcpy(ts->response_buf, ts->input_buf, size);
++		complete(&ts->cmd_done);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int cyttsp5_deassert_int(struct cyttsp5 *ts)
++{
++	u16 size;
++	u8 buf[2];
++	int error;
++
++	error = regmap_bulk_read(ts->regmap, HID_INPUT_REG, buf, sizeof(buf));
++	if (error < 0)
++		return error;
++
++	size = get_unaligned_le16(&buf[0]);
++	if (size == 2 || size == 0)
++		return 0;
++
++	return -EINVAL;
++}
++
++static int cyttsp5_fill_all_touch(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++
++	fill_tch_abs(&si->tch_abs[CY_TCH_X], REPORT_SIZE_16,
++		     TOUCH_REPORT_DESC_X);
++	fill_tch_abs(&si->tch_abs[CY_TCH_Y], REPORT_SIZE_16,
++		     TOUCH_REPORT_DESC_Y);
++	fill_tch_abs(&si->tch_abs[CY_TCH_P], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_P);
++	fill_tch_abs(&si->tch_abs[CY_TCH_T], REPORT_SIZE_5,
++		     TOUCH_REPORT_DESC_CONTACTID);
++	fill_tch_abs(&si->tch_hdr, REPORT_SIZE_5,
++		     TOUCH_REPORT_DESC_HDR_CONTACTCOUNT);
++	fill_tch_abs(&si->tch_abs[CY_TCH_MAJ], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_MAJ);
++	fill_tch_abs(&si->tch_abs[CY_TCH_MIN], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_MIN);
++
++	return 0;
++}
++
++static int cyttsp5_startup(struct cyttsp5 *ts)
++{
++	int error;
++
++	error = cyttsp5_deassert_int(ts);
++	if (error) {
++		dev_err(ts->dev, "Error on deassert int r=%d\n", error);
++		return -ENODEV;
++	}
++
++	/*
++	 * Launch the application as the device starts in bootloader mode
++	 * because of a power-on-reset
++	 */
++	error = cyttsp5_hid_output_bl_launch_app(ts);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on launch app r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_get_hid_descriptor(ts, &ts->hid_desc);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on getting HID descriptor r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_fill_all_touch(ts);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on report descriptor r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_hid_output_get_sysinfo(ts);
++	if (error) {
++		dev_err(ts->dev, "Error on getting sysinfo r=%d\n", error);
++		return error;
++	}
++
++	return error;
++}
++
++static void cyttsp5_cleanup(void *data)
++{
++	struct cyttsp5 *ts = data;
++
++	regulator_disable(ts->vdd);
++}
++
++static int cyttsp5_probe(struct device *dev, struct regmap *regmap, int irq,
++			 const char *name)
++{
++	struct cyttsp5 *ts;
++	struct cyttsp5_sysinfo *si;
++	int error, i;
++
++	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++
++	/* Initialize device info */
++	ts->regmap = regmap;
++	ts->dev = dev;
++	si = &ts->sysinfo;
++	dev_set_drvdata(dev, ts);
++
++	init_completion(&ts->cmd_done);
++
++	/* Power up the device */
++	ts->vdd = devm_regulator_get(dev, "vdd");
++	if (IS_ERR(ts->vdd)) {
++		error = PTR_ERR(ts->vdd);
++		return error;
++	}
++
++	error = devm_add_action_or_reset(dev, cyttsp5_cleanup, ts);
++	if (error) {
++		return error;
++	}
++
++	error = regulator_enable(ts->vdd);
++	if (error) {
++		return error;
++	}
++
++	ts->input = devm_input_allocate_device(dev);
++	if (!ts->input) {
++		dev_err(dev, "Error, failed to allocate input device\n");
++		return -ENODEV;
++	}
++
++	ts->input->name = "cyttsp5";
++	scnprintf(ts->phys, sizeof(ts->phys), "%s/input0", dev_name(dev));
++	ts->input->phys = ts->phys;
++	input_set_drvdata(ts->input, ts);
++
++	/* Reset the gpio to be in a reset state */
++	ts->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(ts->reset_gpio)) {
++		error = PTR_ERR(ts->reset_gpio);
++		dev_err(dev, "Failed to request reset gpio, error %d\n", error);
++		return error;
++	}
++	gpiod_set_value(ts->reset_gpio, 0);
++
++	/* Need a delay to have device up */
++	msleep(20);
++
++	error = devm_request_threaded_irq(dev, irq, NULL, cyttsp5_handle_irq,
++				       IRQF_ONESHOT, name, ts);
++	if (error) {
++		dev_err(dev, "unable to request IRQ\n");
++		return error;
++	}
++
++	error = cyttsp5_startup(ts);
++	if (error) {
++		dev_err(ts->dev, "Fail initial startup r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_parse_dt_key_code(dev);
++	if (error < 0) {
++		dev_err(ts->dev, "Error while parsing dts %d\n", error);
++		return error;
++	}
++
++	touchscreen_parse_properties(ts->input, true, &ts->prop);
++
++	__set_bit(EV_KEY, ts->input->evbit);
++	for (i = 0; i < si->num_btns; i++)
++		__set_bit(si->key_code[i], ts->input->keybit);
++
++	return cyttsp5_setup_input_device(dev);
++}
++
++static int cyttsp5_i2c_probe(struct i2c_client *client,
++			     const struct i2c_device_id *id)
++{
++	struct regmap *regmap;
++	static const struct regmap_config config = {
++		.reg_bits = 8,
++		.val_bits = 8,
++	};
++
++	regmap = devm_regmap_init_i2c(client, &config);
++	if (IS_ERR(regmap)) {
++		dev_err(&client->dev, "regmap allocation failed: %ld\n",
++			PTR_ERR(regmap));
++		return PTR_ERR(regmap);
++	}
++
++	return cyttsp5_probe(&client->dev, regmap, client->irq, client->name);
++}
++
++static const struct of_device_id cyttsp5_of_match[] = {
++	{ .compatible = "cypress,tt21000", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cyttsp5_of_match);
++
++static const struct i2c_device_id cyttsp5_i2c_id[] = {
++	{ CYTTSP5_NAME, 0, },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cyttsp5_i2c_id);
++
++static struct i2c_driver cyttsp5_i2c_driver = {
++	.driver = {
++		.name = CYTTSP5_NAME,
++		.of_match_table = cyttsp5_of_match,
++	},
++	.probe = cyttsp5_i2c_probe,
++	.id_table = cyttsp5_i2c_id,
++};
++module_i2c_driver(cyttsp5_i2c_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Touchscreen driver for Cypress TrueTouch Gen 5 Product");
++MODULE_AUTHOR("Mylène Josserand <mylene.josserand@bootlin.com>");
+-- 
+GitLab
+
diff --git a/nongnu/packages/patches/pinenote-touchscreen-2.patch b/nongnu/packages/patches/pinenote-touchscreen-2.patch
new file mode 100644
index 0000000..9ccef92
--- /dev/null
+++ b/nongnu/packages/patches/pinenote-touchscreen-2.patch
@@ -0,0 +1,108 @@
+From d6bb8a6b5a5210fea70bc590350bfca3a9e3a7a2 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 15 Jan 2022 21:50:45 -0500
+Subject: [PATCH] Input: cyttsp5: support touchscreen device tree overrides
+
+It is possible for the cyttsp5 chip to not have a configuration burned
+to it.
+This leads to a sitatuion where all calibration values return zero,
+leading to a broken touchscreen configuration.
+
+The current driver does not support utilizing overrides from the device
+tree.
+Extend the driver to support this, and permit it to do some basic sanity
+checking of the values for the touchscreen and abort if they are
+invalid.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/input/touchscreen/cyttsp5.c | 62 ++++++++++++++++++++++++++---
+ 1 file changed, 57 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp5.c b/drivers/input/touchscreen/cyttsp5.c
+index 3ac45108090c..e837985d199a 100644
+--- a/drivers/input/touchscreen/cyttsp5.c
++++ b/drivers/input/touchscreen/cyttsp5.c
+@@ -507,15 +507,66 @@ static int cyttsp5_get_sysinfo_regs(struct cyttsp5 *ts)
+ 	struct cyttsp5_sensing_conf_data_dev *scd_dev =
+ 		(struct cyttsp5_sensing_conf_data_dev *)
+ 		&ts->response_buf[HID_SYSINFO_SENSING_OFFSET];
++	u32 tmp;
+ 
+ 	cyttsp5_si_get_btn_data(ts);
+ 
+ 	scd->max_tch = scd_dev->max_num_of_tch_per_refresh_cycle;
+-	scd->res_x = get_unaligned_le16(&scd_dev->res_x);
+-	scd->res_y = get_unaligned_le16(&scd_dev->res_y);
+-	scd->max_z = get_unaligned_le16(&scd_dev->max_z);
+-	scd->len_x = get_unaligned_le16(&scd_dev->len_x);
+-	scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++
++	if (scd->max_tch == 0) {
++		dev_dbg(ts->dev, "Max touch points cannot be zero\n");
++		scd->max_tch = 2;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-size-x", &tmp))
++		scd->res_x = get_unaligned_le16(&scd_dev->res_x);
++	else
++		scd->res_x = tmp;
++
++	if (scd->res_x == 0) {
++		dev_err(ts->dev, "ABS_X cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-size-y", &tmp))
++		scd->res_y = get_unaligned_le16(&scd_dev->res_y);
++	else
++		scd->res_y = tmp;
++
++	if (scd->res_y == 0) {
++		dev_err(ts->dev, "ABS_Y cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-max-pressure", &tmp))
++		scd->max_z = get_unaligned_le16(&scd_dev->max_z);
++	else
++		scd->max_z = tmp;
++
++	if (scd->max_z == 0) {
++		dev_err(ts->dev, "ABS_PRESSURE cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-x-mm", &tmp))
++		scd->len_x = get_unaligned_le16(&scd_dev->len_x);
++	else
++		scd->len_x = tmp;
++
++	if (scd->len_x == 0) {
++		dev_dbg(ts->dev, "Touchscreen size x cannot be zero\n");
++		scd->len_x = scd->res_x + 1;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-y-mm", &tmp))
++		scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++	else
++		scd->len_y = tmp;
++
++	if (scd->len_y == 0) {
++		dev_dbg(ts->dev, "Touchscreen size y cannot be zero\n");
++		scd->len_y = scd->res_y + 1;
++	}
+ 
+ 	return 0;
+ }
+@@ -877,6 +928,7 @@ static int cyttsp5_i2c_probe(struct i2c_client *client,
+ 
+ static const struct of_device_id cyttsp5_of_match[] = {
+ 	{ .compatible = "cypress,tt21000", },
++	{ .compatible = "cypress,tma448", },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, cyttsp5_of_match);
+-- 
+GitLab
+
diff --git a/nongnu/packages/patches/pinenote_defconfig.patch b/nongnu/packages/patches/pinenote_defconfig.patch
new file mode 100644
index 0000000..97898a1
--- /dev/null
+++ b/nongnu/packages/patches/pinenote_defconfig.patch
@@ -0,0 +1,48 @@
+diff --git a/arch/arm64/configs/pinenote_defconfig b/arch/arm64/configs/pinenote_defconfig
+index bea435dc92c4..86cdaa92cc2f 100644
+--- a/arch/arm64/configs/pinenote_defconfig
++++ b/arch/arm64/configs/pinenote_defconfig
+@@ -86,6 +86,7 @@ CONFIG_ARCH_ROCKCHIP=y
+ # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
+ # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
+ CONFIG_SCHED_MC=y
++CONFIG_SCHED_SMT=y
+ CONFIG_NR_CPUS=4
+ CONFIG_HZ_1000=y
+ # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+@@ -155,7 +156,7 @@ CONFIG_CGROUP_NET_PRIO=y
+ CONFIG_BT=m
+ CONFIG_BT_RFCOMM=y
+ CONFIG_BT_RFCOMM_TTY=y
+-CONFIG_BT_HIDP=y
++CONFIG_BT_HIDP=m
+ CONFIG_BT_HS=y
+ CONFIG_BT_LEDS=y
+ CONFIG_BT_HCIUART=m
+@@ -223,14 +224,16 @@ CONFIG_BRCMFMAC=m
+ # CONFIG_WLAN_VENDOR_TI is not set
+ # CONFIG_WLAN_VENDOR_ZYDAS is not set
+ # CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=m
+ CONFIG_INPUT_EVDEV=y
+ CONFIG_KEYBOARD_ADC=m
+ # CONFIG_KEYBOARD_ATKBD is not set
+ CONFIG_KEYBOARD_GPIO=y
+-# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_MOUSE=y
+ CONFIG_INPUT_TOUCHSCREEN=y
+ CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+ CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
++CONFIG_TOUCHSCREEN_CYTTSP5=m
+ CONFIG_INPUT_MISC=y
+ CONFIG_INPUT_RK805_PWRKEY=y
+ CONFIG_INPUT_WS8100_PEN=m
+@@ -459,6 +462,8 @@ CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+ CONFIG_SND_SIMPLE_CARD=m
+ CONFIG_HID_BATTERY_STRENGTH=y
+ CONFIG_HIDRAW=y
++CONFIG_UHID=m
++CONFIG_HID_MICROSOFT=y
+ CONFIG_USB_HIDDEV=y
+ CONFIG_I2C_HID_OF=m
+ CONFIG_I2C_HID_OF_GOODIX=m
diff --git a/nongnu/packages/patches/pinephone-0001-bootsplash.patch b/nongnu/packages/patches/pinephone-0001-bootsplash.patch
new file mode 100644
index 0000000..1e259bf
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0001-bootsplash.patch
@@ -0,0 +1,750 @@
+diff --git a/MAINTAINERS b/MAINTAINERS
+index a74227ad082e..b5633b56391e 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3582,6 +3614,18 @@ F:	drivers/net/bonding/
+ F:	include/net/bond*
+ F:	include/uapi/linux/if_bonding.h
+ 
++BOOTSPLASH
++M:	Max Staudt <mstaudt@suse.de>
++L:	linux-fbdev@vger.kernel.org
++S:	Maintained
++F:	Documentation/ABI/testing/sysfs-platform-bootsplash
++F:	Documentation/bootsplash.rst
++F:	drivers/video/fbdev/core/bootsplash*.*
++F:	drivers/video/fbdev/core/dummycon.c
++F:	include/linux/bootsplash.h
++F:	include/uapi/linux/bootsplash_file.h
++F:	tools/bootsplash/*
++
+ BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER
+ M:	Dan Robertson <dan@dlrobertson.com>
+ L:	linux-iio@vger.kernel.org
+diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
+index 7f1f1fbcef9e..f3ff976266fe 100644
+--- a/drivers/video/console/Kconfig
++++ b/drivers/video/console/Kconfig
+@@ -151,6 +151,30 @@ config FRAMEBUFFER_CONSOLE_ROTATION
+          such that other users of the framebuffer will remain normally
+          oriented.
+ 
++config BOOTSPLASH
++	bool "Bootup splash screen"
++	depends on FRAMEBUFFER_CONSOLE
++	help
++	  This option enables the Linux bootsplash screen.
++
++	  The bootsplash is a full-screen logo or animation indicating a
++	  booting system. It replaces the classic scrolling text with a
++	  graphical alternative, similar to other systems.
++
++	  Since this is technically implemented as a hook on top of fbcon,
++	  it can only work if the FRAMEBUFFER_CONSOLE is enabled and a
++	  framebuffer driver is active. Thus, to get a text-free boot,
++	  the system needs to boot with vesafb, efifb, or similar.
++
++	  Once built into the kernel, the bootsplash needs to be enabled
++	  with bootsplash.enabled=1 and a splash file needs to be supplied.
++
++	  Further documentation can be found in:
++	    Documentation/fb/bootsplash.txt
++
++	  If unsure, say N.
++	  This is typically used by distributors and system integrators.
++
+ config STI_CONSOLE
+         bool "STI text console"
+         depends on PARISC
+diff --git a/drivers/video/fbdev/core/Makefile b/drivers/video/fbdev/core/Makefile
+index 73493bbd7a15..66895321928e 100644
+--- a/drivers/video/fbdev/core/Makefile
++++ b/drivers/video/fbdev/core/Makefile
+@@ -29,3 +29,6 @@ obj-$(CONFIG_FB_SYS_IMAGEBLIT) += sysimgblt.o
+ obj-$(CONFIG_FB_SYS_FOPS)      += fb_sys_fops.o
+ obj-$(CONFIG_FB_SVGALIB)       += svgalib.o
+ obj-$(CONFIG_FB_DDC)           += fb_ddc.o
++
++obj-$(CONFIG_BOOTSPLASH)       += bootsplash.o bootsplash_render.o \
++                                  dummyblit.o
+diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
+new file mode 100644
+index 000000000000..e449755af268
+--- /dev/null
++++ b/drivers/video/fbdev/core/bootsplash.c
+@@ -0,0 +1,294 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (Main file: Glue code, workers, timer, PM, kernel and userland API)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#define pr_fmt(fmt) "bootsplash: " fmt
++
++
++#include <linux/atomic.h>
++#include <linux/bootsplash.h>
++#include <linux/console.h>
++#include <linux/device.h> /* dev_warn() */
++#include <linux/fb.h>
++#include <linux/fs.h>
++#include <linux/kernel.h>
++#include <linux/jiffies.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/printk.h>
++#include <linux/selection.h> /* console_blanked */
++#include <linux/stringify.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++#include <linux/vt_kern.h>
++#include <linux/workqueue.h>
++
++#include "bootsplash_internal.h"
++
++
++/*
++ * We only have one splash screen, so let's keep a single
++ * instance of the internal state.
++ */
++static struct splash_priv splash_state;
++
++
++static void splash_callback_redraw_vc(struct work_struct *ignored)
++{
++	if (console_blanked)
++		return;
++
++	console_lock();
++	if (vc_cons[fg_console].d)
++		update_screen(vc_cons[fg_console].d);
++	console_unlock();
++}
++
++
++static bool is_fb_compatible(const struct fb_info *info)
++{
++	if (!(info->flags & FBINFO_BE_MATH)
++	    != !fb_be_math((struct fb_info *)info)) {
++		dev_warn(info->device,
++			 "Can't draw on foreign endianness framebuffer.\n");
++
++		return false;
++	}
++
++	if (info->flags & FBINFO_MISC_TILEBLITTING) {
++		dev_warn(info->device,
++			 "Can't draw splash on tiling framebuffer.\n");
++
++		return false;
++	}
++
++	if (info->fix.type != FB_TYPE_PACKED_PIXELS
++	    || (info->fix.visual != FB_VISUAL_TRUECOLOR
++		&& info->fix.visual != FB_VISUAL_DIRECTCOLOR)) {
++		dev_warn(info->device,
++			 "Can't draw splash on non-packed or non-truecolor framebuffer.\n");
++
++		dev_warn(info->device,
++			 "  type: %u   visual: %u\n",
++			 info->fix.type, info->fix.visual);
++
++		return false;
++	}
++
++	if (info->var.bits_per_pixel != 16
++	    && info->var.bits_per_pixel != 24
++	    && info->var.bits_per_pixel != 32) {
++		dev_warn(info->device,
++			 "We only support drawing on framebuffers with 16, 24, or 32 bpp, not %d.\n",
++			 info->var.bits_per_pixel);
++
++		return false;
++	}
++
++	return true;
++}
++
++
++/*
++ * Called by fbcon_switch() when an instance is activated or refreshed.
++ */
++void bootsplash_render_full(struct fb_info *info)
++{
++	if (!is_fb_compatible(info))
++		return;
++
++	bootsplash_do_render_background(info);
++}
++
++
++/*
++ * External status enquiry and on/off switch
++ */
++bool bootsplash_would_render_now(void)
++{
++	return !oops_in_progress
++		&& !console_blanked
++		&& bootsplash_is_enabled();
++}
++
++bool bootsplash_is_enabled(void)
++{
++	bool was_enabled;
++
++	/* Make sure we have the newest state */
++	smp_rmb();
++
++	was_enabled = test_bit(0, &splash_state.enabled);
++
++	return was_enabled;
++}
++
++void bootsplash_disable(void)
++{
++	int was_enabled;
++
++	was_enabled = test_and_clear_bit(0, &splash_state.enabled);
++
++	if (was_enabled) {
++		if (oops_in_progress) {
++			/* Redraw screen now so we can see a panic */
++			if (vc_cons[fg_console].d)
++				update_screen(vc_cons[fg_console].d);
++		} else {
++			/* No urgency, redraw at next opportunity */
++			schedule_work(&splash_state.work_redraw_vc);
++		}
++	}
++}
++
++void bootsplash_enable(void)
++{
++	bool was_enabled;
++
++	if (oops_in_progress)
++		return;
++
++	was_enabled = test_and_set_bit(0, &splash_state.enabled);
++
++	if (!was_enabled)
++		schedule_work(&splash_state.work_redraw_vc);
++}
++
++
++/*
++ * Userland API via platform device in sysfs
++ */
++static ssize_t splash_show_enabled(struct device *dev,
++				   struct device_attribute *attr, char *buf)
++{
++	return sprintf(buf, "%d\n", bootsplash_is_enabled());
++}
++
++static ssize_t splash_store_enabled(struct device *device,
++				    struct device_attribute *attr,
++				    const char *buf, size_t count)
++{
++	bool enable;
++	int err;
++
++	if (!buf || !count)
++		return -EFAULT;
++
++	err = kstrtobool(buf, &enable);
++	if (err)
++		return err;
++
++	if (enable)
++		bootsplash_enable();
++	else
++		bootsplash_disable();
++
++	return count;
++}
++
++static DEVICE_ATTR(enabled, 0644, splash_show_enabled, splash_store_enabled);
++
++
++static struct attribute *splash_dev_attrs[] = {
++	&dev_attr_enabled.attr,
++	NULL
++};
++
++ATTRIBUTE_GROUPS(splash_dev);
++
++
++
++
++/*
++ * Power management fixup via platform device
++ *
++ * When the system is woken from sleep or restored after hibernating, we
++ * cannot expect the screen contents to still be present in video RAM.
++ * Thus, we have to redraw the splash if we're currently active.
++ */
++static int splash_resume(struct device *device)
++{
++	if (bootsplash_would_render_now())
++		schedule_work(&splash_state.work_redraw_vc);
++
++	return 0;
++}
++
++static int splash_suspend(struct device *device)
++{
++	cancel_work_sync(&splash_state.work_redraw_vc);
++
++	return 0;
++}
++
++
++static const struct dev_pm_ops splash_pm_ops = {
++	.thaw = splash_resume,
++	.restore = splash_resume,
++	.resume = splash_resume,
++	.suspend = splash_suspend,
++	.freeze = splash_suspend,
++};
++
++static struct platform_driver splash_driver = {
++	.driver = {
++		.name = "bootsplash",
++		.pm = &splash_pm_ops,
++	},
++};
++
++
++/*
++ * Main init
++ */
++void bootsplash_init(void)
++{
++	int ret;
++
++	/* Initialized already? */
++	if (splash_state.splash_device)
++		return;
++
++
++	/* Register platform device to export user API */
++	ret = platform_driver_register(&splash_driver);
++	if (ret) {
++		pr_err("platform_driver_register() failed: %d\n", ret);
++		goto err;
++	}
++
++	splash_state.splash_device
++		= platform_device_alloc("bootsplash", 0);
++
++	if (!splash_state.splash_device)
++		goto err_driver;
++
++	splash_state.splash_device->dev.groups = splash_dev_groups;
++
++	ret = platform_device_add(splash_state.splash_device);
++	if (ret) {
++		pr_err("platform_device_add() failed: %d\n", ret);
++		goto err_device;
++	}
++
++
++	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
++
++	return;
++
++err_device:
++	platform_device_put(splash_state.splash_device);
++	splash_state.splash_device = NULL;
++err_driver:
++	platform_driver_unregister(&splash_driver);
++err:
++	pr_err("Failed to initialize.\n");
++}
+diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
+new file mode 100644
+index 000000000000..b11da5cb90bf
+--- /dev/null
++++ b/drivers/video/fbdev/core/bootsplash_internal.h
+@@ -0,0 +1,55 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (Internal data structures used at runtime)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#ifndef __BOOTSPLASH_INTERNAL_H
++#define __BOOTSPLASH_INTERNAL_H
++
++
++#include <linux/types.h>
++#include <linux/fb.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/spinlock.h>
++
++
++/*
++ * Runtime types
++ */
++struct splash_priv {
++	/*
++	 * Enabled/disabled state, to be used with atomic bit operations.
++	 *   Bit 0: 0 = Splash hidden
++	 *          1 = Splash shown
++	 *
++	 * Note: fbcon.c uses this twice, by calling
++	 *       bootsplash_would_render_now() in set_blitting_type() and
++	 *       in fbcon_switch().
++	 *       This is racy, but eventually consistent: Turning the
++	 *       splash on/off will cause a redraw, which calls
++	 *       fbcon_switch(), which calls set_blitting_type().
++	 *       So the last on/off toggle will make things consistent.
++	 */
++	unsigned long enabled;
++
++	/* Our gateway to userland via sysfs */
++	struct platform_device *splash_device;
++
++	struct work_struct work_redraw_vc;
++};
++
++
++
++/*
++ * Rendering functions
++ */
++void bootsplash_do_render_background(struct fb_info *info);
++
++#endif
+diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
+new file mode 100644
+index 000000000000..4d7e0117f653
+--- /dev/null
++++ b/drivers/video/fbdev/core/bootsplash_render.c
+@@ -0,0 +1,93 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (Rendering functions)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#define pr_fmt(fmt) "bootsplash: " fmt
++
++
++#include <linux/bootsplash.h>
++#include <linux/fb.h>
++#include <linux/kernel.h>
++#include <linux/printk.h>
++#include <linux/types.h>
++
++#include "bootsplash_internal.h"
++
++
++
++
++/*
++ * Rendering: Internal drawing routines
++ */
++
++
++/*
++ * Pack pixel into target format and do Big/Little Endian handling.
++ * This would be a good place to handle endianness conversion if necessary.
++ */
++static inline u32 pack_pixel(const struct fb_var_screeninfo *dst_var,
++			     u8 red, u8 green, u8 blue)
++{
++	u32 dstpix;
++
++	/* Quantize pixel */
++	red = red >> (8 - dst_var->red.length);
++	green = green >> (8 - dst_var->green.length);
++	blue = blue >> (8 - dst_var->blue.length);
++
++	/* Pack pixel */
++	dstpix = red << (dst_var->red.offset)
++		| green << (dst_var->green.offset)
++		| blue << (dst_var->blue.offset);
++
++	/*
++	 * Move packed pixel to the beginning of the memory cell,
++	 * so we can memcpy() it out easily
++	 */
++#ifdef __BIG_ENDIAN
++	switch (dst_var->bits_per_pixel) {
++	case 16:
++		dstpix <<= 16;
++		break;
++	case 24:
++		dstpix <<= 8;
++		break;
++	case 32:
++		break;
++	}
++#else
++	/* This is intrinsically unnecessary on Little Endian */
++#endif
++
++	return dstpix;
++}
++
++
++void bootsplash_do_render_background(struct fb_info *info)
++{
++	unsigned int x, y;
++	u32 dstpix;
++	u32 dst_octpp = info->var.bits_per_pixel / 8;
++
++	dstpix = pack_pixel(&info->var,
++			    0,
++			    0,
++			    0);
++
++	for (y = 0; y < info->var.yres_virtual; y++) {
++		u8 *dstline = info->screen_buffer + (y * info->fix.line_length);
++
++		for (x = 0; x < info->var.xres_virtual; x++) {
++			memcpy(dstline, &dstpix, dst_octpp);
++
++			dstline += dst_octpp;
++		}
++	}
++}
+diff --git a/drivers/video/fbdev/core/dummyblit.c b/drivers/video/fbdev/core/dummyblit.c
+new file mode 100644
+index 000000000000..8c22ff92ce24
+--- /dev/null
++++ b/drivers/video/fbdev/core/dummyblit.c
+@@ -0,0 +1,89 @@
++/*
++ *  linux/drivers/video/fbdev/core/dummyblit.c -- Dummy Blitting Operation
++ *
++ *  Authors:
++ *  Max Staudt <mstaudt@suse.de>
++ *
++ *  These functions are used in place of blitblit/tileblit to suppress
++ *  fbcon's text output while a splash is shown.
++ *
++ *  Only suppressing actual rendering keeps the text buffer in the VC layer
++ *  intact and makes it easy to switch back from the bootsplash to a full
++ *  text console with a simple redraw (with the original functions in place).
++ *
++ *  Based on linux/drivers/video/fbdev/core/bitblit.c
++ *       and linux/drivers/video/fbdev/core/tileblit.c
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#include <linux/module.h>
++#include <linux/fb.h>
++#include <linux/vt_kern.h>
++#include <linux/console.h>
++#include <asm/types.h>
++#include "fbcon.h"
++
++static void dummy_bmove(struct vc_data *vc, struct fb_info *info, int sy,
++			int sx, int dy, int dx, int height, int width)
++{
++	;
++}
++
++static void dummy_clear(struct vc_data *vc, struct fb_info *info, int sy,
++			int sx, int height, int width)
++{
++	;
++}
++
++static void dummy_putcs(struct vc_data *vc, struct fb_info *info,
++			const unsigned short *s, int count, int yy, int xx,
++			int fg, int bg)
++{
++	;
++}
++
++static void dummy_clear_margins(struct vc_data *vc, struct fb_info *info,
++				int color, int bottom_only)
++{
++	;
++}
++
++static void dummy_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++			int softback_lines, int fg, int bg)
++{
++	;
++}
++
++static int dummy_update_start(struct fb_info *info)
++{
++	/*
++	 * Copied from bitblit.c and tileblit.c
++	 *
++	 * As of Linux 4.12, nobody seems to care about our return value.
++	 */
++	struct fbcon_ops *ops = info->fbcon_par;
++	int err;
++
++	err = fb_pan_display(info, &ops->var);
++	ops->var.xoffset = info->var.xoffset;
++	ops->var.yoffset = info->var.yoffset;
++	ops->var.vmode = info->var.vmode;
++	return err;
++}
++
++void fbcon_set_dummyops(struct fbcon_ops *ops)
++{
++	ops->bmove = dummy_bmove;
++	ops->clear = dummy_clear;
++	ops->putcs = dummy_putcs;
++	ops->clear_margins = dummy_clear_margins;
++	ops->cursor = dummy_cursor;
++	ops->update_start = dummy_update_start;
++	ops->rotate_font = NULL;
++}
++EXPORT_SYMBOL_GPL(fbcon_set_dummyops);
++
++MODULE_AUTHOR("Max Staudt <mstaudt@suse.de>");
++MODULE_DESCRIPTION("Dummy Blitting Operation");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
+index 04612f938bab..9a39a6fcfe98 100644
+--- a/drivers/video/fbdev/core/fbcon.c
++++ b/drivers/video/fbdev/core/fbcon.c
+@@ -80,6 +80,7 @@
+ #include <asm/irq.h>
+ 
+ #include "fbcon.h"
++#include <linux/bootsplash.h>
+ 
+ #ifdef FBCONDEBUG
+ #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
+@@ -542,6 +543,8 @@ static int do_fbcon_takeover(int show_logo)
+ 	for (i = first_fb_vc; i <= last_fb_vc; i++)
+ 		con2fb_map[i] = info_idx;
+ 
++	bootsplash_init();
++
+ 	err = do_take_over_console(&fb_con, first_fb_vc, last_fb_vc,
+ 				fbcon_is_default);
+ 
+@@ -661,6 +664,9 @@ static void set_blitting_type(struct vc_data *vc, struct fb_info *info)
+ 	else {
+ 		fbcon_set_rotation(info);
+ 		fbcon_set_bitops(ops);
++
++		if (bootsplash_would_render_now())
++			fbcon_set_dummyops(ops);
+ 	}
+ }
+ 
+@@ -683,6 +689,19 @@ static void set_blitting_type(struct vc_data *vc, struct fb_info *info)
+ 	ops->p = &fb_display[vc->vc_num];
+ 	fbcon_set_rotation(info);
+ 	fbcon_set_bitops(ops);
++
++	/*
++	 * Note:
++	 * This is *eventually correct*.
++	 * Setting the fbcon operations and drawing the splash happen at
++	 * different points in time. If the splash is enabled/disabled
++	 * in between, then bootsplash_{en,dis}able will schedule a
++	 * redraw, which will again render the splash (or not) and set
++	 * the correct fbcon ops.
++	 * The last run will then be the right one.
++	 */
++	if (bootsplash_would_render_now())
++		fbcon_set_dummyops(ops);
+ }
+ 
+ static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount)
+@@ -2184,6 +2203,9 @@ static int fbcon_switch(struct vc_data *vc)
+ 	info = registered_fb[con2fb_map[vc->vc_num]];
+ 	ops = info->fbcon_par;
+ 
++	if (bootsplash_would_render_now())
++		bootsplash_render_full(info);
++
+ 	if (softback_top) {
+ 		if (softback_lines)
+ 			fbcon_set_origin(vc);
+diff --git a/drivers/video/fbdev/core/fbcon.h b/drivers/video/fbdev/core/fbcon.h
+index 18f3ac144237..45f94347fe5e 100644
+--- a/drivers/video/fbdev/core/fbcon.h
++++ b/drivers/video/fbdev/core/fbcon.h
+@@ -214,6 +214,11 @@ static inline int attr_col_ec(int shift, struct vc_data *vc,
+ #define SCROLL_REDRAW	   0x004
+ #define SCROLL_PAN_REDRAW  0x005
+ 
++#ifdef CONFIG_BOOTSPLASH
++extern void fbcon_set_dummyops(struct fbcon_ops *ops);
++#else /* CONFIG_BOOTSPLASH */
++#define fbcon_set_dummyops(x)
++#endif /* CONFIG_BOOTSPLASH */
+ #ifdef CONFIG_FB_TILEBLITTING
+ extern void fbcon_set_tileops(struct vc_data *vc, struct fb_info *info);
+ #endif
+diff --git a/include/linux/bootsplash.h b/include/linux/bootsplash.h
+new file mode 100644
+index 000000000000..c6dd0b43180d
+--- /dev/null
++++ b/include/linux/bootsplash.h
+@@ -0,0 +1,43 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#ifndef __LINUX_BOOTSPLASH_H
++#define __LINUX_BOOTSPLASH_H
++
++#include <linux/fb.h>
++
++
++#ifdef CONFIG_BOOTSPLASH
++
++extern void bootsplash_render_full(struct fb_info *info);
++
++extern bool bootsplash_would_render_now(void);
++
++extern bool bootsplash_is_enabled(void);
++extern void bootsplash_disable(void);
++extern void bootsplash_enable(void);
++
++extern void bootsplash_init(void);
++
++#else /* CONFIG_BOOTSPLASH */
++
++#define bootsplash_render_full(x)
++
++#define bootsplash_would_render_now() (false)
++
++#define bootsplash_is_enabled() (false)
++#define bootsplash_disable()
++#define bootsplash_enable()
++
++#define bootsplash_init()
++
++#endif /* CONFIG_BOOTSPLASH */
++
++
++#endif
diff --git a/nongnu/packages/patches/pinephone-0002-bootsplash.patch b/nongnu/packages/patches/pinephone-0002-bootsplash.patch
new file mode 100644
index 0000000..e8d4cc8
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0002-bootsplash.patch
@@ -0,0 +1,657 @@
+diff --git a/drivers/video/fbdev/core/Makefile b/drivers/video/fbdev/core/Makefile
+index 66895321928e..6a8d1bab8a01 100644
+--- a/drivers/video/fbdev/core/Makefile
++++ b/drivers/video/fbdev/core/Makefile
+@@ -31,4 +31,4 @@ obj-$(CONFIG_FB_SVGALIB)       += svgalib.o
+ obj-$(CONFIG_FB_DDC)           += fb_ddc.o
+ 
+ obj-$(CONFIG_BOOTSPLASH)       += bootsplash.o bootsplash_render.o \
+-                                  dummyblit.o
++                                  bootsplash_load.o dummyblit.o
+diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
+index e449755af268..843c5400fefc 100644
+--- a/drivers/video/fbdev/core/bootsplash.c
++++ b/drivers/video/fbdev/core/bootsplash.c
+@@ -32,6 +32,7 @@
+ #include <linux/workqueue.h>
+ 
+ #include "bootsplash_internal.h"
++#include "uapi/linux/bootsplash_file.h"
+ 
+ 
+ /*
+@@ -102,10 +103,17 @@ static bool is_fb_compatible(const struct fb_info *info)
+  */
+ void bootsplash_render_full(struct fb_info *info)
+ {
++	mutex_lock(&splash_state.data_lock);
++
+ 	if (!is_fb_compatible(info))
+-		return;
++		goto out;
++
++	bootsplash_do_render_background(info, splash_state.file);
++
++	bootsplash_do_render_pictures(info, splash_state.file);
+ 
+-	bootsplash_do_render_background(info);
++out:
++	mutex_unlock(&splash_state.data_lock);
+ }
+ 
+ 
+@@ -116,6 +124,7 @@ bool bootsplash_would_render_now(void)
+ {
+ 	return !oops_in_progress
+ 		&& !console_blanked
++		&& splash_state.file
+ 		&& bootsplash_is_enabled();
+ }
+ 
+@@ -252,6 +261,7 @@ static struct platform_driver splash_driver = {
+ void bootsplash_init(void)
+ {
+ 	int ret;
++	struct splash_file_priv *fp;
+ 
+ 	/* Initialized already? */
+ 	if (splash_state.splash_device)
+@@ -280,8 +290,26 @@ void bootsplash_init(void)
+ 	}
+ 
+ 
++	mutex_init(&splash_state.data_lock);
++	set_bit(0, &splash_state.enabled);
++
+ 	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
+ 
++
++	if (!splash_state.bootfile || !strlen(splash_state.bootfile))
++		return;
++
++	fp = bootsplash_load_firmware(&splash_state.splash_device->dev,
++				      splash_state.bootfile);
++
++	if (!fp)
++		goto err;
++
++	mutex_lock(&splash_state.data_lock);
++	splash_state.splash_fb = NULL;
++	splash_state.file = fp;
++	mutex_unlock(&splash_state.data_lock);
++
+ 	return;
+ 
+ err_device:
+@@ -292,3 +320,7 @@ void bootsplash_init(void)
+ err:
+ 	pr_err("Failed to initialize.\n");
+ }
++
++
++module_param_named(bootfile, splash_state.bootfile, charp, 0444);
++MODULE_PARM_DESC(bootfile, "Bootsplash file to load on boot");
+diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
+index b11da5cb90bf..71e2a27ac0b8 100644
+--- a/drivers/video/fbdev/core/bootsplash_internal.h
++++ b/drivers/video/fbdev/core/bootsplash_internal.h
+@@ -15,15 +15,43 @@
+ 
+ #include <linux/types.h>
+ #include <linux/fb.h>
++#include <linux/firmware.h>
+ #include <linux/kernel.h>
+ #include <linux/mutex.h>
+ #include <linux/spinlock.h>
+ 
++#include "uapi/linux/bootsplash_file.h"
++
+ 
+ /*
+  * Runtime types
+  */
++struct splash_blob_priv {
++	struct splash_blob_header *blob_header;
++	const void *data;
++};
++
++
++struct splash_pic_priv {
++	const struct splash_pic_header *pic_header;
++
++	struct splash_blob_priv *blobs;
++	u16 blobs_loaded;
++};
++
++
++struct splash_file_priv {
++	const struct firmware *fw;
++	const struct splash_file_header *header;
++
++	struct splash_pic_priv *pics;
++};
++
++
+ struct splash_priv {
++	/* Bootup and runtime state */
++	char *bootfile;
++
+ 	/*
+ 	 * Enabled/disabled state, to be used with atomic bit operations.
+ 	 *   Bit 0: 0 = Splash hidden
+@@ -43,6 +71,13 @@ struct splash_priv {
+ 	struct platform_device *splash_device;
+ 
+ 	struct work_struct work_redraw_vc;
++
++	/* Splash data structures including lock for everything below */
++	struct mutex data_lock;
++
++	struct fb_info *splash_fb;
++
++	struct splash_file_priv *file;
+ };
+ 
+ 
+@@ -50,6 +85,14 @@ struct splash_priv {
+ /*
+  * Rendering functions
+  */
+-void bootsplash_do_render_background(struct fb_info *info);
++void bootsplash_do_render_background(struct fb_info *info,
++				     const struct splash_file_priv *fp);
++void bootsplash_do_render_pictures(struct fb_info *info,
++				   const struct splash_file_priv *fp);
++
++
++void bootsplash_free_file(struct splash_file_priv *fp);
++struct splash_file_priv *bootsplash_load_firmware(struct device *device,
++						  const char *path);
+ 
+ #endif
+diff --git a/drivers/video/fbdev/core/bootsplash_load.c b/drivers/video/fbdev/core/bootsplash_load.c
+new file mode 100644
+index 000000000000..fd807571ab7d
+--- /dev/null
++++ b/drivers/video/fbdev/core/bootsplash_load.c
+@@ -0,0 +1,225 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (Loading and freeing functions)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#define pr_fmt(fmt) "bootsplash: " fmt
++
++
++#include <linux/bootsplash.h>
++#include <linux/fb.h>
++#include <linux/firmware.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/printk.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++
++#include "bootsplash_internal.h"
++#include "uapi/linux/bootsplash_file.h"
++
++
++
++
++/*
++ * Free all vmalloc()'d resources describing a splash file.
++ */
++void bootsplash_free_file(struct splash_file_priv *fp)
++{
++	if (!fp)
++		return;
++
++	if (fp->pics) {
++		unsigned int i;
++
++		for (i = 0; i < fp->header->num_pics; i++) {
++			struct splash_pic_priv *pp = &fp->pics[i];
++
++			if (pp->blobs)
++				vfree(pp->blobs);
++		}
++
++		vfree(fp->pics);
++	}
++
++	release_firmware(fp->fw);
++	vfree(fp);
++}
++
++
++
++
++/*
++ * Load a splash screen from a "firmware" file.
++ *
++ * Parsing, and sanity checks.
++ */
++#ifdef __BIG_ENDIAN
++	#define BOOTSPLASH_MAGIC BOOTSPLASH_MAGIC_BE
++#else
++	#define BOOTSPLASH_MAGIC BOOTSPLASH_MAGIC_LE
++#endif
++
++struct splash_file_priv *bootsplash_load_firmware(struct device *device,
++						  const char *path)
++{
++	const struct firmware *fw;
++	struct splash_file_priv *fp;
++	unsigned int i;
++	const u8 *walker;
++
++	if (request_firmware(&fw, path, device))
++		return NULL;
++
++	if (fw->size < sizeof(struct splash_file_header)
++	    || memcmp(fw->data, BOOTSPLASH_MAGIC, sizeof(fp->header->id))) {
++		pr_err("Not a bootsplash file.\n");
++
++		release_firmware(fw);
++		return NULL;
++	}
++
++	fp = vzalloc(sizeof(struct splash_file_priv));
++	if (!fp) {
++		release_firmware(fw);
++		return NULL;
++	}
++
++	pr_info("Loading splash file (%li bytes)\n", fw->size);
++
++	fp->fw = fw;
++	fp->header = (struct splash_file_header *)fw->data;
++
++	/* Sanity checks */
++	if (fp->header->version != BOOTSPLASH_VERSION) {
++		pr_err("Loaded v%d file, but we only support version %d\n",
++			fp->header->version,
++			BOOTSPLASH_VERSION);
++
++		goto err;
++	}
++
++	if (fw->size < sizeof(struct splash_file_header)
++		+ fp->header->num_pics
++			* sizeof(struct splash_pic_header)
++		+ fp->header->num_blobs
++			* sizeof(struct splash_blob_header)) {
++		pr_err("File incomplete.\n");
++
++		goto err;
++	}
++
++	/* Read picture headers */
++	if (fp->header->num_pics) {
++		fp->pics = vzalloc(fp->header->num_pics
++				   * sizeof(struct splash_pic_priv));
++		if (!fp->pics)
++			goto err;
++	}
++
++	walker = fw->data + sizeof(struct splash_file_header);
++	for (i = 0; i < fp->header->num_pics; i++) {
++		struct splash_pic_priv *pp = &fp->pics[i];
++		struct splash_pic_header *ph = (void *)walker;
++
++		pr_debug("Picture %u: Size %ux%u\n", i, ph->width, ph->height);
++
++		if (ph->num_blobs < 1) {
++			pr_err("Picture %u: Zero blobs? Aborting load.\n", i);
++			goto err;
++		}
++
++		pp->pic_header = ph;
++		pp->blobs = vzalloc(ph->num_blobs
++					* sizeof(struct splash_blob_priv));
++		if (!pp->blobs)
++			goto err;
++
++		walker += sizeof(struct splash_pic_header);
++	}
++
++	/* Read blob headers */
++	for (i = 0; i < fp->header->num_blobs; i++) {
++		struct splash_blob_header *bh = (void *)walker;
++		struct splash_pic_priv *pp;
++
++		if (walker + sizeof(struct splash_blob_header)
++		    > fw->data + fw->size)
++			goto err;
++
++		walker += sizeof(struct splash_blob_header);
++
++		if (walker + bh->length > fw->data + fw->size)
++			goto err;
++
++		if (bh->picture_id >= fp->header->num_pics)
++			goto nextblob;
++
++		pp = &fp->pics[bh->picture_id];
++
++		pr_debug("Blob %u, pic %u, blobs_loaded %u, num_blobs %u.\n",
++			 i, bh->picture_id,
++			 pp->blobs_loaded, pp->pic_header->num_blobs);
++
++		if (pp->blobs_loaded >= pp->pic_header->num_blobs)
++			goto nextblob;
++
++		switch (bh->type) {
++		case 0:
++			/* Raw 24-bit packed pixels */
++			if (bh->length != pp->pic_header->width
++					* pp->pic_header->height * 3) {
++				pr_err("Blob %u, type 1: Length doesn't match picture.\n",
++				       i);
++
++				goto err;
++			}
++			break;
++		default:
++			pr_warn("Blob %u, unknown type %u.\n", i, bh->type);
++			goto nextblob;
++		}
++
++		pp->blobs[pp->blobs_loaded].blob_header = bh;
++		pp->blobs[pp->blobs_loaded].data = walker;
++		pp->blobs_loaded++;
++
++nextblob:
++		walker += bh->length;
++		if (bh->length % 16)
++			walker += 16 - (bh->length % 16);
++	}
++
++	if (walker != fw->data + fw->size)
++		pr_warn("Trailing data in splash file.\n");
++
++	/* Walk over pictures and ensure all blob slots are filled */
++	for (i = 0; i < fp->header->num_pics; i++) {
++		struct splash_pic_priv *pp = &fp->pics[i];
++
++		if (pp->blobs_loaded != pp->pic_header->num_blobs) {
++			pr_err("Picture %u doesn't have all blob slots filled.\n",
++			       i);
++
++			goto err;
++		}
++	}
++
++	pr_info("Loaded (%ld bytes, %u pics, %u blobs).\n",
++		fw->size,
++		fp->header->num_pics,
++		fp->header->num_blobs);
++
++	return fp;
++
++
++err:
++	bootsplash_free_file(fp);
++	return NULL;
++}
+diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
+index 4d7e0117f653..2ae36949d0e3 100644
+--- a/drivers/video/fbdev/core/bootsplash_render.c
++++ b/drivers/video/fbdev/core/bootsplash_render.c
+@@ -19,6 +19,7 @@
+ #include <linux/types.h>
+ 
+ #include "bootsplash_internal.h"
++#include "uapi/linux/bootsplash_file.h"
+ 
+ 
+ 
+@@ -70,16 +71,69 @@ static inline u32 pack_pixel(const struct fb_var_screeninfo *dst_var,
+ }
+ 
+ 
+-void bootsplash_do_render_background(struct fb_info *info)
++/*
++ * Copy from source and blend into the destination picture.
++ * Currently assumes that the source picture is 24bpp.
++ * Currently assumes that the destination is <= 32bpp.
++ */
++static int splash_convert_to_fb(u8 *dst,
++				const struct fb_var_screeninfo *dst_var,
++				unsigned int dst_stride,
++				unsigned int dst_xoff,
++				unsigned int dst_yoff,
++				const u8 *src,
++				unsigned int src_width,
++				unsigned int src_height)
++{
++	unsigned int x, y;
++	unsigned int src_stride = 3 * src_width; /* Assume 24bpp packed */
++	u32 dst_octpp = dst_var->bits_per_pixel / 8;
++
++	dst_xoff += dst_var->xoffset;
++	dst_yoff += dst_var->yoffset;
++
++	/* Copy with stride and pixel size adjustment */
++	for (y = 0;
++	     y < src_height && y + dst_yoff < dst_var->yres_virtual;
++	     y++) {
++		const u8 *srcline = src + (y * src_stride);
++		u8 *dstline = dst + ((y + dst_yoff) * dst_stride)
++				  + (dst_xoff * dst_octpp);
++
++		for (x = 0;
++		     x < src_width && x + dst_xoff < dst_var->xres_virtual;
++		     x++) {
++			u8 red, green, blue;
++			u32 dstpix;
++
++			/* Read pixel */
++			red = *srcline++;
++			green = *srcline++;
++			blue = *srcline++;
++
++			/* Write pixel */
++			dstpix = pack_pixel(dst_var, red, green, blue);
++			memcpy(dstline, &dstpix, dst_octpp);
++
++			dstline += dst_octpp;
++		}
++	}
++
++	return 0;
++}
++
++
++void bootsplash_do_render_background(struct fb_info *info,
++				     const struct splash_file_priv *fp)
+ {
+ 	unsigned int x, y;
+ 	u32 dstpix;
+ 	u32 dst_octpp = info->var.bits_per_pixel / 8;
+ 
+ 	dstpix = pack_pixel(&info->var,
+-			    0,
+-			    0,
+-			    0);
++			    fp->header->bg_red,
++			    fp->header->bg_green,
++			    fp->header->bg_blue);
+ 
+ 	for (y = 0; y < info->var.yres_virtual; y++) {
+ 		u8 *dstline = info->screen_buffer + (y * info->fix.line_length);
+@@ -91,3 +145,44 @@ void bootsplash_do_render_background(struct fb_info *info)
+ 		}
+ 	}
+ }
++
++
++void bootsplash_do_render_pictures(struct fb_info *info,
++				   const struct splash_file_priv *fp)
++{
++	unsigned int i;
++
++	for (i = 0; i < fp->header->num_pics; i++) {
++		struct splash_blob_priv *bp;
++		struct splash_pic_priv *pp = &fp->pics[i];
++		long dst_xoff, dst_yoff;
++
++		if (pp->blobs_loaded < 1)
++			continue;
++
++		bp = &pp->blobs[0];
++
++		if (!bp || bp->blob_header->type != 0)
++			continue;
++
++		dst_xoff = (info->var.xres - pp->pic_header->width) / 2;
++		dst_yoff = (info->var.yres - pp->pic_header->height) / 2;
++
++		if (dst_xoff < 0
++		    || dst_yoff < 0
++		    || dst_xoff + pp->pic_header->width > info->var.xres
++		    || dst_yoff + pp->pic_header->height > info->var.yres) {
++			pr_info_once("Picture %u is out of bounds at current resolution: %dx%d\n"
++				     "(this will only be printed once every reboot)\n",
++				     i, info->var.xres, info->var.yres);
++
++			continue;
++		}
++
++		/* Draw next splash frame */
++		splash_convert_to_fb(info->screen_buffer, &info->var,
++				info->fix.line_length, dst_xoff, dst_yoff,
++				bp->data,
++				pp->pic_header->width, pp->pic_header->height);
++	}
++}
+diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
+new file mode 100644
+index 000000000000..89dc9cca8f0c
+--- /dev/null
++++ b/include/uapi/linux/bootsplash_file.h
+@@ -0,0 +1,118 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (File format)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
++ */
++
++#ifndef __BOOTSPLASH_FILE_H
++#define __BOOTSPLASH_FILE_H
++
++
++#define BOOTSPLASH_VERSION 55561
++
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++
++
++/*
++ * On-disk types
++ *
++ * A splash file consists of:
++ *  - One single 'struct splash_file_header'
++ *  - An array of 'struct splash_pic_header'
++ *  - An array of raw data blocks, each padded to 16 bytes and
++ *    preceded by a 'struct splash_blob_header'
++ *
++ * A single-frame splash may look like this:
++ *
++ * +--------------------+
++ * |                    |
++ * | splash_file_header |
++ * |  -> num_blobs = 1  |
++ * |  -> num_pics = 1   |
++ * |                    |
++ * +--------------------+
++ * |                    |
++ * | splash_pic_header  |
++ * |                    |
++ * +--------------------+
++ * |                    |
++ * | splash_blob_header |
++ * |  -> type = 0       |
++ * |  -> picture_id = 0 |
++ * |                    |
++ * | (raw RGB data)     |
++ * | (pad to 16 bytes)  |
++ * |                    |
++ * +--------------------+
++ *
++ * All multi-byte values are stored on disk in the native format
++ * expected by the system the file will be used on.
++ */
++#define BOOTSPLASH_MAGIC_BE "Linux bootsplash"
++#define BOOTSPLASH_MAGIC_LE "hsalpstoob xuniL"
++
++struct splash_file_header {
++	uint8_t  id[16]; /* "Linux bootsplash" (no trailing NUL) */
++
++	/* Splash file format version to avoid clashes */
++	uint16_t version;
++
++	/* The background color */
++	uint8_t bg_red;
++	uint8_t bg_green;
++	uint8_t bg_blue;
++	uint8_t bg_reserved;
++
++	/*
++	 * Number of pic/blobs so we can allocate memory for internal
++	 * structures ahead of time when reading the file
++	 */
++	uint16_t num_blobs;
++	uint8_t num_pics;
++
++	uint8_t padding[103];
++} __attribute__((__packed__));
++
++
++struct splash_pic_header {
++	uint16_t width;
++	uint16_t height;
++
++	/*
++	 * Number of data packages associated with this picture.
++	 * Currently, the only use for more than 1 is for animations.
++	 */
++	uint8_t num_blobs;
++
++	uint8_t padding[27];
++} __attribute__((__packed__));
++
++
++struct splash_blob_header {
++	/* Length of the data block in bytes. */
++	uint32_t length;
++
++	/*
++	 * Type of the contents.
++	 *  0 - Raw RGB data.
++	 */
++	uint16_t type;
++
++	/*
++	 * Picture this blob is associated with.
++	 * Blobs will be added to a picture in the order they are
++	 * found in the file.
++	 */
++	uint8_t picture_id;
++
++	uint8_t padding[9];
++} __attribute__((__packed__));
++
++#endif
diff --git a/nongnu/packages/patches/pinephone-0003-bootsplash.patch b/nongnu/packages/patches/pinephone-0003-bootsplash.patch
new file mode 100644
index 0000000..2169537
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0003-bootsplash.patch
@@ -0,0 +1,66 @@
+diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
+index 843c5400fefc..815b007f81ca 100644
+--- a/drivers/video/fbdev/core/bootsplash.c
++++ b/drivers/video/fbdev/core/bootsplash.c
+@@ -112,6 +112,8 @@ void bootsplash_render_full(struct fb_info *info)
+ 
+ 	bootsplash_do_render_pictures(info, splash_state.file);
+ 
++	bootsplash_do_render_flush(info);
++
+ out:
+ 	mutex_unlock(&splash_state.data_lock);
+ }
+diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
+index 71e2a27ac0b8..0acb383aa4e3 100644
+--- a/drivers/video/fbdev/core/bootsplash_internal.h
++++ b/drivers/video/fbdev/core/bootsplash_internal.h
+@@ -89,6 +89,7 @@ void bootsplash_do_render_background(struct fb_info *info,
+ 				     const struct splash_file_priv *fp);
+ void bootsplash_do_render_pictures(struct fb_info *info,
+ 				   const struct splash_file_priv *fp);
++void bootsplash_do_render_flush(struct fb_info *info);
+ 
+ 
+ void bootsplash_free_file(struct splash_file_priv *fp);
+diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
+index 2ae36949d0e3..8c09c306ff67 100644
+--- a/drivers/video/fbdev/core/bootsplash_render.c
++++ b/drivers/video/fbdev/core/bootsplash_render.c
+@@ -186,3 +186,36 @@ void bootsplash_do_render_pictures(struct fb_info *info,
+ 				pp->pic_header->width, pp->pic_header->height);
+ 	}
+ }
++
++
++void bootsplash_do_render_flush(struct fb_info *info)
++{
++	/*
++	 * FB drivers using deferred_io (such as Xen) need to sync the
++	 * screen after modifying its contents. When the FB is mmap()ed
++	 * from userspace, this happens via a dirty pages callback, but
++	 * when modifying the FB from the kernel, there is no such thing.
++	 *
++	 * So let's issue a fake fb_copyarea (copying the FB onto itself)
++	 * to trick the FB driver into syncing the screen.
++	 *
++	 * A few DRM drivers' FB implementations are broken by not using
++	 * deferred_io when they really should - we match on the known
++	 * bad ones manually for now.
++	 */
++	if (info->fbdefio
++	    || !strcmp(info->fix.id, "astdrmfb")
++	    || !strcmp(info->fix.id, "cirrusdrmfb")
++	    || !strcmp(info->fix.id, "mgadrmfb")) {
++		struct fb_copyarea area;
++
++		area.dx = 0;
++		area.dy = 0;
++		area.width = info->var.xres;
++		area.height = info->var.yres;
++		area.sx = 0;
++		area.sy = 0;
++
++		info->fbops->fb_copyarea(info, &area);
++	}
++}
diff --git a/nongnu/packages/patches/pinephone-0004-bootsplash.patch b/nongnu/packages/patches/pinephone-0004-bootsplash.patch
new file mode 100644
index 0000000..7eb54af
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0004-bootsplash.patch
@@ -0,0 +1,215 @@
+diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
+index 8c09c306ff67..07e3a4eab811 100644
+--- a/drivers/video/fbdev/core/bootsplash_render.c
++++ b/drivers/video/fbdev/core/bootsplash_render.c
+@@ -155,6 +155,7 @@ void bootsplash_do_render_pictures(struct fb_info *info,
+ 	for (i = 0; i < fp->header->num_pics; i++) {
+ 		struct splash_blob_priv *bp;
+ 		struct splash_pic_priv *pp = &fp->pics[i];
++		const struct splash_pic_header *ph = pp->pic_header;
+ 		long dst_xoff, dst_yoff;
+ 
+ 		if (pp->blobs_loaded < 1)
+@@ -165,8 +166,139 @@ void bootsplash_do_render_pictures(struct fb_info *info,
+ 		if (!bp || bp->blob_header->type != 0)
+ 			continue;
+ 
+-		dst_xoff = (info->var.xres - pp->pic_header->width) / 2;
+-		dst_yoff = (info->var.yres - pp->pic_header->height) / 2;
++		switch (ph->position) {
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP_LEFT:
++			dst_xoff = 0;
++			dst_yoff = 0;
++
++			dst_xoff += ph->position_offset;
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = 0;
++
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_yoff = 0;
++
++			dst_xoff -= ph->position_offset;
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff -= ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++
++			dst_xoff -= ph->position_offset;
++			dst_yoff -= ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++
++			dst_yoff -= ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM_LEFT:
++			dst_xoff = 0 + ph->position_offset;
++			dst_yoff = info->var.yres - pp->pic_header->height
++						  - ph->position_offset;
++			break;
++		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_LEFT:
++			dst_xoff = 0;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff += ph->position_offset;
++			break;
++
++		case SPLASH_CORNER_TOP_LEFT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff -= ph->position_offset;
++			dst_yoff -= ph->position_offset;
++			break;
++		case SPLASH_CORNER_TOP:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_yoff -= ph->position_offset;
++			break;
++		case SPLASH_CORNER_TOP_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff += ph->position_offset;
++			dst_yoff -= ph->position_offset;
++			break;
++		case SPLASH_CORNER_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff += ph->position_offset;
++			break;
++		case SPLASH_CORNER_BOTTOM_RIGHT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff += ph->position_offset;
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_CORNER_BOTTOM:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_CORNER_BOTTOM_LEFT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff -= ph->position_offset;
++			dst_yoff += ph->position_offset;
++			break;
++		case SPLASH_CORNER_LEFT:
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++
++			dst_xoff -= ph->position_offset;
++			break;
++
++		default:
++			/* As a fallback, center the picture. */
++			dst_xoff = info->var.xres - pp->pic_header->width;
++			dst_xoff /= 2;
++			dst_yoff = info->var.yres - pp->pic_header->height;
++			dst_yoff /= 2;
++			break;
++		}
+ 
+ 		if (dst_xoff < 0
+ 		    || dst_yoff < 0
+diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
+index 89dc9cca8f0c..71cedcc68933 100644
+--- a/include/uapi/linux/bootsplash_file.h
++++ b/include/uapi/linux/bootsplash_file.h
+@@ -91,7 +91,32 @@ struct splash_pic_header {
+ 	 */
+ 	uint8_t num_blobs;
+ 
+-	uint8_t padding[27];
++	/*
++	 * Corner to move the picture to / from.
++	 *  0x00 - Top left
++	 *  0x01 - Top
++	 *  0x02 - Top right
++	 *  0x03 - Right
++	 *  0x04 - Bottom right
++	 *  0x05 - Bottom
++	 *  0x06 - Bottom left
++	 *  0x07 - Left
++	 *
++	 * Flags:
++	 *  0x10 - Calculate offset from the corner towards the center,
++	 *         rather than from the center towards the corner
++	 */
++	uint8_t position;
++
++	/*
++	 * Pixel offset from the selected position.
++	 * Example: If the picture is in the top right corner, it will
++	 *          be placed position_offset pixels from the top and
++	 *          position_offset pixels from the right margin.
++	 */
++	uint16_t position_offset;
++
++	uint8_t padding[24];
+ } __attribute__((__packed__));
+ 
+ 
+@@ -115,4 +140,22 @@ struct splash_blob_header {
+ 	uint8_t padding[9];
+ } __attribute__((__packed__));
+ 
++
++
++
++/*
++ * Enums for on-disk types
++ */
++enum splash_position {
++	SPLASH_CORNER_TOP_LEFT = 0,
++	SPLASH_CORNER_TOP = 1,
++	SPLASH_CORNER_TOP_RIGHT = 2,
++	SPLASH_CORNER_RIGHT = 3,
++	SPLASH_CORNER_BOTTOM_RIGHT = 4,
++	SPLASH_CORNER_BOTTOM = 5,
++	SPLASH_CORNER_BOTTOM_LEFT = 6,
++	SPLASH_CORNER_LEFT = 7,
++	SPLASH_POS_FLAG_CORNER = 0x10,
++};
++
+ #endif
diff --git a/nongnu/packages/patches/pinephone-0005-bootsplash.patch b/nongnu/packages/patches/pinephone-0005-bootsplash.patch
new file mode 100644
index 0000000..2785c5e
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0005-bootsplash.patch
@@ -0,0 +1,327 @@
+diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
+index 815b007f81ca..c8642142cfea 100644
+--- a/drivers/video/fbdev/core/bootsplash.c
++++ b/drivers/video/fbdev/core/bootsplash.c
+@@ -53,6 +53,14 @@ static void splash_callback_redraw_vc(struct work_struct *ignored)
+ 	console_unlock();
+ }
+ 
++static void splash_callback_animation(struct work_struct *ignored)
++{
++	if (bootsplash_would_render_now()) {
++		/* This will also re-schedule this delayed worker */
++		splash_callback_redraw_vc(ignored);
++	}
++}
++
+ 
+ static bool is_fb_compatible(const struct fb_info *info)
+ {
+@@ -103,17 +111,44 @@ static bool is_fb_compatible(const struct fb_info *info)
+  */
+ void bootsplash_render_full(struct fb_info *info)
+ {
++	bool is_update = false;
++
+ 	mutex_lock(&splash_state.data_lock);
+ 
+-	if (!is_fb_compatible(info))
+-		goto out;
++	/*
++	 * If we've painted on this FB recently, we don't have to do
++	 * the sanity checks and background drawing again.
++	 */
++	if (splash_state.splash_fb == info)
++		is_update = true;
++
++
++	if (!is_update) {
++		/* Check whether we actually support this FB. */
++		splash_state.splash_fb = NULL;
++
++		if (!is_fb_compatible(info))
++			goto out;
++
++		/* Draw the background only once */
++		bootsplash_do_render_background(info, splash_state.file);
+ 
+-	bootsplash_do_render_background(info, splash_state.file);
++		/* Mark this FB as last seen */
++		splash_state.splash_fb = info;
++	}
+ 
+-	bootsplash_do_render_pictures(info, splash_state.file);
++	bootsplash_do_render_pictures(info, splash_state.file, is_update);
+ 
+ 	bootsplash_do_render_flush(info);
+ 
++	bootsplash_do_step_animations(splash_state.file);
++
++	/* Schedule update for animated splash screens */
++	if (splash_state.file->frame_ms > 0)
++		schedule_delayed_work(&splash_state.dwork_animation,
++				      msecs_to_jiffies(
++				      splash_state.file->frame_ms));
++
+ out:
+ 	mutex_unlock(&splash_state.data_lock);
+ }
+@@ -169,8 +204,14 @@ void bootsplash_enable(void)
+ 
+ 	was_enabled = test_and_set_bit(0, &splash_state.enabled);
+ 
+-	if (!was_enabled)
++	if (!was_enabled) {
++		/* Force a full redraw when the splash is re-activated */
++		mutex_lock(&splash_state.data_lock);
++		splash_state.splash_fb = NULL;
++		mutex_unlock(&splash_state.data_lock);
++
+ 		schedule_work(&splash_state.work_redraw_vc);
++	}
+ }
+ 
+ 
+@@ -227,6 +268,14 @@ ATTRIBUTE_GROUPS(splash_dev);
+  */
+ static int splash_resume(struct device *device)
+ {
++	/*
++	 * Force full redraw on resume since we've probably lost the
++	 * framebuffer's contents meanwhile
++	 */
++	mutex_lock(&splash_state.data_lock);
++	splash_state.splash_fb = NULL;
++	mutex_unlock(&splash_state.data_lock);
++
+ 	if (bootsplash_would_render_now())
+ 		schedule_work(&splash_state.work_redraw_vc);
+ 
+@@ -235,6 +284,7 @@ static int splash_resume(struct device *device)
+ 
+ static int splash_suspend(struct device *device)
+ {
++	cancel_delayed_work_sync(&splash_state.dwork_animation);
+ 	cancel_work_sync(&splash_state.work_redraw_vc);
+ 
+ 	return 0;
+@@ -296,6 +346,8 @@ void bootsplash_init(void)
+ 	set_bit(0, &splash_state.enabled);
+ 
+ 	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
++	INIT_DELAYED_WORK(&splash_state.dwork_animation,
++			  splash_callback_animation);
+ 
+ 
+ 	if (!splash_state.bootfile || !strlen(splash_state.bootfile))
+diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
+index 0acb383aa4e3..b3a74835d90f 100644
+--- a/drivers/video/fbdev/core/bootsplash_internal.h
++++ b/drivers/video/fbdev/core/bootsplash_internal.h
+@@ -37,6 +37,8 @@ struct splash_pic_priv {
+ 
+ 	struct splash_blob_priv *blobs;
+ 	u16 blobs_loaded;
++
++	u16 anim_nextframe;
+ };
+ 
+ 
+@@ -45,6 +47,12 @@ struct splash_file_priv {
+ 	const struct splash_file_header *header;
+ 
+ 	struct splash_pic_priv *pics;
++
++	/*
++	 * A local copy of the frame delay in the header.
++	 * We modify it to keep the code simple.
++	 */
++	u16 frame_ms;
+ };
+ 
+ 
+@@ -71,6 +79,7 @@ struct splash_priv {
+ 	struct platform_device *splash_device;
+ 
+ 	struct work_struct work_redraw_vc;
++	struct delayed_work dwork_animation;
+ 
+ 	/* Splash data structures including lock for everything below */
+ 	struct mutex data_lock;
+@@ -88,8 +97,10 @@ struct splash_priv {
+ void bootsplash_do_render_background(struct fb_info *info,
+ 				     const struct splash_file_priv *fp);
+ void bootsplash_do_render_pictures(struct fb_info *info,
+-				   const struct splash_file_priv *fp);
++				   const struct splash_file_priv *fp,
++				   bool is_update);
+ void bootsplash_do_render_flush(struct fb_info *info);
++void bootsplash_do_step_animations(struct splash_file_priv *fp);
+ 
+ 
+ void bootsplash_free_file(struct splash_file_priv *fp);
+diff --git a/drivers/video/fbdev/core/bootsplash_load.c b/drivers/video/fbdev/core/bootsplash_load.c
+index fd807571ab7d..1f661b2d4cc9 100644
+--- a/drivers/video/fbdev/core/bootsplash_load.c
++++ b/drivers/video/fbdev/core/bootsplash_load.c
+@@ -71,6 +71,7 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
+ {
+ 	const struct firmware *fw;
+ 	struct splash_file_priv *fp;
++	bool have_anim = false;
+ 	unsigned int i;
+ 	const u8 *walker;
+ 
+@@ -135,6 +136,13 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
+ 			goto err;
+ 		}
+ 
++		if (ph->anim_type > SPLASH_ANIM_LOOP_FORWARD) {
++			pr_warn("Picture %u: Unsupported animation type %u.\n",
++				i, ph->anim_type);
++
++			ph->anim_type = SPLASH_ANIM_NONE;
++		}
++
+ 		pp->pic_header = ph;
+ 		pp->blobs = vzalloc(ph->num_blobs
+ 					* sizeof(struct splash_blob_priv));
+@@ -202,6 +210,7 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
+ 	/* Walk over pictures and ensure all blob slots are filled */
+ 	for (i = 0; i < fp->header->num_pics; i++) {
+ 		struct splash_pic_priv *pp = &fp->pics[i];
++		const struct splash_pic_header *ph = pp->pic_header;
+ 
+ 		if (pp->blobs_loaded != pp->pic_header->num_blobs) {
+ 			pr_err("Picture %u doesn't have all blob slots filled.\n",
+@@ -209,8 +218,20 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
+ 
+ 			goto err;
+ 		}
++
++		if (ph->anim_type
++		    && ph->num_blobs > 1
++		    && ph->anim_loop < pp->blobs_loaded)
++			have_anim = true;
+ 	}
+ 
++	if (!have_anim)
++		/* Disable animation timer if there is nothing to animate */
++		fp->frame_ms = 0;
++	else
++		/* Enforce minimum delay between frames */
++		fp->frame_ms = max((u16)20, fp->header->frame_ms);
++
+ 	pr_info("Loaded (%ld bytes, %u pics, %u blobs).\n",
+ 		fw->size,
+ 		fp->header->num_pics,
+diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
+index 07e3a4eab811..76033606ca8a 100644
+--- a/drivers/video/fbdev/core/bootsplash_render.c
++++ b/drivers/video/fbdev/core/bootsplash_render.c
+@@ -148,7 +148,8 @@ void bootsplash_do_render_background(struct fb_info *info,
+ 
+ 
+ void bootsplash_do_render_pictures(struct fb_info *info,
+-				   const struct splash_file_priv *fp)
++				   const struct splash_file_priv *fp,
++				   bool is_update)
+ {
+ 	unsigned int i;
+ 
+@@ -161,7 +162,11 @@ void bootsplash_do_render_pictures(struct fb_info *info,
+ 		if (pp->blobs_loaded < 1)
+ 			continue;
+ 
+-		bp = &pp->blobs[0];
++		/* Skip static pictures when refreshing animations */
++		if (ph->anim_type == SPLASH_ANIM_NONE && is_update)
++			continue;
++
++		bp = &pp->blobs[pp->anim_nextframe];
+ 
+ 		if (!bp || bp->blob_header->type != 0)
+ 			continue;
+@@ -351,3 +356,24 @@ void bootsplash_do_render_flush(struct fb_info *info)
+ 		info->fbops->fb_copyarea(info, &area);
+ 	}
+ }
++
++
++void bootsplash_do_step_animations(struct splash_file_priv *fp)
++{
++	unsigned int i;
++
++	/* Step every animation once */
++	for (i = 0; i < fp->header->num_pics; i++) {
++		struct splash_pic_priv *pp = &fp->pics[i];
++
++		if (pp->blobs_loaded < 2
++		    || pp->pic_header->anim_loop > pp->blobs_loaded)
++			continue;
++
++		if (pp->pic_header->anim_type == SPLASH_ANIM_LOOP_FORWARD) {
++			pp->anim_nextframe++;
++			if (pp->anim_nextframe >= pp->pic_header->num_blobs)
++				pp->anim_nextframe = pp->pic_header->anim_loop;
++		}
++	}
++}
+diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
+index 71cedcc68933..b3af0a3c6487 100644
+--- a/include/uapi/linux/bootsplash_file.h
++++ b/include/uapi/linux/bootsplash_file.h
+@@ -77,7 +77,17 @@ struct splash_file_header {
+ 	uint16_t num_blobs;
+ 	uint8_t num_pics;
+ 
+-	uint8_t padding[103];
++	uint8_t unused_1;
++
++	/*
++	 * Milliseconds to wait before painting the next frame in
++	 * an animation.
++	 * This is actually a minimum, as the system is allowed to
++	 * stall for longer between frames.
++	 */
++	uint16_t frame_ms;
++
++	uint8_t padding[100];
+ } __attribute__((__packed__));
+ 
+ 
+@@ -116,7 +126,23 @@ struct splash_pic_header {
+ 	 */
+ 	uint16_t position_offset;
+ 
+-	uint8_t padding[24];
++	/*
++	 * Animation type.
++	 *  0 - off
++	 *  1 - forward loop
++	 */
++	uint8_t anim_type;
++
++	/*
++	 * Animation loop point.
++	 * Actual meaning depends on animation type:
++	 * Type 0 - Unused
++	 *      1 - Frame at which to restart the forward loop
++	 *          (allowing for "intro" frames)
++	 */
++	uint8_t anim_loop;
++
++	uint8_t padding[22];
+ } __attribute__((__packed__));
+ 
+ 
+@@ -158,4 +184,9 @@ enum splash_position {
+ 	SPLASH_POS_FLAG_CORNER = 0x10,
+ };
+ 
++enum splash_anim_type {
++	SPLASH_ANIM_NONE = 0,
++	SPLASH_ANIM_LOOP_FORWARD = 1,
++};
++
+ #endif
diff --git a/nongnu/packages/patches/pinephone-0006-bootsplash.patch b/nongnu/packages/patches/pinephone-0006-bootsplash.patch
new file mode 100644
index 0000000..d6c6db6
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0006-bootsplash.patch
@@ -0,0 +1,82 @@
+diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
+index 2ebaba16f785..416735ab6dc1 100644
+--- a/drivers/tty/vt/vt.c
++++ b/drivers/tty/vt/vt.c
+@@ -105,6 +105,7 @@
+ #include <linux/ctype.h>
+ #include <linux/bsearch.h>
+ #include <linux/gcd.h>
++#include <linux/bootsplash.h>
+ 
+ #define MAX_NR_CON_DRIVER 16
+ 
+@@ -4235,6 +4236,7 @@ void do_unblank_screen(int leaving_gfx)
+ 	}
+ 
+ 	console_blanked = 0;
++	bootsplash_mark_dirty();
+ 	if (vc->vc_sw->con_blank(vc, 0, leaving_gfx))
+ 		/* Low-level driver cannot restore -> do it ourselves */
+ 		update_screen(vc);
+diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
+index c8642142cfea..13fcaabbc2ca 100644
+--- a/drivers/video/fbdev/core/bootsplash.c
++++ b/drivers/video/fbdev/core/bootsplash.c
+@@ -165,6 +165,13 @@ bool bootsplash_would_render_now(void)
+ 		&& bootsplash_is_enabled();
+ }
+ 
++void bootsplash_mark_dirty(void)
++{
++	mutex_lock(&splash_state.data_lock);
++	splash_state.splash_fb = NULL;
++	mutex_unlock(&splash_state.data_lock);
++}
++
+ bool bootsplash_is_enabled(void)
+ {
+ 	bool was_enabled;
+@@ -206,9 +213,7 @@ void bootsplash_enable(void)
+ 
+ 	if (!was_enabled) {
+ 		/* Force a full redraw when the splash is re-activated */
+-		mutex_lock(&splash_state.data_lock);
+-		splash_state.splash_fb = NULL;
+-		mutex_unlock(&splash_state.data_lock);
++		bootsplash_mark_dirty();
+ 
+ 		schedule_work(&splash_state.work_redraw_vc);
+ 	}
+@@ -272,9 +277,7 @@ static int splash_resume(struct device *device)
+ 	 * Force full redraw on resume since we've probably lost the
+ 	 * framebuffer's contents meanwhile
+ 	 */
+-	mutex_lock(&splash_state.data_lock);
+-	splash_state.splash_fb = NULL;
+-	mutex_unlock(&splash_state.data_lock);
++	bootsplash_mark_dirty();
+ 
+ 	if (bootsplash_would_render_now())
+ 		schedule_work(&splash_state.work_redraw_vc);
+diff --git a/include/linux/bootsplash.h b/include/linux/bootsplash.h
+index c6dd0b43180d..4075098aaadd 100644
+--- a/include/linux/bootsplash.h
++++ b/include/linux/bootsplash.h
+@@ -19,6 +19,8 @@ extern void bootsplash_render_full(struct fb_info *info);
+ 
+ extern bool bootsplash_would_render_now(void);
+ 
++extern void bootsplash_mark_dirty(void);
++
+ extern bool bootsplash_is_enabled(void);
+ extern void bootsplash_disable(void);
+ extern void bootsplash_enable(void);
+@@ -31,6 +33,8 @@ extern void bootsplash_init(void);
+ 
+ #define bootsplash_would_render_now() (false)
+ 
++#define bootsplash_mark_dirty()
++
+ #define bootsplash_is_enabled() (false)
+ #define bootsplash_disable()
+ #define bootsplash_enable()
diff --git a/nongnu/packages/patches/pinephone-0007-bootsplash.patch b/nongnu/packages/patches/pinephone-0007-bootsplash.patch
new file mode 100644
index 0000000..3f82eb0
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0007-bootsplash.patch
@@ -0,0 +1,42 @@
+diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
+index f4166263bb3a..a248429194bb 100644
+--- a/drivers/tty/vt/keyboard.c
++++ b/drivers/tty/vt/keyboard.c
+@@ -49,6 +49,8 @@
+ 
+ #include <asm/irq_regs.h>
+ 
++#include <linux/bootsplash.h>
++
+ /*
+  * Exported functions/variables
+  */
+@@ -1413,6 +1415,28 @@ static void kbd_keycode(unsigned int key
+ 	}
+ #endif
+ 
++	/* Trap keys when bootsplash is shown */
++	if (bootsplash_would_render_now()) {
++		/* Deactivate bootsplash on ESC or Alt+Fxx VT switch */
++		if (keycode >= KEY_F1 && keycode <= KEY_F12) {
++			bootsplash_disable();
++
++			/*
++			 * No return here since we want to actually
++			 * perform the VT switch.
++			 */
++		} else {
++			if (keycode == KEY_ESC)
++				bootsplash_disable();
++
++			/*
++			 * Just drop any other keys.
++			 * Their effect would be hidden by the splash.
++			 */
++			return;
++		}
++	}
++
+ 	if (kbd->kbdmode == VC_MEDIUMRAW) {
+ 		/*
+ 		 * This is extended medium raw mode, with keys above 127
diff --git a/nongnu/packages/patches/pinephone-0008-bootsplash.patch b/nongnu/packages/patches/pinephone-0008-bootsplash.patch
new file mode 100644
index 0000000..8a3b715
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0008-bootsplash.patch
@@ -0,0 +1,21 @@
+diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
+index 3ffc1ce29023..bc6a24c9dfa8 100644
+--- a/drivers/tty/sysrq.c
++++ b/drivers/tty/sysrq.c
+@@ -49,6 +49,7 @@
+ #include <linux/syscalls.h>
+ #include <linux/of.h>
+ #include <linux/rcupdate.h>
++#include <linux/bootsplash.h>
+ 
+ #include <asm/ptrace.h>
+ #include <asm/irq_regs.h>
+@@ -104,6 +105,8 @@ static void sysrq_handle_SAK(int key)
+ {
+ 	struct work_struct *SAK_work = &vc_cons[fg_console].SAK_work;
+ 	schedule_work(SAK_work);
++
++	bootsplash_disable();
+ }
+ static struct sysrq_key_op sysrq_SAK_op = {
+ 	.handler	= sysrq_handle_SAK,
diff --git a/nongnu/packages/patches/pinephone-0009-bootsplash.patch b/nongnu/packages/patches/pinephone-0009-bootsplash.patch
new file mode 100644
index 0000000..add68e7
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0009-bootsplash.patch
@@ -0,0 +1,21 @@
+diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
+index 9a39a6fcfe98..8a9c67e1c5d8 100644
+--- a/drivers/video/fbdev/core/fbcon.c
++++ b/drivers/video/fbdev/core/fbcon.c
+@@ -1343,6 +1343,16 @@ static void fbcon_cursor(struct vc_data *vc, int mode)
+ 	int y;
+  	int c = scr_readw((u16 *) vc->vc_pos);
+ 
++	/*
++	 * Disable the splash here so we don't have to hook into
++	 * vt_console_print() in drivers/tty/vt/vt.c
++	 *
++	 * We'd disable the splash just before the call to
++	 * hide_cursor() anyway, so this spot is just fine.
++	 */
++	if (oops_in_progress)
++		bootsplash_disable();
++
+ 	ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
+ 
+ 	if (fbcon_is_inactive(vc, info) || vc->vc_deccm != 1)
diff --git a/nongnu/packages/patches/pinephone-0010-bootsplash.patch b/nongnu/packages/patches/pinephone-0010-bootsplash.patch
new file mode 100644
index 0000000..c74b4da
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0010-bootsplash.patch
@@ -0,0 +1,308 @@
+diff --git a/Documentation/ABI/testing/sysfs-platform-bootsplash b/Documentation/ABI/testing/sysfs-platform-bootsplash
+new file mode 100644
+index 000000000000..742c7b035ded
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-platform-bootsplash
+@@ -0,0 +1,11 @@
++What:		/sys/devices/platform/bootsplash.0/enabled
++Date:		Oct 2017
++KernelVersion:	4.14
++Contact:	Max Staudt <mstaudt@suse.de>
++Description:
++		Can be set and read.
++
++		0: Splash is disabled.
++		1: Splash is shown whenever fbcon would show a text console
++		   (i.e. no graphical application is running), and a splash
++		   file is loaded.
+diff --git a/Documentation/bootsplash.rst b/Documentation/bootsplash.rst
+new file mode 100644
+index 000000000000..611f0c558925
+--- /dev/null
++++ b/Documentation/bootsplash.rst
+@@ -0,0 +1,285 @@
++====================
++The Linux bootsplash
++====================
++
++:Date: November, 2017
++:Author: Max Staudt <mstaudt@suse.de>
++
++
++The Linux bootsplash is a graphical replacement for the '``quiet``' boot
++option, typically showing a logo and a spinner animation as the system starts.
++
++Currently, it is a part of the Framebuffer Console support, and can be found
++as ``CONFIG_BOOTSPLASH`` in the kernel configuration. This means that as long
++as it is enabled, it hijacks fbcon's output and draws a splash screen instead.
++
++Purely compiling in the bootsplash will not render it functional - to actually
++render a splash, you will also need a splash theme file. See the example
++utility and script in ``tools/bootsplash`` for a live demo.
++
++
++
++Motivation
++==========
++
++- The '``quiet``' boot option only suppresses most messages during boot, but
++  errors are still shown.
++
++- A user space implementation can only show a logo once user space has been
++  initialized far enough to allow this. A kernel splash can display a splash
++  immediately as soon as fbcon can be displayed.
++
++- Implementing a splash screen in user space (e.g. Plymouth) is problematic
++  due to resource conflicts.
++
++  For example, if Plymouth is keeping ``/dev/fb0`` (provided via vesafb/efifb)
++  open, then most DRM drivers can't replace it because the address space is
++  still busy - thus leading to a VRAM reservation error.
++
++  See: https://bugzilla.opensuse.org/show_bug.cgi?id=980750
++
++
++
++Command line arguments
++======================
++
++``bootsplash.bootfile``
++  Which file in the initramfs to load.
++
++  The splash theme is loaded via request_firmware(), thus to load
++  ``/lib/firmware/bootsplash/mytheme`` pass the command line:
++
++  ``bootsplash.bootfile=bootsplash/mytheme``
++
++  Note: The splash file *has to be* in the initramfs, as it needs to be
++  available when the splash is initialized early on.
++
++  Default: none, i.e. a non-functional splash, falling back to showing text.
++
++
++
++sysfs run-time configuration
++============================
++
++``/sys/devices/platform/bootsplash.0/enabled``
++  Enable/disable the bootsplash.
++  The system boots with this set to 1, but will not show a splash unless
++  a splash theme file is also loaded.
++
++
++
++Kconfig
++=======
++
++``BOOTSPLASH``
++  Whether to compile in bootsplash support
++  (depends on fbcon compiled in, i.e. ``FRAMEBUFFER_CONSOLE=y``)
++
++
++
++Bootsplash file format
++======================
++
++A file specified in the kernel configuration as ``CONFIG_BOOTSPLASH_FILE``
++or specified on the command line as ``bootsplash.bootfile`` will be loaded
++and displayed as soon as fbcon is initialized.
++
++
++Main blocks
++-----------
++
++There are 3 main blocks in each file:
++
++  - one File header
++  -   n Picture headers
++  -   m (Blob header + payload) blocks
++
++
++Structures
++----------
++
++The on-disk structures are defined in
++``drivers/video/fbdev/core/bootsplash_file.h`` and represent these blocks:
++
++  - ``struct splash_file_header``
++
++    Represents the file header, with splash-wide information including:
++
++      - The magic string "``Linux bootsplash``" on big-endian platforms
++        (the reverse on little endian)
++      - The file format version (for incompatible updates, hopefully never)
++      - The background color
++      - Number of picture and blob blocks
++      - Animation speed (we only allow one delay for all animations)
++
++    The file header is followed by the first picture header.
++
++
++  - ``struct splash_picture_header``
++
++    Represents an object (picture) drawn on screen, including its immutable
++    properties:
++      - Width, height
++      - Positioning relative to screen corners or in the center
++      - Animation, if any
++      - Animation type
++      - Number of blobs
++
++    The picture header is followed by another picture header, up until n
++    picture headers (as defined in the file header) have been read. Then,
++    the (blob header, payload) pairs follow.
++
++
++  - ``struct splash_blob_header``
++    (followed by payload)
++
++    Represents one raw data stream. So far, only picture data is defined.
++
++    The blob header is followed by a payload, then padding to n*16 bytes,
++    then (if further blobs are defined in the file header) a further blob
++    header.
++
++
++Alignment
++---------
++
++The bootsplash file is designed to be loaded into memory as-is.
++
++All structures are a multiple of 16 bytes long, all elements therein are
++aligned to multiples of their length, and the payloads are always padded
++up to multiples of 16 bytes. This is to allow aligned accesses in all
++cases while still simply mapping the structures over an in-memory copy of
++the bootsplash file.
++
++
++Further information
++-------------------
++
++Please see ``drivers/video/fbdev/core/bootsplash_file.h`` for further
++details and possible values in the file.
++
++
++
++Hooks - how the bootsplash is integrated
++========================================
++
++``drivers/video/fbdev/core/fbcon.c``
++  ``fbcon_init()`` calls ``bootsplash_init()``, which loads the default
++  bootsplash file or the one specified on the kernel command line.
++
++  ``fbcon_switch()`` draws the bootsplash when it's active, and is also
++  one of the callers of ``set_blitting_type()``.
++
++  ``set_blitting_type()`` calls ``fbcon_set_dummyops()`` when the
++  bootsplash is active, overriding the text rendering functions.
++
++  ``fbcon_cursor()`` will call ``bootsplash_disable()`` when an oops is
++  being printed in order to make a kernel panic visible.
++
++``drivers/video/fbdev/core/dummyblit.c``
++  This contains the dummy text rendering functions used to suppress text
++  output while the bootsplash is shown.
++
++``drivers/tty/vt/keyboard.c``
++  ``kbd_keycode()`` can call ``bootsplash_disable()`` when the user
++  presses ESC or F1-F12 (changing VT). This is to provide a built-in way
++  of disabling the splash manually at any time.
++
++
++
++FAQ: Frequently Asked Questions
++===============================
++
++I want to see the log! How do I show the log?
++---------------------------------------------
++
++Press ESC while the splash is shown, or remove the ``bootsplash.bootfile``
++parameter from the kernel cmdline. Without that parameter, the bootsplash
++will boot disabled.
++
++
++Why use FB instead of modern DRM/KMS?
++-------------------------------------
++
++This is a semantic problem:
++ - What memory to draw the splash to?
++ - And what mode will the screen be set to?
++
++Using the fbdev emulation solves these issues.
++
++Let's start from a bare KMS system, without fbcon, and without fbdev
++emulation. In this case, as long as userspace doesn't open the KMS
++device, the state of the screen is undefined. No framebuffer is
++allocated in video RAM, and no particular mode is set.
++
++In this case, we'd have to allocate a framebuffer to show the splash,
++and set our mode ourselves. This either wastes a screenful of video RAM
++if the splash is to co-exist with the userspace program's own allocated
++framebuffer, or there is a flicker as we deactivate and delete the
++bootsplash's framebuffer and hand control over to userspace. Since we
++may set a different mode than userspace, we'd also have flicker due
++to mode switching.
++
++This logic is already contained in every KMS driver that performs fbdev
++emulation. So we might as well use that. And the correct API to do so is
++fbdev. Plus, we get compatibility with old, pure fbdev drivers for free.
++With the fbdev emulation, there is *always* a well-defined framebuffer
++to draw on. And the selection of mode has already been done by the
++graphics driver, so we don't need to reinvent that wheel, either.
++Finally, if userspace decides to use /dev/fbX, we don't have to worry
++about wasting video RAM, either.
++
++
++Why is the bootsplash integrated in fbcon?
++------------------------------------------
++
++Right now, the bootsplash is drawn from within fbcon, as this allows us
++to easily know *when* to draw - i.e. when we're safe from fbcon and
++userspace drawing all over our beautiful splash logo.
++
++Separating them is not easy - see the to-do list below.
++
++
++
++TO DO list for future development
++=================================
++
++Second enable/disable switch for the system
++-------------------------------------------
++
++It may be helpful to differentiate between the system and the user
++switching off the bootsplash. Thus, the system may make it disappear and
++reappear e.g. for a password prompt, yet once the user has pressed ESC,
++it could stay gone.
++
++
++Fix buggy DRM/KMS drivers
++-------------------------
++
++Currently, the splash code manually checks for fbdev emulation provided by
++the ast, cirrus, and mgag200 DRM/KMS drivers.
++These drivers use a manual mechanism similar to deferred I/O for their FB
++emulation, and thus need to be manually flushed onto the screen in the same
++way.
++
++This may be improved upon in several ways:
++
++1. Changing these drivers to expose the fbdev BO's memory directly, like
++   bochsdrmfb does.
++2. Creating a new fb_ops->fb_flush() API to allow the kernel to flush the
++   framebuffer once the bootsplash has been drawn into it.
++
++
++Separating from fbcon
++---------------------
++
++Separating these two components would yield independence from fbcon being
++compiled into the kernel, and thus lowering code size in embedded
++applications.
++
++To do this cleanly will involve a clean separation of users of an FB device
++within the kernel, i.e. fbcon, bootsplash, and userspace. Right now, the
++legacy fbcon code and VT code co-operate to switch between fbcon and
++userspace (by setting the VT into KD_GRAPHICS mode). Installing a muxer
++between these components ensues refactoring of old code and checking for
++correct locking.
diff --git a/nongnu/packages/patches/pinephone-0011-bootsplash.patch b/nongnu/packages/patches/pinephone-0011-bootsplash.patch
new file mode 100644
index 0000000..4e0c98f
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-0011-bootsplash.patch
@@ -0,0 +1,499 @@
+diff --git a/tools/bootsplash/.gitignore b/tools/bootsplash/.gitignore
+new file mode 100644
+index 000000000000..091b99a17567
+--- /dev/null
++++ b/tools/bootsplash/.gitignore
+@@ -0,0 +1 @@
++bootsplash-packer
+diff --git a/tools/bootsplash/Makefile b/tools/bootsplash/Makefile
+new file mode 100644
+index 000000000000..0ad8e8a84942
+--- /dev/null
++++ b/tools/bootsplash/Makefile
+@@ -0,0 +1,9 @@
++CC := $(CROSS_COMPILE)gcc
++CFLAGS := -I../../usr/include
++
++PROGS := bootsplash-packer
++
++all: $(PROGS)
++
++clean:
++	rm -fr $(PROGS)
+diff --git a/tools/bootsplash/bootsplash-packer.c b/tools/bootsplash/bootsplash-packer.c
+new file mode 100644
+index 000000000000..ffb6a8b69885
+--- /dev/null
++++ b/tools/bootsplash/bootsplash-packer.c
+@@ -0,0 +1,471 @@
++/*
++ * Kernel based bootsplash.
++ *
++ * (Splash file packer tool)
++ *
++ * Authors:
++ * Max Staudt <mstaudt@suse.de>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#include <endian.h>
++#include <getopt.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++#include <linux/bootsplash_file.h>
++
++
++static void print_help(char *progname)
++{
++	printf("Usage: %s [OPTIONS] outfile\n", progname);
++	printf("\n"
++	       "Options, executed in order given:\n"
++	       "  -h, --help                   Print this help message\n"
++	       "\n"
++	       "  --bg_red <u8>                Background color (red part)\n"
++	       "  --bg_green <u8>              Background color (green part)\n"
++	       "  --bg_blue <u8>               Background color (blue part)\n"
++	       "  --bg_reserved <u8>           (do not use)\n"
++	       "  --frame_ms <u16>             Minimum milliseconds between animation steps\n"
++	       "\n"
++	       "  --picture                    Start describing the next picture\n"
++	       "  --pic_width <u16>            Picture width in pixels\n"
++	       "  --pic_height <u16>           Picture height in pixels\n"
++	       "  --pic_position <u8>             Coarse picture placement:\n"
++	       "                                  0x00 - Top left\n"
++	       "                                  0x01 - Top\n"
++	       "                                  0x02 - Top right\n"
++	       "                                  0x03 - Right\n"
++	       "                                  0x04 - Bottom right\n"
++	       "                                  0x05 - Bottom\n"
++	       "                                  0x06 - Bottom left\n"
++	       "                                  0x07 - Left\n"
++	       "\n"
++	       "                                Flags:\n"
++	       "                                 0x10 - Calculate offset from corner towards center,\n"
++	       "                                         rather than from center towards corner\n"
++	       "  --pic_position_offset <u16>  Distance from base position in pixels\n"
++	       "  --pic_anim_type <u8>         Animation type:\n"
++	       "                                 0 - None\n"
++	       "                                 1 - Forward loop\n"
++	       "  --pic_anim_loop <u8>         Loop point for animation\n"
++	       "\n"
++	       "  --blob <filename>            Include next data stream\n"
++	       "  --blob_type <u16>            Type of data\n"
++	       "  --blob_picture_id <u8>       Picture to associate this blob with, starting at 0\n"
++	       "                                 (default: number of last --picture)\n"
++	       "\n");
++	printf("This tool will write %s files.\n\n",
++#if __BYTE_ORDER == __BIG_ENDIAN
++	       "Big Endian (BE)");
++#elif __BYTE_ORDER == __LITTLE_ENDIAN
++	       "Little Endian (LE)");
++#else
++#error
++#endif
++}
++
++
++struct blob_entry {
++	struct blob_entry *next;
++
++	char *fn;
++
++	struct splash_blob_header header;
++};
++
++
++static void dump_file_header(struct splash_file_header *h)
++{
++	printf(" --- File header ---\n");
++	printf("\n");
++	printf("  version:     %5u\n", h->version);
++	printf("\n");
++	printf("  bg_red:      %5u\n", h->bg_red);
++	printf("  bg_green:    %5u\n", h->bg_green);
++	printf("  bg_blue:     %5u\n", h->bg_blue);
++	printf("  bg_reserved: %5u\n", h->bg_reserved);
++	printf("\n");
++	printf("  num_blobs:   %5u\n", h->num_blobs);
++	printf("  num_pics:    %5u\n", h->num_pics);
++	printf("\n");
++	printf("  frame_ms:    %5u\n", h->frame_ms);
++	printf("\n");
++}
++
++static void dump_pic_header(struct splash_pic_header *ph)
++{
++	printf(" --- Picture header ---\n");
++	printf("\n");
++	printf("  width:           %5u\n", ph->width);
++	printf("  height:          %5u\n", ph->height);
++	printf("\n");
++	printf("  num_blobs:       %5u\n", ph->num_blobs);
++	printf("\n");
++	printf("  position:        %0x3x\n", ph->position);
++	printf("  position_offset: %5u\n", ph->position_offset);
++	printf("\n");
++	printf("  anim_type:       %5u\n", ph->anim_type);
++	printf("  anim_loop:       %5u\n", ph->anim_loop);
++	printf("\n");
++}
++
++static void dump_blob(struct blob_entry *b)
++{
++	printf(" --- Blob header ---\n");
++	printf("\n");
++	printf("  length:     %7u\n", b->header.length);
++	printf("  type:       %7u\n", b->header.type);
++	printf("\n");
++	printf("  picture_id: %7u\n", b->header.picture_id);
++	printf("\n");
++}
++
++
++#define OPT_MAX(var, max) \
++	do { \
++		if ((var) > max) { \
++			fprintf(stderr, "--%s: Invalid value\n", \
++			long_options[option_index].name); \
++			break; \
++		} \
++	} while (0)
++
++static struct option long_options[] = {
++	{"help", 0, 0, 'h'},
++	{"bg_red", 1, 0, 10001},
++	{"bg_green", 1, 0, 10002},
++	{"bg_blue", 1, 0, 10003},
++	{"bg_reserved", 1, 0, 10004},
++	{"frame_ms", 1, 0, 10005},
++	{"picture", 0, 0, 20000},
++	{"pic_width", 1, 0, 20001},
++	{"pic_height", 1, 0, 20002},
++	{"pic_position", 1, 0, 20003},
++	{"pic_position_offset", 1, 0, 20004},
++	{"pic_anim_type", 1, 0, 20005},
++	{"pic_anim_loop", 1, 0, 20006},
++	{"blob", 1, 0, 30000},
++	{"blob_type", 1, 0, 30001},
++	{"blob_picture_id", 1, 0, 30002},
++	{NULL, 0, NULL, 0}
++};
++
++
++int main(int argc, char **argv)
++{
++	FILE *of;
++	char *ofn;
++	int c;
++	int option_index = 0;
++
++	unsigned long ul;
++	struct splash_file_header fh = {};
++	struct splash_pic_header ph[255];
++	struct blob_entry *blob_first = NULL;
++	struct blob_entry *blob_last = NULL;
++	struct blob_entry *blob_cur = NULL;
++
++	if (argc < 2) {
++		print_help(argv[0]);
++		return EXIT_FAILURE;
++	}
++
++
++	/* Parse and and execute user commands */
++	while ((c = getopt_long(argc, argv, "h",
++			  long_options, &option_index)) != -1) {
++		switch (c) {
++		case 10001:	/* bg_red */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			fh.bg_red = ul;
++			break;
++		case 10002:	/* bg_green */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			fh.bg_green = ul;
++			break;
++		case 10003:	/* bg_blue */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			fh.bg_blue = ul;
++			break;
++		case 10004:	/* bg_reserved */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			fh.bg_reserved = ul;
++			break;
++		case 10005:	/* frame_ms */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 65535);
++			fh.frame_ms = ul;
++			break;
++
++
++		case 20000:	/* picture */
++			if (fh.num_pics >= 255) {
++				fprintf(stderr, "--%s: Picture array full\n",
++					long_options[option_index].name);
++				break;
++			}
++
++			fh.num_pics++;
++			break;
++
++		case 20001:	/* pic_width */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 65535);
++			ph[fh.num_pics - 1].width = ul;
++			break;
++
++		case 20002:	/* pic_height */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 65535);
++			ph[fh.num_pics - 1].height = ul;
++			break;
++
++		case 20003:	/* pic_position */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			ph[fh.num_pics - 1].position = ul;
++			break;
++
++		case 20004:	/* pic_position_offset */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			ph[fh.num_pics - 1].position_offset = ul;
++			break;
++
++		case 20005:	/* pic_anim_type */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			ph[fh.num_pics - 1].anim_type = ul;
++			break;
++
++		case 20006:	/* pic_anim_loop */
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			ph[fh.num_pics - 1].anim_loop = ul;
++			break;
++
++
++		case 30000:	/* blob */
++			if (fh.num_blobs >= 65535) {
++				fprintf(stderr, "--%s: Blob array full\n",
++					long_options[option_index].name);
++				break;
++			}
++
++			blob_cur = calloc(1, sizeof(struct blob_entry));
++			if (!blob_cur) {
++				fprintf(stderr, "--%s: Out of memory\n",
++					long_options[option_index].name);
++				break;
++			}
++
++			blob_cur->fn = optarg;
++			if (fh.num_pics)
++				blob_cur->header.picture_id = fh.num_pics - 1;
++
++			if (!blob_first)
++				blob_first = blob_cur;
++			if (blob_last)
++				blob_last->next = blob_cur;
++			blob_last = blob_cur;
++			fh.num_blobs++;
++			break;
++
++		case 30001:	/* blob_type */
++			if (!blob_cur) {
++				fprintf(stderr, "--%s: No blob selected\n",
++					long_options[option_index].name);
++				break;
++			}
++
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			blob_cur->header.type = ul;
++			break;
++
++		case 30002:	/* blob_picture_id */
++			if (!blob_cur) {
++				fprintf(stderr, "--%s: No blob selected\n",
++					long_options[option_index].name);
++				break;
++			}
++
++			ul = strtoul(optarg, NULL, 0);
++			OPT_MAX(ul, 255);
++			blob_cur->header.picture_id = ul;
++			break;
++
++
++
++		case 'h':
++		case '?':
++		default:
++			print_help(argv[0]);
++			goto EXIT;
++		} /* switch (c) */
++	} /* while ((c = getopt_long(...)) != -1) */
++
++	/* Consume and drop lone arguments */
++	while (optind < argc) {
++		ofn = argv[optind];
++		optind++;
++	}
++
++
++	/* Read file lengths */
++	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next) {
++		FILE *f;
++		long pos;
++		int i;
++
++		if (!blob_cur->fn)
++			continue;
++
++		f = fopen(blob_cur->fn, "rb");
++		if (!f)
++			goto ERR_FILE_LEN;
++
++		if (fseek(f, 0, SEEK_END))
++			goto ERR_FILE_LEN;
++
++		pos = ftell(f);
++		if (pos < 0 || pos > (1 << 30))
++			goto ERR_FILE_LEN;
++
++		blob_cur->header.length = pos;
++
++		fclose(f);
++		continue;
++
++ERR_FILE_LEN:
++		fprintf(stderr, "Error getting file length (or too long): %s\n",
++			blob_cur->fn);
++		if (f)
++			fclose(f);
++		continue;
++	}
++
++
++	/* Set magic headers */
++#if __BYTE_ORDER == __BIG_ENDIAN
++	memcpy(&fh.id[0], BOOTSPLASH_MAGIC_BE, 16);
++#elif __BYTE_ORDER == __LITTLE_ENDIAN
++	memcpy(&fh.id[0], BOOTSPLASH_MAGIC_LE, 16);
++#else
++#error
++#endif
++	fh.version = BOOTSPLASH_VERSION;
++
++	/* Set blob counts */
++	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next) {
++		if (blob_cur->header.picture_id < fh.num_pics)
++			ph[blob_cur->header.picture_id].num_blobs++;
++	}
++
++
++	/* Dump structs */
++	dump_file_header(&fh);
++
++	for (ul = 0; ul < fh.num_pics; ul++)
++		dump_pic_header(&ph[ul]);
++
++	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next)
++		dump_blob(blob_cur);
++
++
++	/* Write to file */
++	printf("Writing splash to file: %s\n", ofn);
++	of = fopen(ofn, "wb");
++	if (!of)
++		goto ERR_WRITING;
++
++	if (fwrite(&fh, sizeof(struct splash_file_header), 1, of) != 1)
++		goto ERR_WRITING;
++
++	for (ul = 0; ul < fh.num_pics; ul++) {
++		if (fwrite(&ph[ul], sizeof(struct splash_pic_header), 1, of)
++		    != 1)
++			goto ERR_WRITING;
++	}
++
++	blob_cur = blob_first;
++	while (blob_cur) {
++		struct blob_entry *blob_old = blob_cur;
++		FILE *f;
++		char *buf[256];
++		uint32_t left;
++
++		if (fwrite(&blob_cur->header,
++			   sizeof(struct splash_blob_header), 1, of) != 1)
++			goto ERR_WRITING;
++
++		if (!blob_cur->header.length || !blob_cur->fn)
++			continue;
++
++		f = fopen(blob_cur->fn, "rb");
++		if (!f)
++			goto ERR_FILE_COPY;
++
++		left = blob_cur->header.length;
++		while (left >= sizeof(buf)) {
++			if (fread(buf, sizeof(buf), 1, f) != 1)
++				goto ERR_FILE_COPY;
++			if (fwrite(buf, sizeof(buf), 1, of) != 1)
++				goto ERR_FILE_COPY;
++			left -= sizeof(buf);
++		}
++		if (left) {
++			if (fread(buf, left, 1, f) != 1)
++				goto ERR_FILE_COPY;
++			if (fwrite(buf, left, 1, of) != 1)
++				goto ERR_FILE_COPY;
++		}
++
++		/* Pad data stream to 16 bytes */
++		if (left % 16) {
++			if (fwrite("\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0",
++					16 - (left % 16), 1, of) != 1)
++				goto ERR_FILE_COPY;
++		}
++
++		fclose(f);
++		blob_cur = blob_cur->next;
++		free(blob_old);
++		continue;
++
++ERR_FILE_COPY:
++		if (f)
++			fclose(f);
++		goto ERR_WRITING;
++	}
++
++	fclose(of);
++
++EXIT:
++	return EXIT_SUCCESS;
++
++
++ERR_WRITING:
++	fprintf(stderr, "Error writing splash.\n");
++	fprintf(stderr, "The output file is probably corrupt.\n");
++	if (of)
++		fclose(of);
++
++	while (blob_cur) {
++		struct blob_entry *blob_old = blob_cur;
++
++		blob_cur = blob_cur->next;
++		free(blob_old);
++	}
++
++	return EXIT_FAILURE;
++}
diff --git a/nongnu/packages/patches/pinephone-drop-modem-power-node.patch b/nongnu/packages/patches/pinephone-drop-modem-power-node.patch
new file mode 100644
index 0000000..b90eced
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-drop-modem-power-node.patch
@@ -0,0 +1,175 @@
+From 602d05e416ae0d0fba3022fa2c3d195164b406c6 Mon Sep 17 00:00:00 2001
+From: Clayton Craft <clayton@craftyguy.net>
+Date: Wed, 16 Dec 2020 20:16:14 -0800
+Subject: [PATCH] dts: pinephone: drop modem-power node
+
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 26 +++---------------
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 27 +++----------------
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 27 +++----------------
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 12 +++++++++
+ 4 files changed, 24 insertions(+), 68 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index a21c6d78a..7f0cfdafe 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -86,28 +86,6 @@ &reg_drivevbus {
+ 	status = "okay";
+ };
+ 
+-&uart3 {
+-	modem {
+-		compatible = "quectel,eg25";
+-		char-device-name = "modem-power";
+-
+-		power-supply = <&reg_vbat_bb>; /* PL7 */
+-
+-		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+-		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-
+-		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+-		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
+-
+-		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
+-		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
+-		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
+-
+-		quectel,qdai = "1,1,0,1,0,0,1,1";
+-	};
+-};
+-
+ &usbphy {
+ 	usb-role-switch;
+ 
+@@ -118,6 +96,10 @@ usb0_drd_sw: endpoint {
+ 	};
+ };
+ 
++&ring_indicator {
++	gpios = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 */
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ 	flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 61ff56b17..5e85ddc12 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -109,34 +109,15 @@ &reg_drivevbus {
+ 	status = "okay";
+ };
+ 
++&ring_indicator {
++	gpios = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 */
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
+-&uart3 {
+-	modem {
+-		compatible = "quectel,eg25";
+-		char-device-name = "modem-power";
+-
+-		power-supply = <&reg_vbat_bb>; /* PL7 */
+-
+-		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+-		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-		//status-pwrkey-multiplexed; /* status acts as pwrkey */
+-
+-		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+-		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
+-
+-		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
+-		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
+-		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
+-
+-		quectel,qdai = "1,1,0,1,0,0,1,1";
+-	};
+-};
+-
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index fe7d567a8..f4b9b0991 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -101,34 +101,15 @@ &reg_anx1v0 {
+ 	enable-active-high;
+ };
+ 
++&ring_indicator {
++	gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
+-&uart3 {
+-	modem {
+-		compatible = "quectel,eg25";
+-		char-device-name = "modem-power";
+-
+-		power-supply = <&reg_vbat_bb>; /* PL7 */
+-
+-		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+-		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		status-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+-		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-
+-		host-ready-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+-		wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-RI */
+-
+-		dtr-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-DTR */
+-		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
+-		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
+-
+-		quectel,qdai = "1,1,0,1,0,0,1,1";
+-	};
+-};
+-
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 346113382..7b48126d1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -192,6 +192,17 @@ ec25_codec: ec25-codec {
+ 		sound-name-prefix = "Modem";
+ 	};
+ 
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		ring_indicator: ring-indicator {
++			label = "Ring Indicator";
++			linux,can-disable;
++			linux,code = <KEY_WAKEUP>;
++			wakeup-source;
++		};
++	};
++
+ 	i2c_csi: i2c-csi {
+ 		compatible = "i2c-gpio";
+ 		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
+@@ -264,6 +275,7 @@ reg_usb_5v: usb-5v {
+ 	reg_vbat_bb: vbat-bb {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vbat-bb";
++		regulator-always-on;
+ 		regulator-min-microvolt = <3500000>;
+ 		regulator-max-microvolt = <3500000>;
+ 		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+-- 
+2.31.1
+
diff --git a/nongnu/packages/patches/pinephone-fbcon-remove-no-op-fbcon_set_origin.patch b/nongnu/packages/patches/pinephone-fbcon-remove-no-op-fbcon_set_origin.patch
new file mode 100644
index 0000000..6491c54
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-fbcon-remove-no-op-fbcon_set_origin.patch
@@ -0,0 +1,31 @@
+--- b/drivers/video/fbdev/core/fbcon.c
++++ a/drivers/video/fbdev/core/fbcon.c
+@@ -163,6 +163,8 @@
+ 
+ #define advance_row(p, delta) (unsigned short *)((unsigned long)(p) + (delta) * vc->vc_size_row)
+ 
++static int fbcon_set_origin(struct vc_data *);
++
+ static int fbcon_cursor_noblink;
+ 
+ #define divides(a, b)	((!(a) || (b)%(a)) ? 0 : 1)
+@@ -2633,6 +2635,11 @@
+ 	}
+ }
+ 
++static int fbcon_set_origin(struct vc_data *vc)
++{
++	return 0;
++}
++
+ void fbcon_suspended(struct fb_info *info)
+ {
+ 	struct vc_data *vc = NULL;
+@@ -3103,6 +3110,7 @@
+ 	.con_font_default	= fbcon_set_def_font,
+ 	.con_font_copy 		= fbcon_copy_font,
+ 	.con_set_palette 	= fbcon_set_palette,
++	.con_set_origin 	= fbcon_set_origin,
+ 	.con_invert_region 	= fbcon_invert_region,
+ 	.con_screen_pos 	= fbcon_screen_pos,
+ 	.con_getxy 		= fbcon_getxy,
diff --git a/nongnu/packages/patches/pinephone-pro-add-modem-ri.patch.patch b/nongnu/packages/patches/pinephone-pro-add-modem-ri.patch.patch
new file mode 100644
index 0000000..c02d27f
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-pro-add-modem-ri.patch.patch
@@ -0,0 +1,52 @@
+From fc38b73e2556211d698849b78a4623dc163b7d49 Mon Sep 17 00:00:00 2001
+From: Arnaud Ferraris <arnaud.ferraris@gmail.com>
+Date: Wed, 8 Dec 2021 23:43:08 +0100
+Subject: [PATCH 3/4] arm64: dts: rk3399-pinephone-pro: add modem RI pin
+
+Taht way the modem can wake the phone on incoming calls/messages.
+
+Signed-off-by: Arnaud Ferraris <arnaud.ferraris@gmail.com>
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+index c9365e604..b3b091ea7 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -160,6 +160,21 @@ power {
+ 		};
+ 	};
+ 
++	gpio-key-ri {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&ri_pin>;
++
++		ring_indicator: ring-indicator {
++			label = "ring-indicator";
++			linux,can-disable;
++			linux,code = <KEY_WAKEUP>;
++			gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
++			wakeup-event-action = <EV_ACT_ASSERTED>;
++			wakeup-source;
++		};
++	};
++
+ 	// in1  - digital mic daughhterboard
+ 	// in2  - headset mic
+ 	// in3  - modem output  (muxed with mono)
+@@ -1150,6 +1165,10 @@ flash_pins: flash-pins {
+ 	};
+ 
+ 	modem {
++		ri_pin: ri-pin {
++			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
+ 		vcc_4g_5v_en: vcc-4g-5v-en-pin {
+ 			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+-- 
+2.34.1
+
diff --git a/nongnu/packages/patches/pinephone-pro-remove-modem-node.patch b/nongnu/packages/patches/pinephone-pro-remove-modem-node.patch
new file mode 100644
index 0000000..24be3b4
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-pro-remove-modem-node.patch
@@ -0,0 +1,86 @@
+From 60d8aedea7c8c390ee744730ab3e565ea84496fb Mon Sep 17 00:00:00 2001
+From: Danct12 <danct12@disroot.org>
+Date: Fri, 10 Dec 2021 23:01:34 +0700
+Subject: [PATCH] arm64: dts: rk3399-pinephone-pro: Remove modem node
+
+Since we don't use modem-power driver, this can be removed
+for eg25-manager.
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 40 +------------------
+ 1 file changed, 2 insertions(+), 38 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+index 61c990764..13141c643 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -326,6 +326,7 @@ vcc_4g_5v: vcc-4g-5v {
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+ 		vin-supply = <&vcc5v0_sys>;
++		regulator-always-on;
+ 	};
+ 
+ 	vcc_4g: vcc-4g {
+@@ -338,6 +339,7 @@ vcc_4g: vcc-4g {
+ 		regulator-min-microvolt = <3800000>;
+ 		regulator-max-microvolt = <3800000>;
+ 		vin-supply = <&vcc_sysin>;
++		regulator-always-on;
+ 	};
+ 
+ 	vcc1v8_codec: vcc1v8-codec-regulator {
+@@ -1058,31 +1060,6 @@ mipi_in_panel: endpoint {
+ 
+ &uart3 {
+ 	status = "okay";
+-
+-	modem {
+-		compatible = "quectel,eg25";
+-		char-device-name = "modem-power";
+-
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&modem_control_pins>;
+-
+-		power-supply = <&vcc_4g>;
+-		vbus-supply = <&vcc_4g_5v>;
+-
+-		enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; // W_DISABLE#
+-		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+-		status-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+-		pwrkey-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+-
+-		host-ready-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; // apready
+-		wakeup-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; // ri
+-
+-		dtr-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+-		cts-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+-		rts-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+-
+-		quectel,qdai = "3,0,0,4,0,0,1,1";
+-	};
+ };
+ 
+ &pmu_io_domains {
+@@ -1153,19 +1130,6 @@ vcc_4g_5v_en: vcc-4g-5v-en-pin {
+ 		vcc_4g_en: vcc-4g-en-pin {
+ 			rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+-
+-		modem_control_pins: modem-control-pins {
+-			rockchip,pins =
+-				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+ 	};
+ 
+ 	pmic {
+-- 
+2.34.1
+
diff --git a/nongnu/packages/patches/pinephone-revert-fbcon-remove-now-unusued-softback_lines-cursor-argument.patch b/nongnu/packages/patches/pinephone-revert-fbcon-remove-now-unusued-softback_lines-cursor-argument.patch
new file mode 100644
index 0000000..e7d4da5
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-revert-fbcon-remove-now-unusued-softback_lines-cursor-argument.patch
@@ -0,0 +1,150 @@
+--- b/drivers/video/fbdev/core/bitblit.c
++++ a/drivers/video/fbdev/core/bitblit.c
+@@ -234,7 +234,7 @@
+ }
+ 
+ static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++		       int softback_lines, int fg, int bg)
+-		       int fg, int bg)
+ {
+ 	struct fb_cursor cursor;
+ 	struct fbcon_ops *ops = info->fbcon_par;
+@@ -247,6 +247,15 @@
+ 
+ 	cursor.set = 0;
+ 
++	if (softback_lines) {
++		if (y + softback_lines >= vc->vc_rows) {
++			mode = CM_ERASE;
++			ops->cursor_flash = 0;
++			return;
++		} else
++			y += softback_lines;
++	}
++
+  	c = scr_readw((u16 *) vc->vc_pos);
+ 	attribute = get_attribute(info, c);
+ 	src = vc->vc_font.data + ((c & charmask) * (w * vc->vc_font.height));
+--- b/drivers/video/fbdev/core/fbcon.c
++++ a/drivers/video/fbdev/core/fbcon.c
+@@ -394,7 +394,7 @@
+ 	c = scr_readw((u16 *) vc->vc_pos);
+ 	mode = (!ops->cursor_flash || ops->cursor_state.enable) ?
+ 		CM_ERASE : CM_DRAW;
++	ops->cursor(vc, info, mode, 0, get_color(vc, info, c, 1),
+-	ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
+ 		    get_color(vc, info, c, 0));
+ 	console_unlock();
+ }
+@@ -1345,7 +1345,7 @@
+ 
+ 	ops->cursor_flash = (mode == CM_ERASE) ? 0 : 1;
+ 
++	ops->cursor(vc, info, mode, 0, get_color(vc, info, c, 1),
+-	ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
+ 		    get_color(vc, info, c, 0));
+ }
+ 
+--- b/drivers/video/fbdev/core/fbcon.h
++++ a/drivers/video/fbdev/core/fbcon.h
+@@ -62,7 +62,7 @@
+ 	void (*clear_margins)(struct vc_data *vc, struct fb_info *info,
+ 			      int color, int bottom_only);
+ 	void (*cursor)(struct vc_data *vc, struct fb_info *info, int mode,
++		       int softback_lines, int fg, int bg);
+-		       int fg, int bg);
+ 	int  (*update_start)(struct fb_info *info);
+ 	int  (*rotate_font)(struct fb_info *info, struct vc_data *vc);
+ 	struct fb_var_screeninfo var;  /* copy of the current fb_var_screeninfo */
+--- b/drivers/video/fbdev/core/fbcon_ccw.c
++++ a/drivers/video/fbdev/core/fbcon_ccw.c
+@@ -219,7 +219,7 @@
+ }
+ 
+ static void ccw_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++		       int softback_lines, int fg, int bg)
+-		       int fg, int bg)
+ {
+ 	struct fb_cursor cursor;
+ 	struct fbcon_ops *ops = info->fbcon_par;
+@@ -236,6 +236,15 @@
+ 
+ 	cursor.set = 0;
+ 
++	if (softback_lines) {
++		if (y + softback_lines >= vc->vc_rows) {
++			mode = CM_ERASE;
++			ops->cursor_flash = 0;
++			return;
++		} else
++			y += softback_lines;
++	}
++
+  	c = scr_readw((u16 *) vc->vc_pos);
+ 	attribute = get_attribute(info, c);
+ 	src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.width));
+--- b/drivers/video/fbdev/core/fbcon_cw.c
++++ a/drivers/video/fbdev/core/fbcon_cw.c
+@@ -202,7 +202,7 @@
+ }
+ 
+ static void cw_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++		      int softback_lines, int fg, int bg)
+-		      int fg, int bg)
+ {
+ 	struct fb_cursor cursor;
+ 	struct fbcon_ops *ops = info->fbcon_par;
+@@ -219,6 +219,15 @@
+ 
+ 	cursor.set = 0;
+ 
++	if (softback_lines) {
++		if (y + softback_lines >= vc->vc_rows) {
++			mode = CM_ERASE;
++			ops->cursor_flash = 0;
++			return;
++		} else
++			y += softback_lines;
++	}
++
+  	c = scr_readw((u16 *) vc->vc_pos);
+ 	attribute = get_attribute(info, c);
+ 	src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.width));
+--- b/drivers/video/fbdev/core/fbcon_ud.c
++++ a/drivers/video/fbdev/core/fbcon_ud.c
+@@ -249,7 +249,7 @@
+ }
+ 
+ static void ud_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++		      int softback_lines, int fg, int bg)
+-		      int fg, int bg)
+ {
+ 	struct fb_cursor cursor;
+ 	struct fbcon_ops *ops = info->fbcon_par;
+@@ -267,6 +267,15 @@
+ 
+ 	cursor.set = 0;
+ 
++	if (softback_lines) {
++		if (y + softback_lines >= vc->vc_rows) {
++			mode = CM_ERASE;
++			ops->cursor_flash = 0;
++			return;
++		} else
++			y += softback_lines;
++	}
++
+  	c = scr_readw((u16 *) vc->vc_pos);
+ 	attribute = get_attribute(info, c);
+ 	src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.height));
+--- b/drivers/video/fbdev/core/tileblit.c
++++ a/drivers/video/fbdev/core/tileblit.c
+@@ -80,7 +80,7 @@
+ }
+ 
+ static void tile_cursor(struct vc_data *vc, struct fb_info *info, int mode,
++			int softback_lines, int fg, int bg)
+-			int fg, int bg)
+ {
+ 	struct fb_tilecursor cursor;
+ 	int use_sw = (vc->vc_cursor_type & 0x10);
diff --git a/nongnu/packages/patches/pinephone-revert-fbcon-remove-soft-scrollback-code.patch b/nongnu/packages/patches/pinephone-revert-fbcon-remove-soft-scrollback-code.patch
new file mode 100644
index 0000000..491fbe0
--- /dev/null
+++ b/nongnu/packages/patches/pinephone-revert-fbcon-remove-soft-scrollback-code.patch
@@ -0,0 +1,500 @@
+--- b/drivers/video/fbdev/core/fbcon.c
++++ a/drivers/video/fbdev/core/fbcon.c
+@@ -124,6 +124,12 @@ static int logo_lines;
+ /* logo_shown is an index to vc_cons when >= 0; otherwise follows FBCON_LOGO
+    enums.  */
+ static int logo_shown = FBCON_LOGO_CANSHOW;
++/* Software scrollback */
++static int fbcon_softback_size = 32768;
++static unsigned long softback_buf, softback_curr;
++static unsigned long softback_in;
++static unsigned long softback_top, softback_end;
++static int softback_lines;
+ /* console mappings */
+ static unsigned int first_fb_vc;
+ static unsigned int last_fb_vc = MAX_NR_CONSOLES - 1;
+@@ -163,6 +169,8 @@ static int margin_color;
+ 
+ static const struct consw fb_con;
+ 
++#define CM_SOFTBACK	(8)
++
+ #define advance_row(p, delta) (unsigned short *)((unsigned long)(p) + (delta) * vc->vc_size_row)
+ 
+ static int fbcon_set_origin(struct vc_data *);
+@@ -347,6 +355,18 @@ static int get_color(struct vc_data *vc,
+ 	return color;
+ }
+ 
++static void fbcon_update_softback(struct vc_data *vc)
++{
++	int l = fbcon_softback_size / vc->vc_size_row;
++
++	if (l > 5)
++		softback_end = softback_buf + l * vc->vc_size_row;
++	else
++		/* Smaller scrollback makes no sense, and 0 would screw
++		   the operation totally */
++		softback_top = 0;
++}
++
+ static void fb_flashcursor(struct work_struct *work)
+ {
+ 	struct fbcon_ops *ops = container_of(work, struct fbcon_ops, cursor_work.work);
+@@ -379,7 +399,7 @@ static void fb_flashcursor(struct work_s
+ 	c = scr_readw((u16 *) vc->vc_pos);
+ 	mode = (!ops->cursor_flash || ops->cursor_state.enable) ?
+ 		CM_ERASE : CM_DRAW;
+-	ops->cursor(vc, info, mode, 0, get_color(vc, info, c, 1),
++	ops->cursor(vc, info, mode, softback_lines, get_color(vc, info, c, 1),
+ 		    get_color(vc, info, c, 0));
+ 	console_unlock();
+ 
+@@ -419,7 +439,13 @@ static int __init fb_console_setup(char
+ 		}
+ 		
+ 		if (!strncmp(options, "scrollback:", 11)) {
+-			pr_warn("Ignoring scrollback size option\n");
++			options += 11;
++			if (*options) {
++				fbcon_softback_size = simple_strtoul(options, &options, 0);
++				if (*options == 'k' || *options == 'K') {
++					fbcon_softback_size *= 1024;
++				}
++			}
+ 			continue;
+ 		}
+ 		
+@@ -959,6 +985,31 @@ static const char *fbcon_startup(void)
+ 
+ 	set_blitting_type(vc, info);
+ 
++	if (info->fix.type != FB_TYPE_TEXT) {
++		if (fbcon_softback_size) {
++			if (!softback_buf) {
++				softback_buf =
++				    (unsigned long)
++				    kvmalloc(fbcon_softback_size,
++					    GFP_KERNEL);
++				if (!softback_buf) {
++					fbcon_softback_size = 0;
++					softback_top = 0;
++				}
++			}
++		} else {
++			if (softback_buf) {
++				kvfree((void *) softback_buf);
++				softback_buf = 0;
++				softback_top = 0;
++			}
++		}
++		if (softback_buf)
++			softback_in = softback_top = softback_curr =
++			    softback_buf;
++		softback_lines = 0;
++	}
++
+ 	/* Setup default font */
+ 	if (!p->fontdata && !vc->vc_font.data) {
+ 		if (!fontname[0] || !(font = find_font(fontname)))
+@@ -1129,6 +1180,9 @@ static void fbcon_init(struct vc_data *v
+ 	if (logo)
+ 		fbcon_prepare_logo(vc, info, cols, rows, new_cols, new_rows);
+ 
++	if (vc == svc && softback_buf)
++		fbcon_update_softback(vc);
++
+ 	if (ops->rotate_font && ops->rotate_font(info, vc)) {
+ 		ops->rotate = FB_ROTATE_UR;
+ 		set_blitting_type(vc, info);
+@@ -1152,6 +1206,9 @@ static void fbcon_release_all(void)
+ 	struct fb_info *info;
+ 	int i, j, mapped;
+ 
++	kvfree((void *)softback_buf);
++	softback_buf = 0UL;
++
+ 	fbcon_for_each_registered_fb(i) {
+ 		mapped = 0;
+ 		info = fbcon_registered_fb[i];
+@@ -1312,6 +1369,7 @@ static void fbcon_cursor(struct vc_data
+ {
+ 	struct fb_info *info = fbcon_info_from_console(vc->vc_num);
+ 	struct fbcon_ops *ops = info->fbcon_par;
++	int y;
+  	int c = scr_readw((u16 *) vc->vc_pos);
+ 
+ 	ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
+@@ -1325,11 +1383,19 @@ static void fbcon_cursor(struct vc_data
+ 		fbcon_add_cursor_work(info);
+ 
+ 	ops->cursor_flash = (mode == CM_ERASE) ? 0 : 1;
++	if (mode & CM_SOFTBACK) {
++		mode &= ~CM_SOFTBACK;
++		y = softback_lines;
++	} else {
++		if (softback_lines)
++			fbcon_set_origin(vc);
++		y = 0;
++	}
+ 
+ 	if (!ops->cursor)
+ 		return;
+ 
+-	ops->cursor(vc, info, mode, 0, get_color(vc, info, c, 1),
++	ops->cursor(vc, info, mode, y, get_color(vc, info, c, 1),
+ 		    get_color(vc, info, c, 0));
+ }
+ 
+@@ -1399,6 +1465,8 @@ static void fbcon_set_disp(struct fb_inf
+ 
+ 	if (con_is_visible(vc)) {
+ 		update_screen(vc);
++		if (softback_buf)
++			fbcon_update_softback(vc);
+ 	}
+ }
+ 
+@@ -1536,6 +1604,99 @@ static __inline__ void ypan_down_redraw(
+ 	scrollback_current = 0;
+ }
+ 
++static void fbcon_redraw_softback(struct vc_data *vc, struct fbcon_display *p,
++				  long delta)
++{
++	int count = vc->vc_rows;
++	unsigned short *d, *s;
++	unsigned long n;
++	int line = 0;
++
++	d = (u16 *) softback_curr;
++	if (d == (u16 *) softback_in)
++		d = (u16 *) vc->vc_origin;
++	n = softback_curr + delta * vc->vc_size_row;
++	softback_lines -= delta;
++	if (delta < 0) {
++		if (softback_curr < softback_top && n < softback_buf) {
++			n += softback_end - softback_buf;
++			if (n < softback_top) {
++				softback_lines -=
++				    (softback_top - n) / vc->vc_size_row;
++				n = softback_top;
++			}
++		} else if (softback_curr >= softback_top
++			   && n < softback_top) {
++			softback_lines -=
++			    (softback_top - n) / vc->vc_size_row;
++			n = softback_top;
++		}
++	} else {
++		if (softback_curr > softback_in && n >= softback_end) {
++			n += softback_buf - softback_end;
++			if (n > softback_in) {
++				n = softback_in;
++				softback_lines = 0;
++			}
++		} else if (softback_curr <= softback_in && n > softback_in) {
++			n = softback_in;
++			softback_lines = 0;
++		}
++	}
++	if (n == softback_curr)
++		return;
++	softback_curr = n;
++	s = (u16 *) softback_curr;
++	if (s == (u16 *) softback_in)
++		s = (u16 *) vc->vc_origin;
++	while (count--) {
++		unsigned short *start;
++		unsigned short *le;
++		unsigned short c;
++		int x = 0;
++		unsigned short attr = 1;
++
++		start = s;
++		le = advance_row(s, 1);
++		do {
++			c = scr_readw(s);
++			if (attr != (c & 0xff00)) {
++				attr = c & 0xff00;
++				if (s > start) {
++					fbcon_putcs(vc, start, s - start,
++						    line, x);
++					x += s - start;
++					start = s;
++				}
++			}
++			if (c == scr_readw(d)) {
++				if (s > start) {
++					fbcon_putcs(vc, start, s - start,
++						    line, x);
++					x += s - start + 1;
++					start = s + 1;
++				} else {
++					x++;
++					start++;
++				}
++			}
++			s++;
++			d++;
++		} while (s < le);
++		if (s > start)
++			fbcon_putcs(vc, start, s - start, line, x);
++		line++;
++		if (d == (u16 *) softback_end)
++			d = (u16 *) softback_buf;
++		if (d == (u16 *) softback_in)
++			d = (u16 *) vc->vc_origin;
++		if (s == (u16 *) softback_end)
++			s = (u16 *) softback_buf;
++		if (s == (u16 *) softback_in)
++			s = (u16 *) vc->vc_origin;
++	}
++}
++
+ static void fbcon_redraw_move(struct vc_data *vc, struct fbcon_display *p,
+ 			      int line, int count, int dy)
+ {
+@@ -1740,6 +1901,31 @@ static void fbcon_bmove(struct vc_data *
+ 			p->vrows - p->yscroll);
+ }
+ 
++static inline void fbcon_softback_note(struct vc_data *vc, int t,
++				       int count)
++{
++	unsigned short *p;
++
++	if (vc->vc_num != fg_console)
++		return;
++	p = (unsigned short *) (vc->vc_origin + t * vc->vc_size_row);
++
++	while (count) {
++		scr_memcpyw((u16 *) softback_in, p, vc->vc_size_row);
++		count--;
++		p = advance_row(p, 1);
++		softback_in += vc->vc_size_row;
++		if (softback_in == softback_end)
++			softback_in = softback_buf;
++		if (softback_in == softback_top) {
++			softback_top += vc->vc_size_row;
++			if (softback_top == softback_end)
++				softback_top = softback_buf;
++		}
++	}
++	softback_curr = softback_in;
++}
++
+ static bool fbcon_scroll(struct vc_data *vc, unsigned int t, unsigned int b,
+ 		enum con_scroll dir, unsigned int count)
+ {
+@@ -1762,6 +1948,8 @@ static bool fbcon_scroll(struct vc_data
+ 	case SM_UP:
+ 		if (count > vc->vc_rows)	/* Maximum realistic size */
+ 			count = vc->vc_rows;
++		if (softback_top)
++			fbcon_softback_note(vc, t, count);
+ 		switch (fb_scrollmode(p)) {
+ 		case SCROLL_MOVE:
+ 			fbcon_redraw_blit(vc, info, p, t, b - t - count,
+@@ -2076,6 +2264,14 @@ static int fbcon_switch(struct vc_data *
+ 	info = fbcon_info_from_console(vc->vc_num);
+ 	ops = info->fbcon_par;
+ 
++	if (softback_top) {
++		if (softback_lines)
++			fbcon_set_origin(vc);
++		softback_top = softback_curr = softback_in = softback_buf;
++		softback_lines = 0;
++		fbcon_update_softback(vc);
++	}
++
+ 	if (logo_shown >= 0) {
+ 		struct vc_data *conp2 = vc_cons[logo_shown].d;
+ 
+@@ -2406,6 +2602,9 @@ static int fbcon_do_set_font(struct vc_d
+ 	int resize;
+ 	char *old_data = NULL;
+ 
++	if (con_is_visible(vc) && softback_lines)
++		fbcon_set_origin(vc);
++
+ 	resize = (w != vc->vc_font.width) || (h != vc->vc_font.height);
+ 	if (p->userfont)
+ 		old_data = vc->vc_font.data;
+@@ -2428,6 +2627,8 @@ static int fbcon_do_set_font(struct vc_d
+ 		cols /= w;
+ 		rows /= h;
+ 		vc_resize(vc, cols, rows);
++		if (con_is_visible(vc) && softback_buf)
++			fbcon_update_softback(vc);
+ 	} else if (con_is_visible(vc)
+ 		   && vc->vc_mode == KD_TEXT) {
+ 		fbcon_clear_margins(vc, 0);
+@@ -2582,7 +2783,19 @@ static void fbcon_set_palette(struct vc_
+ 
+ static u16 *fbcon_screen_pos(const struct vc_data *vc, int offset)
+ {
+-	return (u16 *) (vc->vc_origin + offset);
++	unsigned long p;
++	int line;
++	
++	if (vc->vc_num != fg_console || !softback_lines)
++		return (u16 *) (vc->vc_origin + offset);
++	line = offset / vc->vc_size_row;
++	if (line >= softback_lines)
++		return (u16 *) (vc->vc_origin + offset -
++				softback_lines * vc->vc_size_row);
++	p = softback_curr + offset;
++	if (p >= softback_end)
++		p += softback_buf - softback_end;
++	return (u16 *) p;
+ }
+ 
+ static unsigned long fbcon_getxy(struct vc_data *vc, unsigned long pos,
+@@ -2596,7 +2809,22 @@ static unsigned long fbcon_getxy(struct
+ 
+ 		x = offset % vc->vc_cols;
+ 		y = offset / vc->vc_cols;
++		if (vc->vc_num == fg_console)
++			y += softback_lines;
++		ret = pos + (vc->vc_cols - x) * 2;
++	} else if (vc->vc_num == fg_console && softback_lines) {
++		unsigned long offset = pos - softback_curr;
++
++		if (pos < softback_curr)
++			offset += softback_end - softback_buf;
++		offset /= 2;
++		x = offset % vc->vc_cols;
++		y = offset / vc->vc_cols;
+ 		ret = pos + (vc->vc_cols - x) * 2;
++		if (ret == softback_end)
++			ret = softback_buf;
++		if (ret == softback_in)
++			ret = vc->vc_origin;
+ 	} else {
+ 		/* Should not happen */
+ 		x = y = 0;
+@@ -2624,11 +2852,106 @@ static void fbcon_invert_region(struct v
+ 			a = ((a) & 0x88ff) | (((a) & 0x7000) >> 4) |
+ 			    (((a) & 0x0700) << 4);
+ 		scr_writew(a, p++);
++		if (p == (u16 *) softback_end)
++			p = (u16 *) softback_buf;
++		if (p == (u16 *) softback_in)
++			p = (u16 *) vc->vc_origin;
++	}
++}
++
++static void fbcon_scrolldelta(struct vc_data *vc, int lines)
++{
++	struct fb_info *info = registered_fb[con2fb_map[fg_console]];
++	struct fbcon_ops *ops = info->fbcon_par;
++	struct fbcon_display *disp = &fb_display[fg_console];
++	int offset, limit, scrollback_old;
++
++	if (softback_top) {
++		if (vc->vc_num != fg_console)
++			return;
++		if (vc->vc_mode != KD_TEXT || !lines)
++			return;
++		if (logo_shown >= 0) {
++			struct vc_data *conp2 = vc_cons[logo_shown].d;
++
++			if (conp2->vc_top == logo_lines
++			    && conp2->vc_bottom == conp2->vc_rows)
++				conp2->vc_top = 0;
++			if (logo_shown == vc->vc_num) {
++				unsigned long p, q;
++				int i;
++
++				p = softback_in;
++				q = vc->vc_origin +
++				    logo_lines * vc->vc_size_row;
++				for (i = 0; i < logo_lines; i++) {
++					if (p == softback_top)
++						break;
++					if (p == softback_buf)
++						p = softback_end;
++					p -= vc->vc_size_row;
++					q -= vc->vc_size_row;
++					scr_memcpyw((u16 *) q, (u16 *) p,
++						    vc->vc_size_row);
++				}
++				softback_in = softback_curr = p;
++				update_region(vc, vc->vc_origin,
++					      logo_lines * vc->vc_cols);
++			}
++			logo_shown = FBCON_LOGO_CANSHOW;
++		}
++		fbcon_cursor(vc, CM_ERASE | CM_SOFTBACK);
++		fbcon_redraw_softback(vc, disp, lines);
++		fbcon_cursor(vc, CM_DRAW | CM_SOFTBACK);
++		return;
+ 	}
++
++	if (!scrollback_phys_max)
++		return;
++
++	scrollback_old = scrollback_current;
++	scrollback_current -= lines;
++	if (scrollback_current < 0)
++		scrollback_current = 0;
++	else if (scrollback_current > scrollback_max)
++		scrollback_current = scrollback_max;
++	if (scrollback_current == scrollback_old)
++		return;
++
++	if (fbcon_is_inactive(vc, info))
++		return;
++
++	fbcon_cursor(vc, CM_ERASE);
++
++	offset = disp->yscroll - scrollback_current;
++	limit = disp->vrows;
++	switch (disp->scrollmode) {
++	case SCROLL_WRAP_MOVE:
++		info->var.vmode |= FB_VMODE_YWRAP;
++		break;
++	case SCROLL_PAN_MOVE:
++	case SCROLL_PAN_REDRAW:
++		limit -= vc->vc_rows;
++		info->var.vmode &= ~FB_VMODE_YWRAP;
++		break;
++	}
++	if (offset < 0)
++		offset += limit;
++	else if (offset >= limit)
++		offset -= limit;
++
++	ops->var.xoffset = 0;
++	ops->var.yoffset = offset * vc->vc_font.height;
++	ops->update_start(info);
++
++	if (!scrollback_current)
++		fbcon_cursor(vc, CM_DRAW);
+ }
+ 
+ static int fbcon_set_origin(struct vc_data *vc)
+ {
++	if (softback_lines)
++		fbcon_scrolldelta(vc, softback_lines);
+ 	return 0;
+ }
+ 
+@@ -2692,6 +3015,8 @@ static void fbcon_modechanged(struct fb_
+ 
+ 		fbcon_set_palette(vc, color_table);
+ 		update_screen(vc);
++		if (softback_buf)
++			fbcon_update_softback(vc);
+ 	}
+ }
+ 
+@@ -3154,6 +3479,7 @@ static const struct consw fb_con = {
+ 	.con_font_get 		= fbcon_get_font,
+ 	.con_font_default	= fbcon_set_def_font,
+ 	.con_set_palette 	= fbcon_set_palette,
++	.con_scrolldelta 	= fbcon_scrolldelta,
+ 	.con_set_origin 	= fbcon_set_origin,
+ 	.con_invert_region 	= fbcon_invert_region,
+ 	.con_screen_pos 	= fbcon_screen_pos,
diff --git a/nongnu/packages/patches/rk3566-pinenote_dtsi.patch b/nongnu/packages/patches/rk3566-pinenote_dtsi.patch
new file mode 100644
index 0000000..e12b84a
--- /dev/null
+++ b/nongnu/packages/patches/rk3566-pinenote_dtsi.patch
@@ -0,0 +1,167 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+index 59ac178881b3..ec7183330b40 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+@@ -51,11 +51,11 @@ battery_cell: battery-cell {
+
+ 		ocv-capacity-celsius = <20>;
+ 		ocv-capacity-table-0 = <4168000 100>,
+-				       <4109000 95>, <4066000 90>, <4023000 85>, <3985000 80>,
+-				       <3954000 75>, <3924000 70>, <3897000 65>, <3866000 60>,
+-				       <3826000 55>, <3804000 50>, <3789000 45>, <3777000 40>,
+-				       <3770000 35>, <3763000 30>, <3750000 25>, <3732000 20>,
+-				       <3710000 15>, <3680000 10>, <3670000  5>, <3500000  0>;
++					   <4109000 95>, <4066000 90>, <4023000 85>, <3985000 80>,
++					   <3954000 75>, <3924000 70>, <3897000 65>, <3866000 60>,
++					   <3826000 55>, <3804000 50>, <3789000 45>, <3777000 40>,
++					   <3770000 35>, <3763000 30>, <3750000 25>, <3732000 20>,
++					   <3710000 15>, <3680000 10>, <3670000  5>, <3500000  0>;
+ 	};
+
+ 	bt_sco_codec: bt-sco-codec {
+@@ -63,26 +63,26 @@ bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 	};
+
+-	bt-sound {
+-		compatible = "simple-audio-card";
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		simple-audio-card,name = "PineNote Bluetooth";
+-
+-		simple-audio-card,dai-link@0 {
+-			format = "i2s";
+-			frame-master = <&bt_link0_cpu>;
+-			bitclock-master = <&bt_link0_cpu>;
+-
+-			bt_link0_cpu: cpu {
+-				sound-dai = <&i2s2_2ch>;
+-			};
+-
+-			bt_link0_codec: codec {
+-				sound-dai = <&bt_sco_codec 0>;
+-			};
+-		};
+-	};
++	// bt-sound {
++		// compatible = "simple-audio-card";
++		// #address-cells = <1>;
++		// #size-cells = <0>;
++		// simple-audio-card,name = "PineNote Bluetooth";
++//
++		// simple-audio-card,dai-link@0 {
++			// format = "i2s";
++			// frame-master = <&bt_link0_cpu>;
++			// bitclock-master = <&bt_link0_cpu>;
++//
++			// bt_link0_cpu: cpu {
++				// sound-dai = <&i2s2_2ch>;
++			// };
++//
++			// bt_link0_codec: codec {
++				// sound-dai = <&bt_sco_codec 0>;
++			// };
++		// };
++	// };
+
+ 	dmic_codec: dmic-codec {
+ 		compatible = "dmic-codec";
+@@ -95,15 +95,15 @@ gpio-keys {
+ 		pinctrl-0 = <&hall_int_l>;
+ 		pinctrl-names = "default";
+
+-		cover {
+-			label = "cover";
+-			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+-			linux,input-type = <EV_SW>;
+-			linux,code = <SW_MACHINE_COVER>;
+-			linux,can-disable;
+-			wakeup-event-action = <EV_ACT_DEASSERTED>;
+-			wakeup-source;
+-		};
++		/* cover { */
++		/*	label = "cover"; */
++		/*	gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; */
++		/*	linux,input-type = <EV_SW>; */
++		/*	linux,code = <SW_MACHINE_COVER>; */
++		/*	linux,can-disable; */
++		/*	wakeup-event-action = <EV_ACT_DEASSERTED>; */
++		/*	wakeup-source; */
++		/* }; */
+ 	};
+
+ 	gpio-leds {
+@@ -166,13 +166,13 @@ sound {
+ 		simple-audio-card,name = "PineNote";
+ 		simple-audio-card,aux-devs = <&spk_amp>;
+ 		simple-audio-card,widgets = "Headphone", "Headphones",
+-					    "Speaker", "Internal Speakers";
++						"Speaker", "Internal Speakers";
+ 		simple-audio-card,routing = "Headphones", "HPOL",
+-					    "Headphones", "HPOR",
+-					    "Internal Speakers", "Speaker Amp OUTL",
+-					    "Internal Speakers", "Speaker Amp OUTR",
+-					    "Speaker Amp INL", "HPOL",
+-					    "Speaker Amp INR", "HPOR";
++						"Headphones", "HPOR",
++						"Internal Speakers", "Speaker Amp OUTL",
++						"Internal Speakers", "Speaker Amp OUTR",
++						"Speaker Amp INL", "HPOL",
++						"Speaker Amp INR", "HPOR";
+ 		simple-audio-card,pin-switches = "Internal Speakers";
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -340,7 +340,7 @@ &eink {
+
+ &gpu {
+ 	mali-supply = <&vdd_gpu_npu>;
+-	// status = "okay";
++	status = "okay";
+ };
+
+ &i2c0 {
+@@ -669,19 +669,31 @@ accelerometer@18 {
+ 		st,drdy-int-pin = <1>;
+ 		vdd-supply = <&vcc_3v3>;
+ 		vddio-supply = <&vcc_3v3>;
+-	};
+-
+-	touchscreen@24 {
+-		compatible = "cypress,tt21000";
+-		hid-descr-addr = <0x1>;
+-		reg = <0x24>;
+-		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+-		pinctrl-0 = <&ts_int_l>, <&ts_rst_l>;
+-		pinctrl-names = "default";
+-		reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+-		vdd-supply = <&vcc_3v3_pmu>;
+-	};
++		mount-matrix = "-1", "0", "0",
++					"0", "1", "0",
++					"0", "0", "1";
++	};
++
++	// from pgwipeouts dtsi
++    touchscreen@24 {
++        compatible = "cypress,tma448";
++//      compatible = "cypress,tt21000";
++        hid-descr-addr = <0x1>;
++        reg = <0x24>;
++        interrupt-parent = <&gpio0>;
++        interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
++        pinctrl-0 = <&ts_int_l>, <&ts_rst_l>;
++        pinctrl-names = "default";
++        reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++        vdd-supply = <&vcc_3v3_pmu>;
++        touchscreen-max-pressure = <46>;
++        touchscreen-min-x = <10>;
++        touchscreen-min-y = <5>;
++        touchscreen-size-x = <1863>;
++        touchscreen-size-y = <1399>;
++        touchscreen-x-mm = <1864>;
++        touchscreen-y-mm = <1400>;
++    };
+ };
+
+ &i2s1_8ch {
diff --git a/nongnu/packages/patches/rockchip_ebc_addition_extract_fbs.patch b/nongnu/packages/patches/rockchip_ebc_addition_extract_fbs.patch
new file mode 100644
index 0000000..b81081f
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_addition_extract_fbs.patch
@@ -0,0 +1,205 @@
+From c8d0d07432bd3cac0f5574165d132ec92754bb54 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev buffer
+ contents 	  to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 120 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  10 +-
+ 2 files changed, 86 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..66cc052cddcb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,72 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev ,1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next ,1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final ,1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +333,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +395,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1575,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..93289acf6d87 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,17 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/rockchip_ebc_mw_20220624.patch b/nongnu/packages/patches/rockchip_ebc_mw_20220624.patch
new file mode 100644
index 0000000..ab229c2
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_mw_20220624.patch
@@ -0,0 +1,2934 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/39] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irq from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+
+--
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/39] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+--
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/39] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+
+ 	if (!pm_runtime_status_suspended(dev))
+--
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/39] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+--
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/39] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+--
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/39] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+--
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/39] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+--
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/39] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+--
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/39] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+--
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/39] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+--
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/39] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+
+--
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/39] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+
+ 	drm_fbdev_generic_setup(drm, 0);
+
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+
+--
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/39] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+--
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/39] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+--
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/39] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+--
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/39] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+
+ 			// we need four new rokchip_ebc_area entries that we splice into
+--
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/39] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+--
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/39] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+
+ 			*split_counter++;
+--
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/39] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+
+-			*split_counter++;
++			(*split_counter)++;
+
+ 			// let the outer loop delete this area
+ 			return false;
+--
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/39] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+
+ 	area->frame_begin = frame_begin;
+--
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/39] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+
+--
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/39] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+--
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/39] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+--
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/39] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+--
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/39] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+--
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/39] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+
+ 		// try to split, otherwise continue
+--
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/39] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+--
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/39] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+
+--
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/39] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+--
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/39] [rockchip_ebc] 	* add a sysfs handler
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+--
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/39] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+
+--
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/39] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+
+--
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/39] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+--
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/39] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+--
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/39] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+--
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/39] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+--
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/39] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+
+--
+2.30.2
+
+
+From ef6c987fb94885c3678fb5ece754d813b129117a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 23 Jun 2022 20:16:15 +0200
+Subject: [PATCH 38/39] [rockchip_ebc] hopefully fix blitting of
+ odd-starting-coordinate areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 62daf5c107c4..b7358a350655 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1526,7 +1526,8 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				// want to keep here
+ 				// keep 4 higher bits
+ 				tmp_pixel = *dbuf & 0b11110000;
+-				rgb1 = tmp_pixel;
++				// shift by four pixels to the lower bits
++				rgb1 = tmp_pixel >> 4;
+ 			}
+
+ 			gray = rgb0 | rgb1 << 4;
+--
+2.30.2
+
+
+From a09adf1dcfa95c5f7a2254a9354114d4eedf3401 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 24 Jun 2022 11:34:28 +0200
+Subject: [PATCH 39/39] [rockchip_ebc] fix locking in global refresh function
+ and use DRM_EPD_WF_GC16 waveform for auto global refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b7358a350655..479a84da80c0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -413,14 +413,11 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+
+ 	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+ 	memcpy(ctx->next, ctx->final, gray4_size);
++	spin_unlock(&ctx->queue_lock);
+
+-	dma_sync_single_for_device(dev, next_handle,
+-				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, prev_handle,
+-				   gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, next_handle, gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+
+ 	reinit_completion(&ebc->display_end);
+ 	regmap_write(ebc->regmap, EBC_CONFIG_DONE,
+@@ -1146,7 +1143,16 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 				spin_lock(&ebc->refresh_once_lock);
+ 				ebc->do_one_full_refresh = false;
+ 				spin_unlock(&ebc->refresh_once_lock);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++/* 				 * @DRM_EPD_WF_A2: Fast transitions between black and white only */
++/* 				 * @DRM_EPD_WF_DU: Transitions 16-level grayscale to monochrome */
++/* 				 * @DRM_EPD_WF_DU4: Transitions 16-level grayscale to 4-level grayscale */
++/* 				 * @DRM_EPD_WF_GC16: High-quality but flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GCC16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GL16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
++/* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
++				// Not sure why only the GC16 is able to clear the ghosts from A2
++				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+--
+2.30.2
+
diff --git a/nongnu/packages/patches/rockchip_ebc_patches_mw_20220712.patch b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220712.patch
new file mode 100644
index 0000000..d027637
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220712.patch
@@ -0,0 +1,2999 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/40] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irc from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+ 
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+ 
+-- 
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/40] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+-- 
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/40] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+ 
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+ 
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+ 
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+ 
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+ 
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+ 
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	if (!pm_runtime_status_suspended(dev))
+-- 
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/40] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+-- 
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/40] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+ 
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+-- 
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/40] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+ 
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+ 
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+ 
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+ 
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+-- 
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/40] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/40] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/40] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/40] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+-- 
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/40] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+ 
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+ 
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+ 
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+ 
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+ 
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+ 
+-- 
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/40] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+ 
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+ 
+-- 
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/40] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+ 
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+ 
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+ 
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+ 
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+ 
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+-- 
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/40] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+ 
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+ 
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/40] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+ 
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+ 
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+ 
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+-- 
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/40] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+ 
+ 			// we need four new rokchip_ebc_area entries that we splice into
+-- 
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/40] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+-- 
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/40] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+ 
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+ 
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+ 			*split_counter++;
+-- 
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/40] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+-			*split_counter++;
++			(*split_counter)++;
+ 
+ 			// let the outer loop delete this area
+ 			return false;
+-- 
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/40] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+-- 
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/40] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+ 
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/40] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+ 
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+ 
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+-- 
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/40] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+ 
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+ 
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+-- 
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/40] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-- 
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/40] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+-- 
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/40] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+ 
+ 		// try to split, otherwise continue
+-- 
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/40] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+ 
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+-- 
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/40] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+ 
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+ 
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+ 
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+ 
+-- 
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/40] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-- 
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/40] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/40] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+ 
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+ 
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+ 
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+ 
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+ 
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+-- 
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/40] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+ 
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+ 
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+ 
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+ 
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+ 
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+ 
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+ 
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+ 
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+ 
+-- 
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/40] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+-- 
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/40] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/40] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+ 
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+-- 
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/40] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+ 
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+-- 
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/40] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+ 
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From ef6c987fb94885c3678fb5ece754d813b129117a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 23 Jun 2022 20:16:15 +0200
+Subject: [PATCH 38/40] [rockchip_ebc] hopefully fix blitting of
+ odd-starting-coordinate areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 62daf5c107c4..b7358a350655 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1526,7 +1526,8 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				// want to keep here
+ 				// keep 4 higher bits
+ 				tmp_pixel = *dbuf & 0b11110000;
+-				rgb1 = tmp_pixel;
++				// shift by four pixels to the lower bits
++				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+-- 
+2.30.2
+
+
+From a09adf1dcfa95c5f7a2254a9354114d4eedf3401 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 24 Jun 2022 11:34:28 +0200
+Subject: [PATCH 39/40] [rockchip_ebc] fix locking in global refresh function
+ and use DRM_EPD_WF_GC16 waveform for auto global refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b7358a350655..479a84da80c0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -413,14 +413,11 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 
+ 	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+ 	memcpy(ctx->next, ctx->final, gray4_size);
++	spin_unlock(&ctx->queue_lock);
+ 
+-	dma_sync_single_for_device(dev, next_handle,
+-				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, prev_handle,
+-				   gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, next_handle, gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+ 	regmap_write(ebc->regmap, EBC_CONFIG_DONE,
+@@ -1146,7 +1143,16 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 				spin_lock(&ebc->refresh_once_lock);
+ 				ebc->do_one_full_refresh = false;
+ 				spin_unlock(&ebc->refresh_once_lock);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++/* 				 * @DRM_EPD_WF_A2: Fast transitions between black and white only */
++/* 				 * @DRM_EPD_WF_DU: Transitions 16-level grayscale to monochrome */
++/* 				 * @DRM_EPD_WF_DU4: Transitions 16-level grayscale to 4-level grayscale */
++/* 				 * @DRM_EPD_WF_GC16: High-quality but flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GCC16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GL16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
++/* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
++				// Not sure why only the GC16 is able to clear the ghosts from A2
++				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
+
+From 55a53432c02b62613b546c561711096b8ae25b2a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 9 Jul 2022 20:38:21 +0200
+Subject: [PATCH 40/40] [rockchip_ebc] add a naive black&white mode to the ebc
+ driver and use the default_waveform for global_refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 26 ++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 479a84da80c0..db08d12ff143 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -201,6 +201,14 @@ static int limit_fb_blits = -1;
+ module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
+ 
++static bool bw_mode = false;
++module_param(bw_mode, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_mode, "black & white mode");
++
++static int bw_threshold = 7;
++module_param(bw_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_threshold, "black and white threshold");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -1152,7 +1160,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+-				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+@@ -1536,6 +1545,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
++			if (bw_mode){
++				// convert to lack and white
++				if (rgb0 >= bw_threshold){
++					rgb0 = 15;
++				} else {
++					rgb0 = 0;
++				}
++
++				if (rgb1 >= bw_threshold){
++					rgb1 = 15;
++				} else {
++					rgb1 = 0;
++				}
++			}
++
+ 			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/rockchip_ebc_patches_mw_20220730.patch b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220730.patch
new file mode 100644
index 0000000..69ff51b
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220730.patch
@@ -0,0 +1,3027 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/41] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irc from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+ 
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+ 
+-- 
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/41] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+-- 
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/41] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+ 
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+ 
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+ 
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+ 
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+ 
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+ 
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	if (!pm_runtime_status_suspended(dev))
+-- 
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/41] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+-- 
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/41] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+ 
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+-- 
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/41] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+ 
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+ 
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+ 
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+ 
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+-- 
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/41] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/41] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/41] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/41] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+-- 
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/41] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+ 
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+ 
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+ 
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+ 
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+ 
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+ 
+-- 
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/41] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+ 
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+ 
+-- 
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/41] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+ 
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+ 
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+ 
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+ 
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+ 
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+-- 
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/41] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+ 
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+ 
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/41] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+ 
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+ 
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+ 
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+-- 
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/41] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+ 
+ 			// we need four new rokchip_ebc_area entries that we splice into
+-- 
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/41] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+-- 
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/41] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+ 
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+ 
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+ 			*split_counter++;
+-- 
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/41] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+-			*split_counter++;
++			(*split_counter)++;
+ 
+ 			// let the outer loop delete this area
+ 			return false;
+-- 
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/41] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+-- 
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/41] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+ 
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/41] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+ 
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+ 
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+-- 
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/41] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+ 
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+ 
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+-- 
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/41] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-- 
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/41] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+-- 
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/41] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+ 
+ 		// try to split, otherwise continue
+-- 
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/41] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+ 
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+-- 
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/41] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+ 
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+ 
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+ 
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+ 
+-- 
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/41] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-- 
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/41] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/41] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+ 
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+ 
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+ 
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+ 
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+ 
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+-- 
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/41] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+ 
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+ 
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+ 
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+ 
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+ 
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+ 
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+ 
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+ 
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+ 
+-- 
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/41] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+-- 
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/41] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/41] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+ 
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+-- 
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/41] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+ 
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+-- 
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/41] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+ 
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From ef6c987fb94885c3678fb5ece754d813b129117a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 23 Jun 2022 20:16:15 +0200
+Subject: [PATCH 38/41] [rockchip_ebc] hopefully fix blitting of
+ odd-starting-coordinate areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 62daf5c107c4..b7358a350655 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1526,7 +1526,8 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				// want to keep here
+ 				// keep 4 higher bits
+ 				tmp_pixel = *dbuf & 0b11110000;
+-				rgb1 = tmp_pixel;
++				// shift by four pixels to the lower bits
++				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+-- 
+2.30.2
+
+
+From a09adf1dcfa95c5f7a2254a9354114d4eedf3401 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 24 Jun 2022 11:34:28 +0200
+Subject: [PATCH 39/41] [rockchip_ebc] fix locking in global refresh function
+ and use DRM_EPD_WF_GC16 waveform for auto global refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b7358a350655..479a84da80c0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -413,14 +413,11 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 
+ 	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+ 	memcpy(ctx->next, ctx->final, gray4_size);
++	spin_unlock(&ctx->queue_lock);
+ 
+-	dma_sync_single_for_device(dev, next_handle,
+-				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, prev_handle,
+-				   gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, next_handle, gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+ 	regmap_write(ebc->regmap, EBC_CONFIG_DONE,
+@@ -1146,7 +1143,16 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 				spin_lock(&ebc->refresh_once_lock);
+ 				ebc->do_one_full_refresh = false;
+ 				spin_unlock(&ebc->refresh_once_lock);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++/* 				 * @DRM_EPD_WF_A2: Fast transitions between black and white only */
++/* 				 * @DRM_EPD_WF_DU: Transitions 16-level grayscale to monochrome */
++/* 				 * @DRM_EPD_WF_DU4: Transitions 16-level grayscale to 4-level grayscale */
++/* 				 * @DRM_EPD_WF_GC16: High-quality but flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GCC16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GL16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
++/* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
++				// Not sure why only the GC16 is able to clear the ghosts from A2
++				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
+
+From 55a53432c02b62613b546c561711096b8ae25b2a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 9 Jul 2022 20:38:21 +0200
+Subject: [PATCH 40/41] [rockchip_ebc] add a naive black&white mode to the ebc
+ driver and use the default_waveform for global_refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 26 ++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 479a84da80c0..db08d12ff143 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -201,6 +201,14 @@ static int limit_fb_blits = -1;
+ module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
+ 
++static bool bw_mode = false;
++module_param(bw_mode, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_mode, "black & white mode");
++
++static int bw_threshold = 7;
++module_param(bw_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_threshold, "black and white threshold");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -1152,7 +1160,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+-				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+@@ -1536,6 +1545,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
++			if (bw_mode){
++				// convert to lack and white
++				if (rgb0 >= bw_threshold){
++					rgb0 = 15;
++				} else {
++					rgb0 = 0;
++				}
++
++				if (rgb1 >= bw_threshold){
++					rgb1 = 15;
++				} else {
++					rgb1 = 0;
++				}
++			}
++
+ 			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+-- 
+2.30.2
+
+
+From 8d8c7744be03d1698ebef3a74378bda0292811db Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 30 Jul 2022 21:47:33 +0200
+Subject: [PATCH 41/41] [rockchip_ebc] declare the waveform binary data as a
+ firmware file so it will be included automatically into the initrd images
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index db08d12ff143..990b53ef3e86 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -140,6 +140,9 @@
+ #define EBC_REFRESH_TIMEOUT		msecs_to_jiffies(3000)
+ #define EBC_SUSPEND_DELAY_MS		2000
+ 
++#define EBC_FIRMWARE		"rockchip/ebc.wbf"
++MODULE_FIRMWARE(EBC_FIRMWARE);
++
+ struct rockchip_ebc {
+ 	struct clk			*dclk;
+ 	struct clk			*hclk;
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/rockchip_ebc_patches_mw_20220804.patch b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220804.patch
new file mode 100644
index 0000000..dae74fd
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220804.patch
@@ -0,0 +1,3152 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/43] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irc from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+ 
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+ 
+-- 
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/43] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+-- 
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/43] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+ 
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+ 
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+ 
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+ 
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+ 
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+ 
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	if (!pm_runtime_status_suspended(dev))
+-- 
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/43] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+-- 
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/43] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+ 
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+-- 
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/43] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+ 
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+ 
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+ 
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+ 
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+-- 
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/43] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/43] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/43] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/43] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+-- 
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/43] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+ 
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+ 
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+ 
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+ 
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+ 
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+ 
+-- 
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/43] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+ 
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+ 
+-- 
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/43] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+ 
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+ 
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+ 
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+ 
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+ 
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+-- 
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/43] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+ 
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+ 
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/43] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+ 
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+ 
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+ 
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+-- 
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/43] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+ 
+ 			// we need four new rokchip_ebc_area entries that we splice into
+-- 
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/43] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+-- 
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/43] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+ 
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+ 
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+ 			*split_counter++;
+-- 
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/43] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+-			*split_counter++;
++			(*split_counter)++;
+ 
+ 			// let the outer loop delete this area
+ 			return false;
+-- 
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/43] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+-- 
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/43] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+ 
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/43] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+ 
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+ 
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+-- 
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/43] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+ 
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+ 
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+-- 
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/43] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-- 
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/43] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+-- 
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/43] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+ 
+ 		// try to split, otherwise continue
+-- 
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/43] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+ 
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+-- 
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/43] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+ 
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+ 
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+ 
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+ 
+-- 
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/43] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-- 
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/43] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/43] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+ 
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+ 
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+ 
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+ 
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+ 
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+-- 
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/43] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+ 
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+ 
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+ 
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+ 
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+ 
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+ 
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+ 
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+ 
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+ 
+-- 
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/43] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+-- 
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/43] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/43] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+ 
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+-- 
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/43] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+ 
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+-- 
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/43] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+ 
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From ef6c987fb94885c3678fb5ece754d813b129117a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 23 Jun 2022 20:16:15 +0200
+Subject: [PATCH 38/43] [rockchip_ebc] hopefully fix blitting of
+ odd-starting-coordinate areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 62daf5c107c4..b7358a350655 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1526,7 +1526,8 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				// want to keep here
+ 				// keep 4 higher bits
+ 				tmp_pixel = *dbuf & 0b11110000;
+-				rgb1 = tmp_pixel;
++				// shift by four pixels to the lower bits
++				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+-- 
+2.30.2
+
+
+From a09adf1dcfa95c5f7a2254a9354114d4eedf3401 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 24 Jun 2022 11:34:28 +0200
+Subject: [PATCH 39/43] [rockchip_ebc] fix locking in global refresh function
+ and use DRM_EPD_WF_GC16 waveform for auto global refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b7358a350655..479a84da80c0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -413,14 +413,11 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 
+ 	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+ 	memcpy(ctx->next, ctx->final, gray4_size);
++	spin_unlock(&ctx->queue_lock);
+ 
+-	dma_sync_single_for_device(dev, next_handle,
+-				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, prev_handle,
+-				   gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, next_handle, gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+ 	regmap_write(ebc->regmap, EBC_CONFIG_DONE,
+@@ -1146,7 +1143,16 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 				spin_lock(&ebc->refresh_once_lock);
+ 				ebc->do_one_full_refresh = false;
+ 				spin_unlock(&ebc->refresh_once_lock);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++/* 				 * @DRM_EPD_WF_A2: Fast transitions between black and white only */
++/* 				 * @DRM_EPD_WF_DU: Transitions 16-level grayscale to monochrome */
++/* 				 * @DRM_EPD_WF_DU4: Transitions 16-level grayscale to 4-level grayscale */
++/* 				 * @DRM_EPD_WF_GC16: High-quality but flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GCC16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GL16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
++/* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
++				// Not sure why only the GC16 is able to clear the ghosts from A2
++				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
+
+From 55a53432c02b62613b546c561711096b8ae25b2a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 9 Jul 2022 20:38:21 +0200
+Subject: [PATCH 40/43] [rockchip_ebc] add a naive black&white mode to the ebc
+ driver and use the default_waveform for global_refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 26 ++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 479a84da80c0..db08d12ff143 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -201,6 +201,14 @@ static int limit_fb_blits = -1;
+ module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
+ 
++static bool bw_mode = false;
++module_param(bw_mode, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_mode, "black & white mode");
++
++static int bw_threshold = 7;
++module_param(bw_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_threshold, "black and white threshold");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -1152,7 +1160,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+-				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+@@ -1536,6 +1545,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
++			if (bw_mode){
++				// convert to lack and white
++				if (rgb0 >= bw_threshold){
++					rgb0 = 15;
++				} else {
++					rgb0 = 0;
++				}
++
++				if (rgb1 >= bw_threshold){
++					rgb1 = 15;
++				} else {
++					rgb1 = 0;
++				}
++			}
++
+ 			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+-- 
+2.30.2
+
+
+From 8d8c7744be03d1698ebef3a74378bda0292811db Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 30 Jul 2022 21:47:33 +0200
+Subject: [PATCH 41/43] [rockchip_ebc] declare the waveform binary data as a
+ firmware file so it will be included automatically into the initrd images
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index db08d12ff143..990b53ef3e86 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -140,6 +140,9 @@
+ #define EBC_REFRESH_TIMEOUT		msecs_to_jiffies(3000)
+ #define EBC_SUSPEND_DELAY_MS		2000
+ 
++#define EBC_FIRMWARE		"rockchip/ebc.wbf"
++MODULE_FIRMWARE(EBC_FIRMWARE);
++
+ struct rockchip_ebc {
+ 	struct clk			*dclk;
+ 	struct clk			*hclk;
+-- 
+2.30.2
+
+
+From 7702f79c4e2ebf5e2c389c59c5776b4b157ca424 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 4 Aug 2022 21:19:05 +0200
+Subject: [PATCH 42/43] [rockchip_ebc] mirror the y-axis for panel_reflection=0
+ to ensure a usable image is shown. Note that this might not be in line with
+ the actual hardware orientation and should probably be handled by the
+ compositor!
+
+If you previously used panel_reflection=1 make sure to
+
+1) disable any libinput calibration matrix fixes for the touchscreen
+2) revert the mount-matrix option for the accelerometer
+3) not sure if any changes for the stylus are needed
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 31 ++++++++++++++++++++++---
+ 1 file changed, 28 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 990b53ef3e86..f78e6070d3dd 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1500,6 +1500,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	void *dst;
+ 	int test1, test2;
+ 
++	unsigned int delta_y;
++	unsigned int start_y;
++	unsigned int end_y2;
++
++	// -2 because we need to go to the beginning of the last line
++	start_y = panel_reflection ? src_clip->y1 : src_clip->y2 - 2;
++	delta_y = panel_reflection ? 1: -1;
++
++	if (panel_reflection)
++		end_y2 = src_clip->y2;
++	else
++		end_y2 = src_clip->y2 - 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 	// depending on the direction we must either save the first or the last bit
+@@ -1507,9 +1520,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+-	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
++	src = vaddr + start_y * src_pitch + start_x * fb->format->cpp[0];
+ 
+-	for (y = src_clip->y1; y < src_clip->y2; y++) {
++	for (y = src_clip->y1; y < end_y2; y++) {
+ 		const u32 *sbuf = src;
+ 		u8 *dbuf = dst;
+ 
+@@ -1569,7 +1582,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		}
+ 
+ 		dst += dst_pitch;
+-		src += src_pitch;
++		if (panel_reflection)
++			src += src_pitch;
++		else
++			src -= src_pitch;
+ 	}
+ 
+ 	return !!changed;
+@@ -1640,6 +1656,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x1 = plane_state->dst.x2 - x2;
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
++		else
++		{
++			// "normal" mode
++			// flip y coordinates
++			int y1 = dst_clip->y1, y2 = dst_clip->y2;
++
++			dst_clip->y1 = plane_state->dst.y2 - y2;
++			dst_clip->y2 = plane_state->dst.y2 - y1;
++		}
+ 
+ 		if (limit_fb_blits != 0){
+ 			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+-- 
+2.30.2
+
+
+From a5f8caf928a9f48075116d74d224d8607d96d69c Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 4 Aug 2022 21:38:02 +0200
+Subject: [PATCH 43/43] [rockchip_ebc] add a module parameter
+ 'refresh_waveform' that can be used to dynamically change the waveform that
+ is used for global refreshes. Can also by set via sys-file:
+
+echo 4 > /sys/module/rockchip_ebc/parameters/refresh_waveform
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f78e6070d3dd..d8e44e696084 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -196,6 +196,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int refresh_waveform = DRM_EPD_WF_GC16;
++module_param(refresh_waveform, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_waveform, "refresh waveform to use");
++
+ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+@@ -1164,7 +1168,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+ 				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++				rockchip_ebc_refresh(ebc, ctx, true, refresh_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/rockchip_ebc_patches_mw_20220808.patch b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220808.patch
new file mode 100644
index 0000000..cd31e67
--- /dev/null
+++ b/nongnu/packages/patches/rockchip_ebc_patches_mw_20220808.patch
@@ -0,0 +1,3202 @@
+From cb80d9f99f75ea1ed6c8c6b194910b6ae9574a07 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:06:31 +0200
+Subject: [PATCH 01/44] [rockchip_ebc] when doing partial refreshes, wait for
+ each frame to finish (i.e. wait for the irc from the epd controller) before
+ starting to fill in the buffers for the next frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 285f43bc6d91..d7ed954e1618 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -580,11 +580,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
+ 
+ 		if (list_empty(&areas))
+ 			break;
+@@ -597,6 +597,11 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
++		if (frame) {
++			if (!wait_for_completion_timeout(&ebc->display_end,
++							 EBC_FRAME_TIMEOUT))
++				drm_err(drm, "Frame %d timed out!\n", frame);
++		}
+ 	}
+ }
+ 
+-- 
+2.30.2
+
+
+From cdbfcec184ed55da2d55a8622240e5a30c03eb1e Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:13:57 +0200
+Subject: [PATCH 02/44] [rockchip_ebc] change the dma mappings in
+ rockchip_ebc_partial_refresh according to the documentation in
+ Documentation/core-api/dma-api.rst and use dma_map_single to get dma address
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d7ed954e1618..b0dfc493c059 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -479,8 +480,8 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 					 struct rockchip_ebc_ctx *ctx)
+ {
+-	dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	dma_addr_t prev_handle = virt_to_phys(ctx->prev);
++	// dma_addr_t next_handle = virt_to_phys(ctx->next);
++	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -489,10 +490,18 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
++	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
++	dma_addr_t phase_handles[2];
++	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
++	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
++		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
+@@ -603,6 +612,10 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+-- 
+2.30.2
+
+
+From f79e16df9a8f7853e206d5f4cb122ca231a0b2ab Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 21:25:29 +0200
+Subject: [PATCH 03/44] [rockchip_ebc] Some people (including me on a Debian
+ sid installation) see kernel panics/hangs on reboot/shutdown (and module
+ unload) with the new driver.  Investigation shows that the refresh thread
+ hangs on the schedule() command, which lead me to believe that the thread is
+ not properly shut down when the kernel module is triggered to shutdown. This
+ patch attempts to
+
+- explicitly shut down the refresh thread before termination
+- adds some control commands to quickly finish for various park/stop
+  states
+- only attempts to park the refresh thread if it is not dead yet (which
+  caused a kernel panic on shutdown)
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b0dfc493c059..4df73794281b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -13,6 +13,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/sched.h>
+ #include <linux/dma-mapping.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -760,12 +761,13 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 			rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_RESET);
+ 		}
+ 
+-		while (!kthread_should_park()) {
++		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+ 			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 
+ 			set_current_state(TASK_IDLE);
+-			if (list_empty(&ctx->queue))
++			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+ 				schedule();
++			}
+ 			__set_current_state(TASK_RUNNING);
+ 		}
+ 
+@@ -775,8 +777,9 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-
+-		kthread_parkme();
++		if (!kthread_should_stop()){
++			kthread_parkme();
++		}
+ 	}
+ 
+ 	return 0;
+@@ -925,7 +928,7 @@ static void rockchip_ebc_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ 	if (crtc_state->mode_changed)
+-		kthread_unpark(ebc->refresh_thread);
++			kthread_unpark(ebc->refresh_thread);
+ }
+ 
+ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+@@ -935,8 +938,11 @@ static void rockchip_ebc_crtc_atomic_disable(struct drm_crtc *crtc,
+ 	struct drm_crtc_state *crtc_state;
+ 
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+-	if (crtc_state->mode_changed)
+-		kthread_park(ebc->refresh_thread);
++	if (crtc_state->mode_changed){
++		if (! ((ebc->refresh_thread->__state) & (TASK_DEAD))){
++			kthread_park(ebc->refresh_thread);
++		}
++	}
+ }
+ 
+ static const struct drm_crtc_helper_funcs rockchip_ebc_crtc_helper_funcs = {
+@@ -1573,9 +1579,8 @@ static int rockchip_ebc_remove(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 
+ 	drm_dev_unregister(&ebc->drm);
+-	drm_atomic_helper_shutdown(&ebc->drm);
+-
+ 	kthread_stop(ebc->refresh_thread);
++	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+@@ -1589,6 +1594,7 @@ static void rockchip_ebc_shutdown(struct platform_device *pdev)
+ 	struct rockchip_ebc *ebc = platform_get_drvdata(pdev);
+ 	struct device *dev = &pdev->dev;
+ 
++	kthread_stop(ebc->refresh_thread);
+ 	drm_atomic_helper_shutdown(&ebc->drm);
+ 
+ 	if (!pm_runtime_status_suspended(dev))
+-- 
+2.30.2
+
+
+From 74e9d814c298f064a07ebc77b1e7ec447cc340f6 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:20:41 +0200
+Subject: [PATCH 04/44] [rockchip_ebc] use dma_sync_single_for_cpu before
+ writing to dma buffers
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4df73794281b..d8af43fe9f42 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -506,6 +506,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+ 
++		// now the CPU is allowed to change the phase buffer
++		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+@@ -533,6 +536,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+ 							 &area->clip);
+@@ -568,6 +572,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 * also ensures both phase buffers get set to 0xff.
+ 			 */
+ 			if (frame_delta > last_phase) {
++				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+-- 
+2.30.2
+
+
+From 39686d27f0193a625b6f569b8de88e1b85e92480 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 30 May 2022 22:39:00 +0200
+Subject: [PATCH 05/44] rockchip_ebc fix previous commit
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8af43fe9f42..6a0f125040df 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -507,7 +507,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		bool sync_prev = false;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+-		dma_sync_single_for_cpu(dev, phase_handle, phase_size, DMA_TO_DEVICE);
++		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+ 
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+-- 
+2.30.2
+
+
+From a347a0909bb7bde73ba53b9ebae044f7fd17466f Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:13:28 +0200
+Subject: [PATCH 06/44] [rockchip_ebc] convert all remaining uses of
+ virt_to_phys to the dma api
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 37 ++++++++++++++-----------
+ 1 file changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6a0f125040df..87deb8098d2d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -308,15 +308,17 @@ to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+ }
+ 
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+-					const struct rockchip_ebc_ctx *ctx)
++					struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					)
+ {
+ 	struct drm_device *drm = &ebc->drm;
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->next),
+ 				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, virt_to_phys(ctx->prev),
++	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+@@ -479,10 +481,11 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ }
+ 
+ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+-					 struct rockchip_ebc_ctx *ctx)
++					 struct rockchip_ebc_ctx *ctx,
++					 dma_addr_t next_handle,
++					 dma_addr_t prev_handle
++					 )
+ {
+-	// dma_addr_t next_handle = virt_to_phys(ctx->next);
+-	// dma_addr_t prev_handle = virt_to_phys(ctx->prev);
+ 	struct rockchip_ebc_area *area, *next_area;
+ 	u32 last_phase = ebc->lut.num_phases - 1;
+ 	struct drm_device *drm = &ebc->drm;
+@@ -491,9 +494,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	LIST_HEAD(areas);
+ 	u32 frame;
+ 
+-	dma_addr_t next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_addr_t prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
+-
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	phase_handles[1] = dma_map_single(dev, ctx->phase[1], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -501,7 +501,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	for (frame = 0;; frame++) {
+ 		/* Swap phase buffers to minimize latency between frames. */
+ 		u8 *phase_buffer = ctx->phase[frame % 2];
+-		// dma_addr_t phase_handle = virt_to_phys(phase_buffer);
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
+@@ -618,8 +617,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_err(drm, "Frame %d timed out!\n", frame);
+ 		}
+ 	}
+-	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+-	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+ }
+@@ -633,6 +630,8 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	u32 dsp_ctrl = 0, epd_ctrl = 0;
+ 	struct device *dev = drm->dev;
+ 	int ret, temperature;
++	dma_addr_t next_handle;
++	dma_addr_t prev_handle;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -700,15 +699,21 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 			   EBC_DSP_CTRL_DSP_LUT_MODE,
+ 			   dsp_ctrl);
+ 
++	next_handle = dma_map_single(dev, ctx->next, ctx->gray4_size, DMA_TO_DEVICE);
++	prev_handle = dma_map_single(dev, ctx->prev, ctx->gray4_size, DMA_TO_DEVICE);
++
+ 	regmap_write(ebc->regmap, EBC_WIN_MST0,
+-		     virt_to_phys(ctx->next));
++		     next_handle);
+ 	regmap_write(ebc->regmap, EBC_WIN_MST1,
+-		     virt_to_phys(ctx->prev));
++		     prev_handle);
+ 
+ 	if (global_refresh)
+-		rockchip_ebc_global_refresh(ebc, ctx);
++		rockchip_ebc_global_refresh(ebc, ctx, next_handle, prev_handle);
+ 	else
+-		rockchip_ebc_partial_refresh(ebc, ctx);
++		rockchip_ebc_partial_refresh(ebc, ctx, next_handle, prev_handle);
++
++	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
++	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+-- 
+2.30.2
+
+
+From 28a024ea077105a567f8151f182f9e29c19027e5 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:16:37 +0200
+Subject: [PATCH 07/44] [rockchip_ebc] add missing dma sinc call
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 87deb8098d2d..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,7 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 7e9e19d5342f5b9bf79d0dcddee2108d1991b7bf Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:19:14 +0200
+Subject: [PATCH 08/44] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next to get the current image. Also, delete all pending area
+ updates when doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..470638f59d43 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -786,7 +802,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		// memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From 53bf42cca1aaabf10e03a8c2e455bea16b2ac539 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 3 Jun 2022 21:27:38 +0200
+Subject: [PATCH 09/44] Revert "[rockchip_ebc] global refresh should use
+ ctx->final instead of ctx->next"
+
+This reverts commit 599a3057df02ab9188d3d6c9db5b5d6846a445c9.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 470638f59d43..0681504fc8d7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,15 +317,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
+-	struct rockchip_ebc_area *area, *next_area;
+-	LIST_HEAD(areas);
+-
+-	spin_lock(&ctx->queue_lock);
+-	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+-	memcpy(ctx->next, ctx->final, gray4_size);
+-
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -338,12 +329,6 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
+-	// while we wait for the refresh, delete all scheduled areas
+-	list_for_each_entry_safe(area, next_area, &areas, list) {
+-		list_del(&area->list);
+-		kfree(area);
+-	}
+-
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -771,7 +756,6 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
+-		memset(ctx->final, 0xff, ctx->gray4_size);
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+@@ -802,8 +786,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		// memset(ctx->next, 0xff, ctx->gray4_size);
+-		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
++		memset(ctx->next, 0xff, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+-- 
+2.30.2
+
+
+From c4babc5ae528d3c8c260fe6584f0d1812dda65ef Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:39:48 +0200
+Subject: [PATCH 10/44] [rockchip_ebc] global refresh should use ctx->final
+ instead of ctx->next     to get the current image. Also, delete all pending
+ area updates when     doing a global refresh.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 0681504fc8d7..41852c23802e 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -317,6 +317,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	u32 gray4_size = ctx->gray4_size;
+ 	struct device *dev = drm->dev;
+ 
++	struct rockchip_ebc_area *area, *next_area;
++	LIST_HEAD(areas);
++
++	spin_lock(&ctx->queue_lock);
++	list_splice_tail_init(&ctx->queue, &areas);
++	spin_unlock(&ctx->queue_lock);
++
++	memcpy(ctx->next, ctx->final, gray4_size);
++
+ 	dma_sync_single_for_device(dev, next_handle,
+ 				   gray4_size, DMA_TO_DEVICE);
+ 	dma_sync_single_for_device(dev, prev_handle,
+@@ -329,6 +338,12 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 		     ebc->dsp_start |
+ 		     EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) |
+ 		     EBC_DSP_START_DSP_FRM_START);
++	// while we wait for the refresh, delete all scheduled areas
++	list_for_each_entry_safe(area, next_area, &areas, list) {
++		list_del(&area->list);
++		kfree(area);
++	}
++
+ 	if (!wait_for_completion_timeout(&ebc->display_end,
+ 					 EBC_REFRESH_TIMEOUT))
+ 		drm_err(drm, "Refresh timed out!\n");
+@@ -756,6 +771,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 */
+ 		memset(ctx->prev, 0xff, ctx->gray4_size);
+ 		memset(ctx->next, 0xff, ctx->gray4_size);
++		memset(ctx->final, 0xff, ctx->gray4_size);
++
+ 		/* NOTE: In direct mode, the phase buffers are repurposed for
+ 		 * source driver polarity data, where the no-op value is 0. */
+ 		memset(ctx->phase[0], direct_mode ? 0 : 0xff, ctx->phase_size);
+-- 
+2.30.2
+
+
+From bb0e94904c9188675bfb6b3e264cc409c558ea72 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:44:00 +0200
+Subject: [PATCH 11/44] [rockchip_ebc] add the possibility to trigger one
+ global refresh using a module-global variable do_one_full_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 41852c23802e..b1c8f967350b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -154,6 +154,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	spinlock_t			refresh_once_lock;
++	// should this go into the ctx?
++	bool do_one_full_refresh;
+ };
+ 
+ static int default_waveform = DRM_EPD_WF_GC16;
+@@ -744,6 +747,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ {
+ 	struct rockchip_ebc *ebc = data;
+ 	struct rockchip_ebc_ctx *ctx;
++	bool one_full_refresh;
+ 
+ 	while (!kthread_should_stop()) {
+ 		/* The context will change each time the thread is unparked. */
+@@ -790,7 +794,18 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		}
+ 
+ 		while ((!kthread_should_park()) && (!kthread_should_stop())) {
+-			rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			spin_lock(&ebc->refresh_once_lock);
++			one_full_refresh = ebc->do_one_full_refresh;
++			spin_unlock(&ebc->refresh_once_lock);
++
++			if (one_full_refresh) {
++				spin_lock(&ebc->refresh_once_lock);
++				ebc->do_one_full_refresh = false;
++				spin_unlock(&ebc->refresh_once_lock);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++			} else {
++				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
++			}
+ 
+ 			set_current_state(TASK_IDLE);
+ 			if (list_empty(&ctx->queue) && (!kthread_should_stop()) && (!kthread_should_park())){
+@@ -1519,6 +1534,9 @@ static int rockchip_ebc_probe(struct platform_device *pdev)
+ 
+ 	ebc = devm_drm_dev_alloc(dev, &rockchip_ebc_drm_driver,
+ 				 struct rockchip_ebc, drm);
++
++	spin_lock_init(&ebc->refresh_once_lock);
++
+ 	if (IS_ERR(ebc))
+ 		return PTR_ERR(ebc);
+ 
+-- 
+2.30.2
+
+
+From 2b62b6c5853200cf1f1f63010d8edb56a8a08ceb Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:46:46 +0200
+Subject: [PATCH 12/44] [rockchip_ebc] add possibility to change the
+ off-screen, i.e. the content of the screen when the module is unloaded. The
+ content is read on module-load time from the firmware file
+ rockchip/rockchip_ebc_default_screen.bin. The file must be of size 1314144
+ bytes containing the 4 bit gray values for each pixel
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b1c8f967350b..edf98b048a07 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -154,6 +155,9 @@ struct rockchip_ebc {
+ 	u32				dsp_start;
+ 	bool				lut_changed;
+ 	bool				reset_complete;
++	// one screen content: 1872 * 1404 / 2
++	// the array size should probably be set dynamically...
++	char off_screen[1314144];
+ 	spinlock_t			refresh_once_lock;
+ 	// should this go into the ctx?
+ 	bool do_one_full_refresh;
+@@ -818,7 +822,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 		 * Clear the display before disabling the CRTC. Use the
+ 		 * highest-quality waveform to minimize visible artifacts.
+ 		 */
+-		memset(ctx->next, 0xff, ctx->gray4_size);
++		memcpy(ctx->final, ebc->off_screen, ctx->gray4_size);
+ 		rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 		if (!kthread_should_stop()){
+ 			kthread_parkme();
+@@ -1334,6 +1338,7 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	struct drm_device *drm = &ebc->drm;
+ 	struct drm_bridge *bridge;
+ 	int ret;
++	const struct firmware * default_offscreen;
+ 
+ 	ret = drmm_epd_lut_file_init(drm, &ebc->lut_file, "rockchip/ebc.wbf");
+ 	if (ret)
+@@ -1392,6 +1397,24 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 
+ 	drm_fbdev_generic_setup(drm, 0);
+ 
++	// check if there is a default off-screen
++	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
++	{
++		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
++		if (default_offscreen->size != 1314144)
++			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
++		else {
++			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
++			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
++		}
++	} else {
++		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
++		// fill the off-screen with some values
++		memset(ebc->off_screen, 0xff, 1314144);
++		/* memset(ebc->off_screen, 0x00, 556144); */
++	}
++	release_firmware(default_offscreen);
++
+ 	return 0;
+ }
+ 
+-- 
+2.30.2
+
+
+From f7fb21e16439c8e271786a20543c7ed74e892750 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 19:49:14 +0200
+Subject: [PATCH 13/44] [rockchip_ebc] implement a simple auto_refresh scheme
+ which triggers a global refresh after a certain area has been drawn using the
+ partial refresh path. The threshold of drawn area after which the refresh is
+ triggered can be modified using the sysfs file
+ /sys/module/rockchip_ebc/parameters/refresh_threshold. A default value of 20
+ (screen areas) seems good enough to get a refresh after 5 pages of ebook
+ reading. This seems to imply that quite a lot of duplicate draws are made for
+ each page turn (not investigated further). The auto-refresh feature is
+ deactivated by default and can be activated using the module parameter
+ auto_refresh or by writing 1 to
+ /sys/module/rockchip_ebc/parameters/auto_refresh
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index edf98b048a07..69ef34e86ba7 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -183,6 +183,14 @@ static bool skip_reset = false;
+ module_param(skip_reset, bool, 0444);
+ MODULE_PARM_DESC(skip_reset, "skip the initial display reset");
+ 
++static bool auto_refresh = false;
++module_param(auto_refresh, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(auto_refresh, "auto refresh the screen based on partial refreshed area");
++
++static int refresh_threshold = 20;
++module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -243,6 +251,7 @@ struct rockchip_ebc_ctx {
+ 	u32				gray4_size;
+ 	u32				phase_pitch;
+ 	u32				phase_size;
++	u64 area_count;
+ };
+ 
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+@@ -288,6 +297,10 @@ static struct rockchip_ebc_ctx *rockchip_ebc_ctx_alloc(u32 width, u32 height)
+ 	ctx->phase_pitch = width;
+ 	ctx->phase_size  = phase_size;
+ 
++	// we keep track of the updated area and use this value to trigger global
++	// refreshes if auto_refresh is enabled
++	ctx->area_count = 0;
++
+ 	return ctx;
+ }
+ 
+@@ -516,6 +529,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	struct device *dev = drm->dev;
+ 	LIST_HEAD(areas);
+ 	u32 frame;
++	u64 local_area_count = 0;
+ 
+ 	dma_addr_t phase_handles[2];
+ 	phase_handles[0] = dma_map_single(dev, ctx->phase[0], ctx->gray4_size, DMA_TO_DEVICE);
+@@ -558,6 +572,9 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				local_area_count += (u64) (
++					area->clip.x2 - area->clip.x1) *
++					(area->clip.y2 - area->clip.y1);
+ 				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->next,
+ 							 ctx->final,
+@@ -642,6 +659,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
++	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
++	ctx->area_count += local_area_count;
+ }
+ 
+ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+@@ -655,6 +674,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	int ret, temperature;
+ 	dma_addr_t next_handle;
+ 	dma_addr_t prev_handle;
++	int one_screen_area = 1314144;
+ 
+ 	/* Resume asynchronously while preparing to refresh. */
+ 	ret = pm_runtime_get(dev);
+@@ -738,6 +758,19 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	dma_unmap_single(dev, next_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, prev_handle, ctx->gray4_size, DMA_TO_DEVICE);
+ 
++	// do we need a full refresh
++	if (auto_refresh){
++		if (ctx->area_count >= refresh_threshold * one_screen_area){
++			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
++			spin_lock(&ebc->refresh_once_lock);
++			ebc->do_one_full_refresh = true;
++			spin_unlock(&ebc->refresh_once_lock);
++			ctx->area_count = 0;
++		}
++	} else {
++		ctx->area_count = 0;
++	}
++
+ 	/* Drive the output pins low once the refresh is complete. */
+ 	regmap_write(ebc->regmap, EBC_DSP_START,
+ 		     ebc->dsp_start |
+-- 
+2.30.2
+
+
+From eef2a823bf96f492a4d28fe0f90ea91a3c1bb936 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 4 Jun 2022 20:02:26 +0200
+Subject: [PATCH 14/44] [rockchip_ebc] Add two ioctls to the rockchip_ebc
+ module:
+
+DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH triggers a global fresh
+
+DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN can be used to supply off-screen
+content that is display on shutdown/module-unload.
+
+Corresponding ioctl structures:
+
+struct drm_rockchip_ebc_trigger_global_refresh {
+       bool trigger_global_refresh;
+};
+
+struct drm_rockchip_ebc_off_screen {
+       __u64 info1; // <- not used
+       char * ptr_screen_content;
+};
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 41 +++++++++++++++++++++++++
+ include/uapi/drm/rockchip_ebc_drm.h     | 25 +++++++++++++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 include/uapi/drm/rockchip_ebc_drm.h
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 69ef34e86ba7..9a0a238829bb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -15,6 +15,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/sched.h>
+ #include <linux/dma-mapping.h>
++#include <linux/uaccess.h>
+ #include <linux/firmware.h>
+ 
+ #include <drm/drm_atomic.h>
+@@ -29,6 +30,7 @@
+ #include <drm/drm_gem_shmem_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
++#include <drm/rockchip_ebc_drm.h>
+ 
+ #define EBC_DSP_START			0x0000
+ #define EBC_DSP_START_DSP_OUT_LOW		BIT(31)
+@@ -193,6 +195,43 @@ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples"
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
++static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_trigger_global_refresh *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++
++	if (args->trigger_global_refresh){
++		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		spin_lock(&ebc->refresh_once_lock);
++		ebc->do_one_full_refresh = true;
++		spin_unlock(&ebc->refresh_once_lock);
++		// try to trigger the refresh immediately
++		wake_up_process(ebc->refresh_thread);
++	}
++
++	return 0;
++}
++
++static int ioctl_set_off_screen(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_off_screen *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result;
++
++	copy_result = copy_from_user(&ebc->off_screen, args->ptr_screen_content, 1313144);
++
++	return 0;
++}
++
++static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
++			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
++			  DRM_RENDER_ALLOW),
++};
++
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.lastclose		= drm_fb_helper_lastclose,
+ 	DRM_GEM_SHMEM_DRIVER_OPS,
+@@ -203,6 +242,8 @@ static const struct drm_driver rockchip_ebc_drm_driver = {
+ 	.date			= "20220303",
+ 	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
+ 	.fops			= &rockchip_ebc_fops,
++	.ioctls = ioctls,
++	.num_ioctls = DRM_ROCKCHIP_EBC_NUM_IOCTLS,
+ };
+ 
+ static const struct drm_mode_config_funcs rockchip_ebc_mode_config_funcs = {
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+new file mode 100644
+index 000000000000..befa62a68be0
+--- /dev/null
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -0,0 +1,25 @@
++#ifndef __ROCKCHIP_EBC_DRM_H__
++#define __ROCKCHIP_EBC_DRM_H__
++
++#include "drm.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++
++struct drm_rockchip_ebc_trigger_global_refresh {
++	bool trigger_global_refresh;
++};
++
++struct drm_rockchip_ebc_off_screen {
++	__u64 info1;
++	char * ptr_screen_content;
++};
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++
++#define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
++#define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++
++#endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From 2855fb8cf5824b9d0d62d194440a4d7aad360c28 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 9 Jun 2022 09:56:13 +0200
+Subject: [PATCH 15/44] [rockchip_ebc] try to split overlapping areas into four
+ subareas during refresh so that the non-overlapping parts can start to
+ refresh as soon as possible and we only need to wait for the overlapping
+ part.
+
+The number of areas to split while preparing each frame can be limited.
+I'm not sure if this is really required, but I fear that too many splits
+could slow down the refresh thread.
+
+Splitting areas can produce areas that do not align with full bytes (4
+bit/byte), so we also try to account for odd start/end clips.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 176 +++++++++++++++++++++++-
+ 1 file changed, 172 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 9a0a238829bb..6f7bbe0bd70f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,10 +415,15 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+-				       u32 current_frame, u32 num_phases)
++				       u32 current_frame, u32 num_phases,
++				       struct rockchip_ebc_area *next_area,
++					   int * split_counter
++					   )
+ {
+ 	struct rockchip_ebc_area *other;
++	// by default, begin now
+ 	u32 frame_begin = current_frame;
++	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -437,11 +442,124 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
++		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = other_end;
+-			continue;
++
++			// so here we would optimally want to split the new area into three
++			// parts that do not overlap with the already-started area, and one
++			// which is overlapping. The overlapping one will be scheduled for
++			// later, but the other three should start immediately.
++
++			// if the area is equal to the clip, continue
++			if (drm_rect_equals(&area->clip, &intersection))
++				continue;
++
++			// for now, min size if 2x2
++			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++				continue;
++
++			// ok, we want to split this area and start with any partial areas
++			// that are not overlapping (well, let this be decided upon at the
++			// next outer loop - we delete this area so we need not to juggle
++			// around the four areas until we found the one that is actually
++			// overlapping)
++			int xmin, xmax, ymin, ymax, xcenter, ycenter;
++			xmin = area->clip.x1;
++			if (intersection.x1 > xmin)
++				xcenter = intersection.x1;
++			else
++				xcenter = intersection.x2;
++			xmax = area->clip.x2;
++
++			ymin = area->clip.y1;
++			if (intersection.y1 > ymin)
++				ycenter = intersection.y1;
++			else
++				ycenter = intersection.y2;
++			ymax = area->clip.y2;
++
++			if ((xmin == xcenter) | (xcenter == xmax))
++				continue;
++			if ((ymin == ycenter) | (ycenter == ymax))
++				continue;
++
++			// we do not want to overhelm the refresh thread and limit us to a
++			// certain number of splits. The rest needs to wait
++			if (*split_counter >= 6)
++				continue;
++
++			// we need four new rokchip_ebc_area entries that we splice into
++			// the list. Note that the currently next item shall be copied
++			// backwards because to prevent the outer list iteration from
++			// skipping over our newly created items.
++
++			struct rockchip_ebc_area * item1;
++			struct rockchip_ebc_area * item2;
++			struct rockchip_ebc_area * item3;
++			struct rockchip_ebc_area * item4;
++			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++			// TODO: Error checking!!!!
++			/* if (!area) */
++			/* 	return -ENOMEM; */
++
++			if (list_is_last(&area->list, areas)){
++				/* printk(KERN_INFO "adding to end of list\n"); */
++				list_add_tail(&item1->list, areas);
++				list_add_tail(&item2->list, areas);
++				list_add_tail(&item3->list, areas);
++				list_add_tail(&item4->list, areas);
++			}
++			else{
++				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
++				__list_add(&item4->list, areas, areas->next);
++				__list_add(&item3->list, areas, areas->next);
++				__list_add(&item2->list, areas, areas->next);
++				__list_add(&item1->list, areas, areas->next);
++			}
++			next_area = item1;
++
++			// now fill the areas
++			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
++			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
++			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
++			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
++
++			item1->frame_begin = EBC_FRAME_PENDING;
++			item1->clip.x1 = xmin;
++			item1->clip.x2 = xcenter;
++			item1->clip.y1 = ymin;
++			item1->clip.y2 = ycenter;
++
++			item2->frame_begin = EBC_FRAME_PENDING;
++			item2->clip.x1 = xmin;
++			item2->clip.x2 = xcenter;
++			item2->clip.y1 = ycenter + 1;
++			item2->clip.y2 = ymax;
++
++			item3->frame_begin = EBC_FRAME_PENDING;
++			item3->clip.x1 = xcenter + 1;
++			item3->clip.x2 = xmax;
++			item3->clip.y1 = ymin;
++			item3->clip.y2 = ycenter;
++
++			item4->frame_begin = EBC_FRAME_PENDING;
++			item4->clip.x1 = xcenter + 1;
++			item4->clip.x2 = xmax;
++			item4->clip.y1 = ycenter + 1;
++			item4->clip.y2 = ymax;
++
++			*split_counter++;
++
++			// let the outer loop delete this area
++			return false;
++			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -538,8 +656,18 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 				     u8 *dst, const u8 *src,
+ 				     const struct drm_rect *clip)
+ {
++	bool start_x_is_odd = clip->x1 & 1;
++	bool end_x_is_odd = clip->x2 & 1;
++	u8 first_odd;
++	u8 last_odd;
++
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
+ 	unsigned int pitch = ctx->gray4_pitch;
+ 	unsigned int width = x2_bytes - x1_bytes;
+ 	const u8 *src_line;
+@@ -550,8 +678,29 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+ 	for (y = clip->y1; y < clip->y2; y++) {
++		if (start_x_is_odd)
++			// keep only lower bit to restore it after the blitting
++			first_odd = *src_line & 0b00001111;
++		if (end_x_is_odd){
++			dst_line += pitch - 1;
++			// keep only the upper bit for restoring later
++			last_odd = *dst_line & 0b11110000;
++			dst_line -= pitch - 1;
++		}
++
+ 		memcpy(dst_line, src_line, width);
+ 
++		if (start_x_is_odd){
++			// write back the first 4 saved bits
++			*dst_line = first_odd | (*dst_line & 0b11110000);
++		}
++		if (end_x_is_odd){
++			// write back the last 4 saved bits
++			dst_line += pitch -1;
++			*dst_line = (*dst_line & 0b00001111) | last_odd;
++			dst_line -= pitch -1;
++		}
++
+ 		dst_line += pitch;
+ 		src_line += pitch;
+ 	}
+@@ -582,6 +731,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_addr_t phase_handle = phase_handles[frame % 2];
+ 		bool sync_next = false;
+ 		bool sync_prev = false;
++		int split_counter = 0;
+ 
+ 		// now the CPU is allowed to change the phase buffer
+ 		dma_sync_single_for_cpu(dev, phase_handle, ctx->phase_size, DMA_TO_DEVICE);
+@@ -601,18 +751,20 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases)) {
++							ebc->lut.num_phases, next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+ 			}
+ 
++			// we wait a little bit longer to start
+ 			frame_delta = frame - area->frame_begin;
+ 			if (frame_delta < 0)
+ 				continue;
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
++				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -1212,9 +1364,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
++	bool start_x_is_odd = src_clip->x1 & 1;
++	bool end_x_is_odd = src_clip->x2 & 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
++	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1236,7 +1392,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			/* Unbias the value for rounding to 4 bits. */
+ 			rgb0 += 0x07000000U; rgb1 += 0x07000000U;
+ 
+-			gray = rgb0 >> 28 | rgb1 >> 28 << 4;
++			rgb0 >>= 28;
++			rgb1 >>= 28;
++
++			if (x == src_clip->x1 && start_x_is_odd) {
++				// rgb0 should be filled with the content of the src pixel here
++				rgb0 = *dbuf;
++			}
++			if (x == src_clip->x2 && end_x_is_odd) {
++				// rgb1 should be filled with the content of the src pixel here
++				rgb1 = *dbuf;
++			}
++
++			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+ 		}
+-- 
+2.30.2
+
+
+From 58cb814fa8389a157c30d90511be33b75066a417 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:55:34 +0200
+Subject: [PATCH 16/44] [rockchip_ebc] add a sys parameter split_area_limit
+ (default: 12) that determines how many areas to maximally split in each
+ scheduling run. Set to 0 to disable area splitting.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 6f7bbe0bd70f..ae8f6727d05c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -193,6 +193,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int split_area_limit = 12;
++module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -488,7 +492,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 			// we do not want to overhelm the refresh thread and limit us to a
+ 			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= 6)
++			if (*split_counter >= split_area_limit)
+ 				continue;
+ 
+ 			// we need four new rokchip_ebc_area entries that we splice into
+-- 
+2.30.2
+
+
+From 2b91cc2d12d73e24bfbfae3fdc9a71e83885092d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:56:36 +0200
+Subject: [PATCH 17/44] [rockchip_ebc] fix ioctl printk message
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index ae8f6727d05c..4d6a799d7bb4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,7 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl would trigger full refresh \n");
++		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+-- 
+2.30.2
+
+
+From 314ebae7211613cce9085809115212f3dc1002a8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:14 +0200
+Subject: [PATCH 18/44] [rockchip_ebc] fix clips of split areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4d6a799d7bb4..4eb6e1e0f261 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -544,19 +544,19 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item2->frame_begin = EBC_FRAME_PENDING;
+ 			item2->clip.x1 = xmin;
+ 			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter + 1;
++			item2->clip.y1 = ycenter;
+ 			item2->clip.y2 = ymax;
+ 
+ 			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter + 1;
++			item3->clip.x1 = xcenter;
+ 			item3->clip.x2 = xmax;
+ 			item3->clip.y1 = ymin;
+ 			item3->clip.y2 = ycenter;
+ 
+ 			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter + 1;
++			item4->clip.x1 = xcenter;
+ 			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter + 1;
++			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+ 			*split_counter++;
+-- 
+2.30.2
+
+
+From 5894a086939ec2c8e88bdbe2505052d6d4fd7da4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:57:44 +0200
+Subject: [PATCH 19/44] [rockchip_ebc] fix incrementing of splitting counter
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4eb6e1e0f261..7e1558403973 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -559,7 +559,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			item4->clip.y1 = ycenter;
+ 			item4->clip.y2 = ymax;
+ 
+-			*split_counter++;
++			(*split_counter)++;
+ 
+ 			// let the outer loop delete this area
+ 			return false;
+-- 
+2.30.2
+
+
+From 325b7773c89b498de357d2952ed47ba052658296 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 20:58:17 +0200
+Subject: [PATCH 20/44] [rockchip_ebc] Fix a bug in the scheduling function
+ that could schedule an area too early: if the area overlaps with an
+ already-started area, its begin_frame will be set to the end frame of the
+ other one. However, if any frame in the list follows that can start earlier
+ (because it does not overlap or finishes at an earlier time) than this
+ earlier end frame will be used to schedule the new area.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7e1558403973..973d13ffd0d3 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -576,8 +576,9 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, start at the same time as the other area. */
+-		frame_begin = other->frame_begin;
++		/* Otherwise, the earliest start is the same time as that of the other
++		 * area. */
++		frame_begin = max(frame_begin, other->frame_begin);
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+-- 
+2.30.2
+
+
+From 350e4ec1da7cb4fe67ccb6d54b98cfead031c500 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 11 Jun 2022 21:08:19 +0200
+Subject: [PATCH 21/44] [rockchip_ebc] The current driver iteration does not
+ guarantee consistency between the list of currently-worked on damaged areas
+ (snapshot of ctx->queue taken at the beginning of each frame) and the
+ framebuffer content (ctx->final). As such it is possible that the content of
+ the framebuffer changes before a given area can be drawn, potentially leading
+ to garbled screen content. This effects is hugely dependent on the nature of
+ drawing calls emitted by individual applications. Large scheduled areas tend
+ to be good, but if an application sends large bursts of
+ overlapping/overwriting areas then bad things happen. The bug/effect is also
+ triggered if area splitting is done to increase drawing performance.
+
+For example, this can be nicely seen under Gnome when
+chaotically moving the nautilus window.
+
+This patch is not a fix but somewhat reduces the impact by moving the
+splinlock guarding the ctx->queue so it guards both the whole
+frame-prepartion phase of the partial refresh function and the
+framebuffer blitting function.
+
+An alternative that also greatly reduces the effect is to copy the whole
+framebuffer before preparing a given frame. However, this has a huge
+performance impact and thus is not feasible if we still want to to
+real-time drawings.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 973d13ffd0d3..3ef899c4779f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -744,7 +744,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
+-		spin_unlock(&ctx->queue_lock);
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+@@ -832,6 +831,8 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		dma_sync_single_for_device(dev, phase_handle,
+ 					   ctx->phase_size, DMA_TO_DEVICE);
+ 
++		spin_unlock(&ctx->queue_lock);
++
+ 		/* if (frame) { */
+ 		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
+ 		/* 					 EBC_FRAME_TIMEOUT)) */
+@@ -1448,6 +1449,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+@@ -1493,10 +1495,11 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 	}
+ 
+-	if (list_empty(&ebc_plane_state->areas))
++	if (list_empty(&ebc_plane_state->areas)){
++		spin_unlock(&ctx->queue_lock);
+ 		return;
++	}
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From b36084b7f777dda669cf8132f539c2ebb89dca45 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:05:06 +0200
+Subject: [PATCH 22/44] [rockchip_ebc] remove/comment out debug printk messages
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 3ef899c4779f..819e4bf28595 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -206,7 +206,6 @@ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+ 	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
+ 
+ 	if (args->trigger_global_refresh){
+-		printk(KERN_INFO "rockchip_ebc: ioctl triggered full refresh \n");
+ 		spin_lock(&ebc->refresh_once_lock);
+ 		ebc->do_one_full_refresh = true;
+ 		spin_unlock(&ebc->refresh_once_lock);
+@@ -427,7 +426,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	struct rockchip_ebc_area *other;
+ 	// by default, begin now
+ 	u32 frame_begin = current_frame;
+-	/* printk(KERN_INFO "scheduling area: %i-%i %i-%i\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2); */
++	//printk(KERN_INFO "scheduling area: %i-%i %i-%i (current frame: %i)\n", area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2, current_frame);
+ 
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+@@ -768,7 +767,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 
+ 			/* Copy ctx->final to ctx->next on the first frame. */
+ 			if (frame_delta == 0) {
+-				printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
++				//printk(KERN_INFO "rockchip partial refresh starting area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				local_area_count += (u64) (
+ 					area->clip.x2 - area->clip.x1) *
+ 					(area->clip.y2 - area->clip.y1);
+@@ -817,6 +816,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+ 
++				//printk(KERN_INFO "rockchip partial refresh stopping area on frame %i (%i/%i %i/%i)\n", frame, area->clip.x1, area->clip.x2, area->clip.y1, area->clip.y2);
+ 				list_del(&area->list);
+ 				kfree(area);
+ 			}
+@@ -858,7 +858,6 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-	/* printk(KERN_INFO "loca area count: %llu\n", local_area_count); */
+ 	ctx->area_count += local_area_count;
+ }
+ 
+@@ -960,7 +959,6 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc,
+ 	// do we need a full refresh
+ 	if (auto_refresh){
+ 		if (ctx->area_count >= refresh_threshold * one_screen_area){
+-			printk(KERN_INFO "rockchip: triggering full refresh due to drawn area threshold\n");
+ 			spin_lock(&ebc->refresh_once_lock);
+ 			ebc->do_one_full_refresh = true;
+ 			spin_unlock(&ebc->refresh_once_lock);
+@@ -1650,15 +1648,12 @@ static int rockchip_ebc_drm_init(struct rockchip_ebc *ebc)
+ 	// check if there is a default off-screen
+ 	if (!request_firmware(&default_offscreen, "rockchip/rockchip_ebc_default_screen.bin", drm->dev))
+ 	{
+-		printk(KERN_INFO "rockchip_ebc: default off-screen file found\n");
+ 		if (default_offscreen->size != 1314144)
+ 			drm_err(drm, "Size of default offscreen data file is not 1314144\n");
+ 		else {
+-			printk(KERN_INFO "rockchip_ebc: loading default off-screen\n");
+ 			memcpy(ebc->off_screen, default_offscreen->data, 1314144);
+ 		}
+ 	} else {
+-		printk(KERN_INFO "rockchip_ebc: no default off-screen file found\n");
+ 		// fill the off-screen with some values
+ 		memset(ebc->off_screen, 0xff, 1314144);
+ 		/* memset(ebc->off_screen, 0x00, 556144); */
+-- 
+2.30.2
+
+
+From 74cfa9aaf87f2f0b93a65052c248f0bd21b4b422 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:08:08 +0200
+Subject: [PATCH 23/44] [rockchip_ebc] move the area-splitting code to its own
+ function and hopefully fix the pointer-usage and list-handlings bugs.
+
+Also, try to split areas even if the other area was not started yet. I'm
+not really sure if this brings benefits, but the idea is that if we have
+smaller areas, then future overlaps will probably happen less.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 265 +++++++++++++++---------
+ 1 file changed, 162 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 819e4bf28595..52bf5d11ec57 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -415,11 +415,157 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 	memcpy(ctx->prev, ctx->next, gray4_size);
+ }
+ 
++/*
++ * Returns true if the area was split, false otherwise
++ */
++static int try_to_split_area(
++		struct list_head *areas,
++	    struct rockchip_ebc_area *area,
++	    struct rockchip_ebc_area *other,
++	    int * split_counter,
++	    struct rockchip_ebc_area **p_next_area,
++		struct drm_rect * intersection
++	    ){
++
++	// for now, min size if 2x2
++	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
++		return 0;
++
++	// ok, we want to split this area and start with any partial areas
++	// that are not overlapping (well, let this be decided upon at the
++	// next outer loop - we delete this area so we need not to juggle
++	// around the four areas until we found the one that is actually
++	// overlapping)
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	xmin = area->clip.x1;
++	if (intersection->x1 > xmin)
++		xcenter = intersection->x1;
++	else
++		xcenter = intersection->x2;
++	xmax = area->clip.x2;
++
++	ymin = area->clip.y1;
++	if (intersection->y1 > ymin)
++		ycenter = intersection->y1;
++	else
++		ycenter = intersection->y2;
++	ymax = area->clip.y2;
++
++	if ((xmin == xcenter) | (xcenter == xmax)){
++		no_xsplit = true;
++		split_both = false;
++	}
++	if ((ymin == ycenter) | (ycenter == ymax)){
++		no_ysplit = true;
++		split_both = false;
++	}
++
++	// can we land here at all???
++	if (no_xsplit && no_ysplit)
++		return 0;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
++	// we need four new rokchip_ebc_area entries that we splice into
++	// the list. Note that the currently next item shall be copied
++	// backwards because to prevent the outer list iteration from
++	// skipping over our newly created items.
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
++	if (split_both || no_xsplit)
++		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
++	if (split_both || no_ysplit)
++		item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
++	if (split_both)
++		item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
++
++	// TODO: Error checking!!!!
++	/* if (!area) */
++	/* 	return -ENOMEM; */
++
++	if (no_xsplit)
++		xcenter = xmax;
++
++	if (no_ysplit)
++		ycenter = ymax;
++
++	if (list_is_last(&area->list, areas)){
++		list_add_tail(&item1->list, areas);
++		if (split_both || no_xsplit)
++			list_add_tail(&item2->list, areas);
++		if (split_both || no_ysplit)
++			list_add_tail(&item3->list, areas);
++		if (split_both)
++			list_add_tail(&item4->list, areas);
++	}
++	else{
++		if (split_both)
++			__list_add(&item4->list, &area->list, area->list.next);
++		if (split_both || no_ysplit)
++			__list_add(&item3->list, &area->list, area->list.next);
++		if (split_both || no_xsplit)
++			__list_add(&item2->list, &area->list, area->list.next);
++		__list_add(&item1->list, &area->list, area->list.next);
++	}
++	*p_next_area = item1;
++
++	// now fill the areas
++
++	// always
++	item1->frame_begin = EBC_FRAME_PENDING;
++	item1->clip.x1 = xmin;
++	item1->clip.x2 = xcenter;
++	item1->clip.y1 = ymin;
++	item1->clip.y2 = ycenter;
++
++	if (split_both || no_xsplit){
++		// no xsplit
++		item2->frame_begin = EBC_FRAME_PENDING;
++		item2->clip.x1 = xmin;
++		item2->clip.x2 = xcenter;
++		item2->clip.y1 = ycenter;
++		item2->clip.y2 = ymax;
++	}
++
++	if (split_both || no_ysplit){
++		// no ysplit
++		item3->frame_begin = EBC_FRAME_PENDING;
++		item3->clip.x1 = xcenter;
++		item3->clip.x2 = xmax;
++		item3->clip.y1 = ymin;
++		item3->clip.y2 = ycenter;
++	}
++
++	if (split_both){
++		// both splits
++		item4->frame_begin = EBC_FRAME_PENDING;
++		item4->clip.x1 = xcenter;
++		item4->clip.x2 = xmax;
++		item4->clip.y1 = ycenter;
++		item4->clip.y2 = ymax;
++	}
++
++	(*split_counter)++;
++	return 1;
++}
++
+ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 				       struct rockchip_ebc_area *area,
+ 				       struct drm_device *drm,
+ 				       u32 current_frame, u32 num_phases,
+-				       struct rockchip_ebc_area *next_area,
++				       struct rockchip_ebc_area **p_next_area,
+ 					   int * split_counter
+ 					   )
+ {
+@@ -460,109 +606,13 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			if (drm_rect_equals(&area->clip, &intersection))
+ 				continue;
+ 
+-			// for now, min size if 2x2
+-			if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+-				continue;
+-
+-			// ok, we want to split this area and start with any partial areas
+-			// that are not overlapping (well, let this be decided upon at the
+-			// next outer loop - we delete this area so we need not to juggle
+-			// around the four areas until we found the one that is actually
+-			// overlapping)
+-			int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-			xmin = area->clip.x1;
+-			if (intersection.x1 > xmin)
+-				xcenter = intersection.x1;
+-			else
+-				xcenter = intersection.x2;
+-			xmax = area->clip.x2;
+-
+-			ymin = area->clip.y1;
+-			if (intersection.y1 > ymin)
+-				ycenter = intersection.y1;
+-			else
+-				ycenter = intersection.y2;
+-			ymax = area->clip.y2;
+-
+-			if ((xmin == xcenter) | (xcenter == xmax))
+-				continue;
+-			if ((ymin == ycenter) | (ycenter == ymax))
+-				continue;
+-
+-			// we do not want to overhelm the refresh thread and limit us to a
+-			// certain number of splits. The rest needs to wait
+-			if (*split_counter >= split_area_limit)
++			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++			{
++				// let the outer loop delete this area
++				return false;
++			} else {
+ 				continue;
+-
+-			// we need four new rokchip_ebc_area entries that we splice into
+-			// the list. Note that the currently next item shall be copied
+-			// backwards because to prevent the outer list iteration from
+-			// skipping over our newly created items.
+-
+-			struct rockchip_ebc_area * item1;
+-			struct rockchip_ebc_area * item2;
+-			struct rockchip_ebc_area * item3;
+-			struct rockchip_ebc_area * item4;
+-			item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+-			item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+-			item3 = kmalloc(sizeof(*item3), GFP_KERNEL);
+-			item4 = kmalloc(sizeof(*item4), GFP_KERNEL);
+-
+-			// TODO: Error checking!!!!
+-			/* if (!area) */
+-			/* 	return -ENOMEM; */
+-
+-			if (list_is_last(&area->list, areas)){
+-				/* printk(KERN_INFO "adding to end of list\n"); */
+-				list_add_tail(&item1->list, areas);
+-				list_add_tail(&item2->list, areas);
+-				list_add_tail(&item3->list, areas);
+-				list_add_tail(&item4->list, areas);
+-			}
+-			else{
+-				/* printk(KERN_INFO "splicing into the middle of the list\n"); */
+-				__list_add(&item4->list, areas, areas->next);
+-				__list_add(&item3->list, areas, areas->next);
+-				__list_add(&item2->list, areas, areas->next);
+-				__list_add(&item1->list, areas, areas->next);
+ 			}
+-			next_area = item1;
+-
+-			// now fill the areas
+-			/* printk(KERN_INFO "area1: %i %i %i %i\n", xmin, xcenter, ymin, ycenter); */
+-			/* printk(KERN_INFO "area2: %i %i %i %i\n", xmin, xcenter, ycenter, ymax); */
+-			/* printk(KERN_INFO "area3: %i %i %i %i\n", xcenter, xmax, ymin, ycenter); */
+-			/* printk(KERN_INFO "area4: %i %i %i %i\n", xcenter, xmax, ycenter, ymax); */
+-
+-			item1->frame_begin = EBC_FRAME_PENDING;
+-			item1->clip.x1 = xmin;
+-			item1->clip.x2 = xcenter;
+-			item1->clip.y1 = ymin;
+-			item1->clip.y2 = ycenter;
+-
+-			item2->frame_begin = EBC_FRAME_PENDING;
+-			item2->clip.x1 = xmin;
+-			item2->clip.x2 = xcenter;
+-			item2->clip.y1 = ycenter;
+-			item2->clip.y2 = ymax;
+-
+-			item3->frame_begin = EBC_FRAME_PENDING;
+-			item3->clip.x1 = xcenter;
+-			item3->clip.x2 = xmax;
+-			item3->clip.y1 = ymin;
+-			item3->clip.y2 = ycenter;
+-
+-			item4->frame_begin = EBC_FRAME_PENDING;
+-			item4->clip.x1 = xcenter;
+-			item4->clip.x2 = xmax;
+-			item4->clip.y1 = ycenter;
+-			item4->clip.y2 = ymax;
+-
+-			(*split_counter)++;
+-
+-			// let the outer loop delete this area
+-			return false;
+-			/* continue; */
+ 		}
+ 
+ 		/*
+@@ -578,6 +628,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		/* Otherwise, the earliest start is the same time as that of the other
+ 		 * area. */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++
++		// try to split, otherwise continue
++		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
++		{
++			// let the outer loop delete this area
++			return false;
++		} else {
++			continue;
++		}
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
+@@ -754,7 +813,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (area->frame_begin == EBC_FRAME_PENDING &&
+ 			    !rockchip_ebc_schedule_area(&areas, area, drm, frame,
+-							ebc->lut.num_phases, next_area, &split_counter)) {
++							ebc->lut.num_phases, &next_area, &split_counter)) {
+ 				list_del(&area->list);
+ 				kfree(area);
+ 				continue;
+-- 
+2.30.2
+
+
+From 491388a2f538ef97c9699c723b3b574072b0fd85 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:10:24 +0200
+Subject: [PATCH 24/44] [rockchip_ebc] remove comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 52bf5d11ec57..5d42b45abb5b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -591,7 +591,6 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		intersection = area->clip;
+ 		if (!drm_rect_intersect(&intersection, &other->clip))
+ 			continue;
+-		// we got here, so there is a collision
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-- 
+2.30.2
+
+
+From 5a177ed3f5813d31b8d2aeda46866a067f296fdd Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:13 +0200
+Subject: [PATCH 25/44] [rockchip_ebc] fix another scheduling bug: only
+ increase, but never drecrease the frame_begin number
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 5d42b45abb5b..7f5fe7252ac4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -594,7 +594,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+-			frame_begin = other_end;
++			frame_begin = max(frame_begin, other_end);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+-- 
+2.30.2
+
+
+From 35f8f647a3f7bd68cd96abee41c442abded7c2b8 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:26:32 +0200
+Subject: [PATCH 26/44] [rockchip_ebc] rework comment
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 7f5fe7252ac4..974e9d23c648 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -624,8 +624,8 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			return false;
+ 		}
+ 
+-		/* Otherwise, the earliest start is the same time as that of the other
+-		 * area. */
++		/* They do overlap but are are not equal and both not started yet, so
++		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
+ 
+ 		// try to split, otherwise continue
+-- 
+2.30.2
+
+
+From d4e78c0e92bec79bacd6e73d4df5a663eb1c2cc4 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 11:27:38 +0200
+Subject: [PATCH 27/44] [rockchip_ebc] even if its not really clear if it is
+ required, also sync the next-buffer to the cpu before using it
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 974e9d23c648..97173aeed53c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -866,10 +866,12 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 			 */
+ 			if (frame_delta > last_phase) {
+ 				dma_sync_single_for_cpu(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
++				dma_sync_single_for_cpu(dev, next_handle, gray4_size, DMA_TO_DEVICE);
+ 				rockchip_ebc_blit_pixels(ctx, ctx->prev,
+ 							 ctx->next,
+ 							 &area->clip);
+ 				sync_prev = true;
++				sync_prev = true;
+ 
+ 				drm_dbg(drm, "area %p (" DRM_RECT_FMT ") finished on %u\n",
+ 					area, DRM_RECT_ARG(&area->clip), frame);
+-- 
+2.30.2
+
+
+From ecbf9a93fc89fa8129bdd6ef0db4e39988d65d3d Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:15 +0200
+Subject: [PATCH 28/44] [rockchip_ebc] enable drawing of clips not aligned to
+ full bytes (i.e. even start/end coordinates).
+
+Needs more testing.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 62 ++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 97173aeed53c..4baefc8b5496 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1418,7 +1418,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				 const struct drm_rect *dst_clip,
+ 				 const void *vaddr,
+ 				 const struct drm_framebuffer *fb,
+-				 const struct drm_rect *src_clip)
++				 const struct drm_rect *src_clip,
++				 int adjust_x1,
++				 int adjust_x2
++				 )
+ {
+ 	unsigned int dst_pitch = ctx->gray4_pitch;
+ 	unsigned int src_pitch = fb->pitches[0];
+@@ -1428,13 +1431,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	int delta_x;
+ 	void *dst;
+ 
+-	bool start_x_is_odd = src_clip->x1 & 1;
+-	bool end_x_is_odd = src_clip->x2 & 1;
+-
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 
+-	// I think this also works if dst_clip->x1 is odd
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+ 
+@@ -1445,6 +1444,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		for (x = src_clip->x1; x < src_clip->x2; x += 2) {
+ 			u32 rgb0, rgb1;
+ 			u8 gray;
++			u8 tmp_pixel;
+ 
+ 			rgb0 = *sbuf; sbuf += delta_x;
+ 			rgb1 = *sbuf; sbuf += delta_x;
+@@ -1459,13 +1459,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			if (x == src_clip->x1 && start_x_is_odd) {
++			// Does this account for panel reflection?
++			if (x == src_clip->x1 && (adjust_x1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+-				rgb0 = *dbuf;
++				// keep lower 4 bits
++				// I'm not sure how to directly read only one byte from the u32
++				// pointer dbuf ...
++				tmp_pixel = *dbuf & 0b00001111;
++				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && end_x_is_odd) {
+-				// rgb1 should be filled with the content of the src pixel here
+-				rgb1 = *dbuf;
++			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++				// rgb1 should be filled with the content of the dst pixel we
++				// want to keep here
++				// keep 4 higher bits
++				tmp_pixel = *dbuf & 0b11110000;
++				rgb1 = tmp_pixel;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+@@ -1511,7 +1519,9 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-		int adjust;
++		int adjust_x1;
++		int adjust_x2;
++		bool clip_changed_fb;
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1519,18 +1529,20 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		/* Adjust the clips to always process full bytes (2 pixels). */
+ 		/* NOTE: in direct mode, the minimum block size is 4 pixels. */
+ 		if (direct_mode)
+-			adjust = dst_clip->x1 & 3;
++			adjust_x1 = dst_clip->x1 & 3;
+ 		else
+-			adjust = dst_clip->x1 & 1;
+-		dst_clip->x1 -= adjust;
+-		src_clip.x1  -= adjust;
++			adjust_x1 = dst_clip->x1 & 1;
++
++		dst_clip->x1 -= adjust_x1;
++		src_clip.x1  -= adjust_x1;
+ 
+ 		if (direct_mode)
+-			adjust = ((dst_clip->x2 + 3) ^ 3) & 3;
++			adjust_x2 = ((dst_clip->x2 + 3) ^ 3) & 3;
+ 		else
+-			adjust = dst_clip->x2 & 1;
+-		dst_clip->x2 += adjust;
+-		src_clip.x2  += adjust;
++			adjust_x2 = dst_clip->x2 & 1;
++
++		dst_clip->x2 += adjust_x2;
++		src_clip.x2  += adjust_x2;
+ 
+ 		if (panel_reflection) {
+ 			int x1 = dst_clip->x1, x2 = dst_clip->x2;
+@@ -1539,8 +1551,16 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		if (!rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip)) {
++		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++
++		// reverse coordinates
++		dst_clip->x1 += adjust_x1;
++		src_clip.x1  += adjust_x1;
++		dst_clip->x2 -= adjust_x2;
++		src_clip.x2  -= adjust_x2;
++
++		if (!clip_changed_fb) {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") skipped\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
+ 
+-- 
+2.30.2
+
+
+From cbe09b1efa307db0a5dd927c74f23663c2159494 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 17 Jun 2022 12:41:58 +0200
+Subject: [PATCH 29/44] [rockchip_ebc] move the queue_lock a little bit further
+ up. Not sure if this is required, but this way we lock as soon as possible in
+ the update routine.
+
+Note that this still does not prevent the damaged-area list and the
+final framebuffer content to get out of sync during ebc refreshes.
+However, it should prevent any coherency issues and ensure consistent
+framebuffer content during each frame update.
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 4baefc8b5496..15b14acbfd2b 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
+ 	ctx = to_ebc_crtc_state(crtc_state)->ctx;
+ 
++	spin_lock(&ctx->queue_lock);
+ 	drm_rect_fp_to_int(&src, &plane_state->src);
+ 	translate_x = plane_state->dst.x1 - src.x1;
+ 	translate_y = plane_state->dst.y1 - src.y1;
+@@ -1515,7 +1516,6 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
+-	spin_lock(&ctx->queue_lock);
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+-- 
+2.30.2
+
+
+From af9c4d804c7ef2efdb5ee2730b2fd9d6c6974e63 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 20 Jun 2022 13:19:31 +0200
+Subject: [PATCH 30/44] [rockchip_ebc] 	* add a sysfs handler 	 
+ (/sys/module/rockchip_ebc/parameters/limit_fb_blits) to limit the numbers of
+ framebuffer blits. The default value of -1 does not limit blits at all. Can
+ be used to investigate the buffer contents while debugging complex drawing
+ chains. 	* add an ioctl to retrieve the final, next, prev and
+ phase[0,1] 	  buffer contents to user space.
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 123 +++++++++++++++---------
+ include/uapi/drm/rockchip_ebc_drm.h     |  12 ++-
+ 2 files changed, 91 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 15b14acbfd2b..278a35209044 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -197,6 +197,10 @@ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+ 
++static int limit_fb_blits = -1;
++module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -228,11 +232,75 @@ static int ioctl_set_off_screen(struct drm_device *dev, void *data,
+ 	return 0;
+ }
+ 
++
++/**
++ * struct rockchip_ebc_ctx - context for performing display refreshes
++ *
++ * @kref: Reference count, maintained as part of the CRTC's atomic state
++ * @queue: Queue of damaged areas to be refreshed
++ * @queue_lock: Lock protecting access to @queue
++ * @prev: Display contents (Y4) before this refresh
++ * @next: Display contents (Y4) after this refresh
++ * @final: Display contents (Y4) after all pending refreshes
++ * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
++ * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
++ * @gray4_size: Size of a Y4 pixel buffer in bytes
++ * @phase_pitch: Horizontal line length of a phase buffer in bytes
++ * @phase_size: Size of a phase buffer in bytes
++ */
++struct rockchip_ebc_ctx {
++	struct kref			kref;
++	struct list_head		queue;
++	spinlock_t			queue_lock;
++	u8				*prev;
++	u8				*next;
++	u8				*final;
++	u8				*phase[2];
++	u32				gray4_pitch;
++	u32				gray4_size;
++	u32				phase_pitch;
++	u32				phase_size;
++	u64 area_count;
++};
++
++struct ebc_crtc_state {
++	struct drm_crtc_state		base;
++	struct rockchip_ebc_ctx		*ctx;
++};
++
++static inline struct ebc_crtc_state *
++to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
++{
++	return container_of(crtc_state, struct ebc_crtc_state, base);
++}
++static int ioctl_extract_fbs(struct drm_device *dev, void *data,
++		struct drm_file *file_priv)
++{
++	struct drm_rockchip_ebc_extract_fbs *args = data;
++	struct rockchip_ebc *ebc = dev_get_drvdata(dev->dev);
++	int copy_result = 0;
++	struct rockchip_ebc_ctx * ctx;
++
++	// todo: use access_ok here
++	access_ok(args->ptr_next, 1313144);
++	ctx = to_ebc_crtc_state(READ_ONCE(ebc->crtc.state))->ctx;
++	copy_result |= copy_to_user(args->ptr_prev, ctx->prev, 1313144);
++	copy_result |= copy_to_user(args->ptr_next, ctx->next, 1313144);
++	copy_result |= copy_to_user(args->ptr_final, ctx->final, 1313144);
++
++	copy_result |= copy_to_user(args->ptr_phase1, ctx->phase[0], 2 * 1313144);
++	copy_result |= copy_to_user(args->ptr_phase2, ctx->phase[1], 2 * 1313144);
++
++	return copy_result;
++}
++
+ static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_GLOBAL_REFRESH, ioctl_trigger_global_refresh,
+ 			  DRM_RENDER_ALLOW),
+ 	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_OFF_SCREEN, ioctl_set_off_screen,
+ 			  DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(ROCKCHIP_EBC_EXTRACT_FBS, ioctl_extract_fbs,
++			  DRM_RENDER_ALLOW),
+ };
+ 
+ static const struct drm_driver rockchip_ebc_drm_driver = {
+@@ -268,36 +336,6 @@ struct rockchip_ebc_area {
+ 	u32				frame_begin;
+ };
+ 
+-/**
+- * struct rockchip_ebc_ctx - context for performing display refreshes
+- *
+- * @kref: Reference count, maintained as part of the CRTC's atomic state
+- * @queue: Queue of damaged areas to be refreshed
+- * @queue_lock: Lock protecting access to @queue
+- * @prev: Display contents (Y4) before this refresh
+- * @next: Display contents (Y4) after this refresh
+- * @final: Display contents (Y4) after all pending refreshes
+- * @phase: Buffers for selecting a phase from the EBC's LUT, 1 byte/pixel
+- * @gray4_pitch: Horizontal line length of a Y4 pixel buffer in bytes
+- * @gray4_size: Size of a Y4 pixel buffer in bytes
+- * @phase_pitch: Horizontal line length of a phase buffer in bytes
+- * @phase_size: Size of a phase buffer in bytes
+- */
+-struct rockchip_ebc_ctx {
+-	struct kref			kref;
+-	struct list_head		queue;
+-	spinlock_t			queue_lock;
+-	u8				*prev;
+-	u8				*next;
+-	u8				*final;
+-	u8				*phase[2];
+-	u32				gray4_pitch;
+-	u32				gray4_size;
+-	u32				phase_pitch;
+-	u32				phase_size;
+-	u64 area_count;
+-};
+-
+ static void rockchip_ebc_ctx_free(struct rockchip_ebc_ctx *ctx)
+ {
+ 	struct rockchip_ebc_area *area;
+@@ -360,17 +398,6 @@ static void rockchip_ebc_ctx_release(struct kref *kref)
+  * CRTC
+  */
+ 
+-struct ebc_crtc_state {
+-	struct drm_crtc_state		base;
+-	struct rockchip_ebc_ctx		*ctx;
+-};
+-
+-static inline struct ebc_crtc_state *
+-to_ebc_crtc_state(struct drm_crtc_state *crtc_state)
+-{
+-	return container_of(crtc_state, struct ebc_crtc_state, base);
+-}
+-
+ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 					struct rockchip_ebc_ctx *ctx,
+ 					 dma_addr_t next_handle,
+@@ -1551,8 +1578,18 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
+ 
+-		clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+-					  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++		if (limit_fb_blits != 0){
++			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
++						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
++			// the counter should only reach 0 here, -1 can only be externally set
++			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
++		} else {
++			// we do not want to blit anything
++			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			clip_changed_fb = false;
++		}
++
+ 
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+diff --git a/include/uapi/drm/rockchip_ebc_drm.h b/include/uapi/drm/rockchip_ebc_drm.h
+index befa62a68be0..5e8c87ae6af2 100644
+--- a/include/uapi/drm/rockchip_ebc_drm.h
++++ b/include/uapi/drm/rockchip_ebc_drm.h
+@@ -17,9 +17,19 @@ struct drm_rockchip_ebc_off_screen {
+ 	char * ptr_screen_content;
+ };
+ 
+-#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x02
++struct drm_rockchip_ebc_extract_fbs {
++	char * ptr_prev;
++	char * ptr_next;
++	char * ptr_final;
++	char * ptr_phase1;
++	char * ptr_phase2;
++};
++
++
++#define DRM_ROCKCHIP_EBC_NUM_IOCTLS		0x03
+ 
+ #define DRM_IOCTL_ROCKCHIP_EBC_GLOBAL_REFRESH	DRM_IOWR(DRM_COMMAND_BASE + 0x00, struct drm_rockchip_ebc_trigger_global_refresh)
+ #define DRM_IOCTL_ROCKCHIP_EBC_OFF_SCREEN	DRM_IOWR(DRM_COMMAND_BASE + 0x01, struct drm_rockchip_ebc_off_screen)
++#define DRM_IOCTL_ROCKCHIP_EBC_EXTRACT_FBS	DRM_IOWR(DRM_COMMAND_BASE + 0x02, struct drm_rockchip_ebc_extract_fbs)
+ 
+ #endif /* __ROCKCHIP_EBC_DRM_H__*/
+-- 
+2.30.2
+
+
+From d238a50853c30c65bee6e7a6a2d5565250980247 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:17:10 +0200
+Subject: [PATCH 31/44] [rockchip_ebc] fix compiler warnings by moving variable
+ declaration to the top of the functions
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 44 ++++++++++++++-----------
+ 1 file changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 278a35209044..d0670d482432 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -453,6 +453,22 @@ static int try_to_split_area(
+ 	    struct rockchip_ebc_area **p_next_area,
+ 		struct drm_rect * intersection
+ 	    ){
++	int xmin, xmax, ymin, ymax, xcenter, ycenter;
++
++	bool no_xsplit = false;
++	bool no_ysplit = false;
++	bool split_both = true;
++
++	struct rockchip_ebc_area * item1;
++	struct rockchip_ebc_area * item2;
++	struct rockchip_ebc_area * item3;
++	struct rockchip_ebc_area * item4;
++
++	// we do not want to overhelm the refresh thread and limit us to a
++	// certain number of splits. The rest needs to wait
++	if (*split_counter >= split_area_limit)
++		return 0;
++
+ 
+ 	// for now, min size if 2x2
+ 	if ((area->clip.x2 - area->clip.x1 < 2) | (area->clip.y2 - area->clip.y1 < 2))
+@@ -463,12 +479,6 @@ static int try_to_split_area(
+ 	// next outer loop - we delete this area so we need not to juggle
+ 	// around the four areas until we found the one that is actually
+ 	// overlapping)
+-	int xmin, xmax, ymin, ymax, xcenter, ycenter;
+-
+-	bool no_xsplit = false;
+-	bool no_ysplit = false;
+-	bool split_both = true;
+-
+ 	xmin = area->clip.x1;
+ 	if (intersection->x1 > xmin)
+ 		xcenter = intersection->x1;
+@@ -496,20 +506,11 @@ static int try_to_split_area(
+ 	if (no_xsplit && no_ysplit)
+ 		return 0;
+ 
+-	// we do not want to overhelm the refresh thread and limit us to a
+-	// certain number of splits. The rest needs to wait
+-	if (*split_counter >= split_area_limit)
+-		return 0;
+-
+ 	// we need four new rokchip_ebc_area entries that we splice into
+ 	// the list. Note that the currently next item shall be copied
+ 	// backwards because to prevent the outer list iteration from
+ 	// skipping over our newly created items.
+ 
+-	struct rockchip_ebc_area * item1;
+-	struct rockchip_ebc_area * item2;
+-	struct rockchip_ebc_area * item3;
+-	struct rockchip_ebc_area * item4;
+ 	item1 = kmalloc(sizeof(*item1), GFP_KERNEL);
+ 	if (split_both || no_xsplit)
+ 		item2 = kmalloc(sizeof(*item2), GFP_KERNEL);
+@@ -752,17 +753,20 @@ static void rockchip_ebc_blit_pixels(const struct rockchip_ebc_ctx *ctx,
+ 
+ 	unsigned int x1_bytes = clip->x1 / 2;
+ 	unsigned int x2_bytes = clip->x2 / 2;
+-	// the integer division floors by default, but we want to include the last
+-	// byte (partially)
+-	if (end_x_is_odd)
+-		x2_bytes++;
+ 
+ 	unsigned int pitch = ctx->gray4_pitch;
+-	unsigned int width = x2_bytes - x1_bytes;
++	unsigned int width;
+ 	const u8 *src_line;
+ 	unsigned int y;
+ 	u8 *dst_line;
+ 
++	// the integer division floors by default, but we want to include the last
++	// byte (partially)
++	if (end_x_is_odd)
++		x2_bytes++;
++
++	width = x2_bytes - x1_bytes;
++
+ 	dst_line = dst + clip->y1 * pitch + x1_bytes;
+ 	src_line = src + clip->y1 * pitch + x1_bytes;
+ 
+-- 
+2.30.2
+
+
+From e0434586f31db9beb962f8185fd567a1eae4a879 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:19:06 +0200
+Subject: [PATCH 32/44] [rockchip_ebc] add debug printk statements but comment
+ them out
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 28 +++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d0670d482432..491efd20f2e9 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -605,24 +605,32 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	list_for_each_entry(other, areas, list) {
+ 		struct drm_rect intersection;
+ 		u32 other_end;
++		//printk(KERN_INFO "    test other area: %i-%i %i-%i\n", other->clip.x1, other->clip.x2, other->clip.y1, other->clip.y2);
+ 
+ 		/* Only consider areas before this one in the list. */
+-		if (other == area)
++		if (other == area){
++			//printk(KERN_INFO "        other==area\n");
+ 			break;
++		}
+ 
+ 		/* Skip areas that finish refresh before this area begins. */
+ 		other_end = other->frame_begin + num_phases;
+-		if (other_end <= frame_begin)
++		if (other_end <= frame_begin){
++			//printk(KERN_INFO "        other finishes before: %i %i\n", other_end, frame_begin);
+ 			continue;
++		}
+ 
+ 		/* If there is no collision, the areas are independent. */
+ 		intersection = area->clip;
+-		if (!drm_rect_intersect(&intersection, &other->clip))
++		if (!drm_rect_intersect(&intersection, &other->clip)){
++			//printk(KERN_INFO "        no collision\n");
+ 			continue;
++		}
+ 
+ 		/* If the other area already started, wait until it finishes. */
+ 		if (other->frame_begin < current_frame) {
+ 			frame_begin = max(frame_begin, other_end);
++			//printk(KERN_INFO "        other already started, setting to %i\n", frame_begin);
+ 
+ 			// so here we would optimally want to split the new area into three
+ 			// parts that do not overlap with the already-started area, and one
+@@ -630,12 +638,15 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 			// later, but the other three should start immediately.
+ 
+ 			// if the area is equal to the clip, continue
+-			if (drm_rect_equals(&area->clip, &intersection))
++			if (drm_rect_equals(&area->clip, &intersection)){
++				//printk(KERN_INFO "        intersection completely contains area\n");
+ 				continue;
++			}
+ 
+ 			if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 			{
+ 				// let the outer loop delete this area
++				//printk(KERN_INFO "        dropping after trying to split\n");
+ 				return false;
+ 			} else {
+ 				continue;
+@@ -649,17 +660,20 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 		if (drm_rect_equals(&area->clip, &intersection)) {
+ 			drm_dbg(drm, "area %p (" DRM_RECT_FMT ") dropped, inside " DRM_RECT_FMT "\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&other->clip));
++			//printk(KERN_INFO "    dropping\n");
+ 			return false;
+ 		}
+ 
+ 		/* They do overlap but are are not equal and both not started yet, so
+ 		 * they can potentially start together */
+ 		frame_begin = max(frame_begin, other->frame_begin);
++		//printk(KERN_INFO "    setting to: %i\n", frame_begin);
+ 
+ 		// try to split, otherwise continue
+ 		if (try_to_split_area(areas, area, other, split_counter, p_next_area, &intersection))
+ 		{
+ 			// let the outer loop delete this area
++			//printk(KERN_INFO "    dropping after trying to split\n");
+ 			return false;
+ 		} else {
+ 			continue;
+@@ -667,6 +681,7 @@ static bool rockchip_ebc_schedule_area(struct list_head *areas,
+ 	}
+ 
+ 	area->frame_begin = frame_begin;
++	//printk(KERN_INFO "    area scheduled to start at frame: %i (current: %i)\n", frame_begin, current_frame);
+ 
+ 	return true;
+ }
+@@ -1547,12 +1562,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 	ebc_plane_state = to_ebc_plane_state(plane_state);
+ 	vaddr = ebc_plane_state->base.data[0].vaddr;
+ 
++	//printk(KERN_INFO "new fb clips\n");
+ 	list_for_each_entry_safe(area, next_area, &ebc_plane_state->areas, list) {
+ 		struct drm_rect *dst_clip = &area->clip;
+ 		struct drm_rect src_clip = area->clip;
+ 		int adjust_x1;
+ 		int adjust_x2;
+ 		bool clip_changed_fb;
++		//printk(KERN_INFO "    checking from list: (" DRM_RECT_FMT ") \n",
++			/* DRM_RECT_ARG(&area->clip)); */
+ 
+ 		/* Convert from plane coordinates to CRTC coordinates. */
+ 		drm_rect_translate(dst_clip, translate_x, translate_y);
+@@ -1611,6 +1629,8 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		} else {
+ 			drm_dbg(plane->dev, "area %p (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
+ 				area, DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip));
++			//printk(KERN_INFO "    adding to list: (" DRM_RECT_FMT ") <= (" DRM_RECT_FMT ") blitted\n",
++				/* DRM_RECT_ARG(&area->clip), DRM_RECT_ARG(&src_clip)); */
+ 		}
+ 	}
+ 
+-- 
+2.30.2
+
+
+From bb4e13779de8d427868da024e781cff625e8287b Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:21:42 +0200
+Subject: [PATCH 33/44] [rockchip_ebc] add commented-out spin_unlock to
+ indicate old position
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 491efd20f2e9..351cae36bc4d 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -847,6 +847,7 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		/* Move the queued damage areas to the local list. */
+ 		spin_lock(&ctx->queue_lock);
+ 		list_splice_tail_init(&ctx->queue, &areas);
++		/* spin_unlock(&ctx->queue_lock); */
+ 
+ 		list_for_each_entry_safe(area, next_area, &areas, list) {
+ 			s32 frame_delta;
+-- 
+2.30.2
+
+
+From 340c5eec973094f937d67527f868a46e2729cbba Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:22:18 +0200
+Subject: [PATCH 34/44] [rockchip_ebc] not sure if this has any bad
+ consequences, but also wait on the hardware to finish the first frame
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 351cae36bc4d..e8d108727c75 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -957,11 +957,14 @@ static void rockchip_ebc_partial_refresh(struct rockchip_ebc *ebc,
+ 		regmap_write(ebc->regmap, EBC_DSP_START,
+ 			     ebc->dsp_start |
+ 			     EBC_DSP_START_DSP_FRM_START);
+-		if (frame) {
+-			if (!wait_for_completion_timeout(&ebc->display_end,
+-							 EBC_FRAME_TIMEOUT))
+-				drm_err(drm, "Frame %d timed out!\n", frame);
+-		}
++		/* if (frame) { */
++		/* 	if (!wait_for_completion_timeout(&ebc->display_end, */
++		/* 					 EBC_FRAME_TIMEOUT)) */
++		/* 		drm_err(drm, "Frame %d timed out!\n", frame); */
++		/* } */
++		if (!wait_for_completion_timeout(&ebc->display_end,
++						 EBC_FRAME_TIMEOUT))
++			drm_err(drm, "Frame %d timed out!\n", frame);
+ 	}
+ 	dma_unmap_single(dev, phase_handles[0], ctx->gray4_size, DMA_TO_DEVICE);
+ 	dma_unmap_single(dev, phase_handles[1], ctx->gray4_size, DMA_TO_DEVICE);
+-- 
+2.30.2
+
+
+From 3242d3d78bdc68361c165838f59724732cdbb0e3 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:23:03 +0200
+Subject: [PATCH 35/44] [rockchip_ebc] hopefully fix the blitting routine for
+ odd start/end coordinates and panel_reflection=1
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index e8d108727c75..f30010151c02 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1480,9 +1480,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	u8 changed = 0;
+ 	int delta_x;
+ 	void *dst;
++	int test1, test2;
+ 
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
++	// depending on the direction we must either save the first or the last bit
++	test1 = panel_reflection ? adjust_x1 : adjust_x2;
++	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+ 	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
+@@ -1509,8 +1513,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 			rgb0 >>= 28;
+ 			rgb1 >>= 28;
+ 
+-			// Does this account for panel reflection?
+-			if (x == src_clip->x1 && (adjust_x1 == 1)) {
++			if (x == src_clip->x1 && (test1 == 1)) {
+ 				// rgb0 should be filled with the content of the src pixel here
+ 				// keep lower 4 bits
+ 				// I'm not sure how to directly read only one byte from the u32
+@@ -1518,7 +1521,7 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				tmp_pixel = *dbuf & 0b00001111;
+ 				rgb0 = tmp_pixel;
+ 			}
+-			if (x == src_clip->x2 && (adjust_x2 == 1)) {
++			if (x == src_clip->x2 && (test2 == 1)) {
+ 				// rgb1 should be filled with the content of the dst pixel we
+ 				// want to keep here
+ 				// keep 4 higher bits
+-- 
+2.30.2
+
+
+From 2b41563e202a5d55e19fad1164ecfc89b1e43210 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:24:07 +0200
+Subject: [PATCH 36/44] [rockchip_ebc] add commented-out printk statements
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f30010151c02..a72d1e219691 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1608,18 +1608,17 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		}
+ 
+ 		if (limit_fb_blits != 0){
+-			printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = rockchip_ebc_blit_fb(ctx, dst_clip, vaddr,
+ 						  plane_state->fb, &src_clip, adjust_x1, adjust_x2);
+ 			// the counter should only reach 0 here, -1 can only be externally set
+ 			limit_fb_blits -= (limit_fb_blits > 0) ? 1 : 0;
+ 		} else {
+ 			// we do not want to blit anything
+-			printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
++			//printk(KERN_INFO "atomic update: not blitting: %i\n", limit_fb_blits);
+ 			clip_changed_fb = false;
+ 		}
+ 
+-
+ 		// reverse coordinates
+ 		dst_clip->x1 += adjust_x1;
+ 		src_clip.x1  += adjust_x1;
+-- 
+2.30.2
+
+
+From 917a31bb1ac2eb3adbe272fd79d40ac8b21169d9 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Wed, 22 Jun 2022 10:25:04 +0200
+Subject: [PATCH 37/44] [rockchip_ebc] add commented-out old position of lock
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index a72d1e219691..62daf5c107c4 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1645,6 +1645,7 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 		return;
+ 	}
+ 
++	/* spin_lock(&ctx->queue_lock); */
+ 	list_splice_tail_init(&ebc_plane_state->areas, &ctx->queue);
+ 	spin_unlock(&ctx->queue_lock);
+ 
+-- 
+2.30.2
+
+
+From ef6c987fb94885c3678fb5ece754d813b129117a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 23 Jun 2022 20:16:15 +0200
+Subject: [PATCH 38/44] [rockchip_ebc] hopefully fix blitting of
+ odd-starting-coordinate areas
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 62daf5c107c4..b7358a350655 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1526,7 +1526,8 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				// want to keep here
+ 				// keep 4 higher bits
+ 				tmp_pixel = *dbuf & 0b11110000;
+-				rgb1 = tmp_pixel;
++				// shift by four pixels to the lower bits
++				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
+ 			gray = rgb0 | rgb1 << 4;
+-- 
+2.30.2
+
+
+From a09adf1dcfa95c5f7a2254a9354114d4eedf3401 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Fri, 24 Jun 2022 11:34:28 +0200
+Subject: [PATCH 39/44] [rockchip_ebc] fix locking in global refresh function
+ and use DRM_EPD_WF_GC16 waveform for auto global refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index b7358a350655..479a84da80c0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -413,14 +413,11 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc,
+ 
+ 	spin_lock(&ctx->queue_lock);
+ 	list_splice_tail_init(&ctx->queue, &areas);
+-	spin_unlock(&ctx->queue_lock);
+-
+ 	memcpy(ctx->next, ctx->final, gray4_size);
++	spin_unlock(&ctx->queue_lock);
+ 
+-	dma_sync_single_for_device(dev, next_handle,
+-				   gray4_size, DMA_TO_DEVICE);
+-	dma_sync_single_for_device(dev, prev_handle,
+-				   gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, next_handle, gray4_size, DMA_TO_DEVICE);
++	dma_sync_single_for_device(dev, prev_handle, gray4_size, DMA_TO_DEVICE);
+ 
+ 	reinit_completion(&ebc->display_end);
+ 	regmap_write(ebc->regmap, EBC_CONFIG_DONE,
+@@ -1146,7 +1143,16 @@ static int rockchip_ebc_refresh_thread(void *data)
+ 				spin_lock(&ebc->refresh_once_lock);
+ 				ebc->do_one_full_refresh = false;
+ 				spin_unlock(&ebc->refresh_once_lock);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++/* 				 * @DRM_EPD_WF_A2: Fast transitions between black and white only */
++/* 				 * @DRM_EPD_WF_DU: Transitions 16-level grayscale to monochrome */
++/* 				 * @DRM_EPD_WF_DU4: Transitions 16-level grayscale to 4-level grayscale */
++/* 				 * @DRM_EPD_WF_GC16: High-quality but flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GCC16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GL16: Less flashy 16-level grayscale */
++/* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
++/* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
++				// Not sure why only the GC16 is able to clear the ghosts from A2
++				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
+
+From 55a53432c02b62613b546c561711096b8ae25b2a Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 9 Jul 2022 20:38:21 +0200
+Subject: [PATCH 40/44] [rockchip_ebc] add a naive black&white mode to the ebc
+ driver and use the default_waveform for global_refreshes
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 26 ++++++++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 479a84da80c0..db08d12ff143 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -201,6 +201,14 @@ static int limit_fb_blits = -1;
+ module_param(limit_fb_blits, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many fb blits to allow. -1 does not limit");
+ 
++static bool bw_mode = false;
++module_param(bw_mode, bool, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_mode, "black & white mode");
++
++static int bw_threshold = 7;
++module_param(bw_threshold, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(bw_threshold, "black and white threshold");
++
+ DEFINE_DRM_GEM_FOPS(rockchip_ebc_fops);
+ 
+ static int ioctl_trigger_global_refresh(struct drm_device *dev, void *data,
+@@ -1152,7 +1160,8 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLR16: Less flashy 16-level grayscale, plus anti-ghosting */
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+-				rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
++				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+@@ -1536,6 +1545,21 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 				rgb1 = tmp_pixel >> 4;
+ 			}
+ 
++			if (bw_mode){
++				// convert to lack and white
++				if (rgb0 >= bw_threshold){
++					rgb0 = 15;
++				} else {
++					rgb0 = 0;
++				}
++
++				if (rgb1 >= bw_threshold){
++					rgb1 = 15;
++				} else {
++					rgb1 = 0;
++				}
++			}
++
+ 			gray = rgb0 | rgb1 << 4;
+ 			changed |= gray ^ *dbuf;
+ 			*dbuf++ = gray;
+-- 
+2.30.2
+
+
+From 8d8c7744be03d1698ebef3a74378bda0292811db Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Sat, 30 Jul 2022 21:47:33 +0200
+Subject: [PATCH 41/44] [rockchip_ebc] declare the waveform binary data as a
+ firmware file so it will be included automatically into the initrd images
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index db08d12ff143..990b53ef3e86 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -140,6 +140,9 @@
+ #define EBC_REFRESH_TIMEOUT		msecs_to_jiffies(3000)
+ #define EBC_SUSPEND_DELAY_MS		2000
+ 
++#define EBC_FIRMWARE		"rockchip/ebc.wbf"
++MODULE_FIRMWARE(EBC_FIRMWARE);
++
+ struct rockchip_ebc {
+ 	struct clk			*dclk;
+ 	struct clk			*hclk;
+-- 
+2.30.2
+
+
+From 7702f79c4e2ebf5e2c389c59c5776b4b157ca424 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 4 Aug 2022 21:19:05 +0200
+Subject: [PATCH 42/44] [rockchip_ebc] mirror the y-axis for panel_reflection=0
+ to ensure a usable image is shown. Note that this might not be in line with
+ the actual hardware orientation and should probably be handled by the
+ compositor!
+
+If you previously used panel_reflection=1 make sure to
+
+1) disable any libinput calibration matrix fixes for the touchscreen
+2) revert the mount-matrix option for the accelerometer
+3) not sure if any changes for the stylus are needed
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 31 ++++++++++++++++++++++---
+ 1 file changed, 28 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index 990b53ef3e86..f78e6070d3dd 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1500,6 +1500,19 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	void *dst;
+ 	int test1, test2;
+ 
++	unsigned int delta_y;
++	unsigned int start_y;
++	unsigned int end_y2;
++
++	// -2 because we need to go to the beginning of the last line
++	start_y = panel_reflection ? src_clip->y1 : src_clip->y2 - 2;
++	delta_y = panel_reflection ? 1: -1;
++
++	if (panel_reflection)
++		end_y2 = src_clip->y2;
++	else
++		end_y2 = src_clip->y2 - 1;
++
+ 	delta_x = panel_reflection ? -1 : 1;
+ 	start_x = panel_reflection ? src_clip->x2 - 1 : src_clip->x1;
+ 	// depending on the direction we must either save the first or the last bit
+@@ -1507,9 +1520,9 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	test2 = panel_reflection ? adjust_x2 : adjust_x1;
+ 
+ 	dst = ctx->final + dst_clip->y1 * dst_pitch + dst_clip->x1 / 2;
+-	src = vaddr + src_clip->y1 * src_pitch + start_x * fb->format->cpp[0];
++	src = vaddr + start_y * src_pitch + start_x * fb->format->cpp[0];
+ 
+-	for (y = src_clip->y1; y < src_clip->y2; y++) {
++	for (y = src_clip->y1; y < end_y2; y++) {
+ 		const u32 *sbuf = src;
+ 		u8 *dbuf = dst;
+ 
+@@ -1569,7 +1582,10 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 		}
+ 
+ 		dst += dst_pitch;
+-		src += src_pitch;
++		if (panel_reflection)
++			src += src_pitch;
++		else
++			src -= src_pitch;
+ 	}
+ 
+ 	return !!changed;
+@@ -1640,6 +1656,15 @@ static void rockchip_ebc_plane_atomic_update(struct drm_plane *plane,
+ 			dst_clip->x1 = plane_state->dst.x2 - x2;
+ 			dst_clip->x2 = plane_state->dst.x2 - x1;
+ 		}
++		else
++		{
++			// "normal" mode
++			// flip y coordinates
++			int y1 = dst_clip->y1, y2 = dst_clip->y2;
++
++			dst_clip->y1 = plane_state->dst.y2 - y2;
++			dst_clip->y2 = plane_state->dst.y2 - y1;
++		}
+ 
+ 		if (limit_fb_blits != 0){
+ 			//printk(KERN_INFO "atomic update: blitting: %i\n", limit_fb_blits);
+-- 
+2.30.2
+
+
+From a5f8caf928a9f48075116d74d224d8607d96d69c Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Thu, 4 Aug 2022 21:38:02 +0200
+Subject: [PATCH 43/44] [rockchip_ebc] add a module parameter
+ 'refresh_waveform' that can be used to dynamically change the waveform that
+ is used for global refreshes. Can also by set via sys-file:
+
+echo 4 > /sys/module/rockchip_ebc/parameters/refresh_waveform
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index f78e6070d3dd..d8e44e696084 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -196,6 +196,10 @@ static int refresh_threshold = 20;
+ module_param(refresh_threshold, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(refresh_threshold, "refresh threshold in screen area multiples");
+ 
++static int refresh_waveform = DRM_EPD_WF_GC16;
++module_param(refresh_waveform, int, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(refresh_waveform, "refresh waveform to use");
++
+ static int split_area_limit = 12;
+ module_param(split_area_limit, int, S_IRUGO|S_IWUSR);
+ MODULE_PARM_DESC(split_area_limit, "how many areas to split in each scheduling call");
+@@ -1164,7 +1168,7 @@ static int rockchip_ebc_refresh_thread(void *data)
+ /* 				 * @DRM_EPD_WF_GLD16: Less flashy 16-level grayscale, plus anti-ghosting */
+ 				// Not sure why only the GC16 is able to clear the ghosts from A2
+ 				// rockchip_ebc_refresh(ebc, ctx, true, DRM_EPD_WF_GC16);
+-				rockchip_ebc_refresh(ebc, ctx, true, default_waveform);
++				rockchip_ebc_refresh(ebc, ctx, true, refresh_waveform);
+ 			} else {
+ 				rockchip_ebc_refresh(ebc, ctx, false, default_waveform);
+ 			}
+-- 
+2.30.2
+
+
+From 39ffc2d84bc6f625a01db77b223ef06dcc6c7776 Mon Sep 17 00:00:00 2001
+From: Maximilian Weigand <mweigand@mweigand.net>
+Date: Mon, 8 Aug 2022 21:22:18 +0200
+Subject: [PATCH 44/44] [rockchip_ebc] use Bayer ordered dithering with a 4x4
+ matrix in black & white mode
+
+---
+ drivers/gpu/drm/rockchip/rockchip_ebc.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+index d8e44e696084..d64e7cabf362 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_ebc.c
++++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c
+@@ -1508,6 +1508,13 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 	unsigned int start_y;
+ 	unsigned int end_y2;
+ 
++	int pattern[4][4] = {
++		{0, 8, 2, 10},
++		{12, 4, 14, 6},
++		{3, 11, 1,  9},
++		{15, 7, 13, 5},
++	};
++
+ 	// -2 because we need to go to the beginning of the last line
+ 	start_y = panel_reflection ? src_clip->y1 : src_clip->y2 - 2;
+ 	delta_y = panel_reflection ? 1: -1;
+@@ -1567,13 +1574,15 @@ static bool rockchip_ebc_blit_fb(const struct rockchip_ebc_ctx *ctx,
+ 
+ 			if (bw_mode){
+ 				// convert to lack and white
+-				if (rgb0 >= bw_threshold){
++				if (rgb0 > pattern[x & 3][y & 3]){
++				// if (rgb0 >= bw_threshold){
+ 					rgb0 = 15;
+ 				} else {
+ 					rgb0 = 0;
+ 				}
+ 
+-				if (rgb1 >= bw_threshold){
++				// if (rgb1 >= bw_threshold){
++				if (rgb1 > pattern[(x + 1) & 3][y & 3]){
+ 					rgb1 = 15;
+ 				} else {
+ 					rgb1 = 0;
+-- 
+2.30.2
+
diff --git a/nongnu/packages/patches/sdbus-cpp-remove-systemd.patch b/nongnu/packages/patches/sdbus-cpp-remove-systemd.patch
new file mode 100644
index 0000000..7a00ae9
--- /dev/null
+++ b/nongnu/packages/patches/sdbus-cpp-remove-systemd.patch
@@ -0,0 +1,67 @@
+From 9f7400d32229c0a1d32349cf0a61900a50f0437a Mon Sep 17 00:00:00 2001
+From: Petr Hodina <phodina@protonmail.com>
+Date: Sun, 29 May 2022 06:09:27 +0200
+Subject: [PATCH] Remove systemd.
+
+
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index be4e836..97f5aef 100644
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -12,27 +12,6 @@ include(GNUInstallDirs) # Installation directories for `install` command and pkg
+ # PERFORMING CHECKS & PREPARING THE DEPENDENCIES
+ #-------------------------------
+ 
+-option(BUILD_LIBSYSTEMD "Build libsystemd static library and incorporate it into libsdbus-c++" OFF)
+-
+-if(NOT BUILD_LIBSYSTEMD)
+-    find_package(PkgConfig REQUIRED)
+-    pkg_check_modules(Systemd IMPORTED_TARGET GLOBAL libsystemd>=236)
+-    if(NOT TARGET PkgConfig::Systemd)
+-        message(FATAL_ERROR "libsystemd of version at least 236 is required, but was not found "
+-                            "(if you have systemd in your OS, you may want to install package containing pkgconfig "
+-                            " files for libsystemd library. On Ubuntu, that is libsystemd-dev. "
+-                            " Alternatively, you may turn BUILD_LIBSYSTEMD on for sdbus-c++ to download, build "
+-                            "and incorporate libsystemd as embedded library within sdbus-c++)")
+-    endif()
+-    add_library(Systemd::Libsystemd ALIAS PkgConfig::Systemd)
+-    string(REGEX MATCHALL "([0-9]+)" SYSTEMD_VERSION_LIST "${Systemd_VERSION}")
+-    list(GET SYSTEMD_VERSION_LIST 0 LIBSYSTEMD_VERSION)
+-    message(STATUS "Building with libsystemd v${LIBSYSTEMD_VERSION}")
+-else()
+-    # Build static libsystemd library as an external project
+-    include(cmake/LibsystemdExternalProject.cmake)
+-endif()
+-
+ find_package(Threads REQUIRED)
+ 
+ #-------------------------------
+@@ -104,18 +83,13 @@ endif()
+ 
+ # Having an object target allows unit tests to reuse already built sources without re-building
+ add_library(sdbus-c++-objlib OBJECT ${SDBUSCPP_SRCS})
+-target_compile_definitions(sdbus-c++-objlib PRIVATE BUILD_LIB=1 LIBSYSTEMD_VERSION=${LIBSYSTEMD_VERSION})
+ target_include_directories(sdbus-c++-objlib PUBLIC $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>
+                                                    $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/src>)
+ if(DEFINED BUILD_SHARED_LIBS)
+     set_target_properties(sdbus-c++-objlib PROPERTIES POSITION_INDEPENDENT_CODE ${BUILD_SHARED_LIBS})
+ endif()
+-if(BUILD_LIBSYSTEMD)
+-    add_dependencies(sdbus-c++-objlib LibsystemdBuildProject)
+-endif()
+ target_link_libraries(sdbus-c++-objlib
+         PUBLIC
+-            Systemd::Libsystemd
+             Threads::Threads)
+ 
+ add_library(sdbus-c++)
+@@ -231,6 +205,5 @@ set(CPACK_DEBIAN_FILE_NAME DEB-DEFAULT)
+ set(CPACK_DEBIAN_PACKAGE_SECTION "libs")
+ set(CPACK_DEBIAN_PACKAGE_SHLIBDEPS ON)
+ set(CPACK_DEBIAN_ENABLE_COMPONENT_DEPENDS ON)
+-set(CPACK_DEBIAN_DEV_PACKAGE_DEPENDS "libsystemd-dev (>=236)")
+ 
+ include(CPack)
+-- 
+2.35.1
+
diff --git a/nongnu/packages/patches/touchscreen-driver-01.patch b/nongnu/packages/patches/touchscreen-driver-01.patch
new file mode 100644
index 0000000..20026b4
--- /dev/null
+++ b/nongnu/packages/patches/touchscreen-driver-01.patch
@@ -0,0 +1,976 @@
+From a24cb29eca1a72afb1037f5468d3036b34ea1b66 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
+Date: Sun, 9 Jan 2022 21:53:28 +1000
+Subject: [PATCH] Input: Add driver for Cypress Generation 5 touchscreen
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the basic driver for the Cypress TrueTouch Gen5 touchscreen
+controllers. This driver supports only the I2C bus but it uses regmap
+so SPI support could be added later.
+The touchscreen can retrieve some defined zone that are handled as
+buttons (according to the hardware). That is why it handles
+button and multitouch events.
+
+Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
+Tested-by: Andreas Kemnade <andreas@kemnade.info> # Kobo Clara HD
+---
+ drivers/input/touchscreen/Kconfig   |  16 +
+ drivers/input/touchscreen/Makefile  |   1 +
+ drivers/input/touchscreen/cyttsp5.c | 902 ++++++++++++++++++++++++++++
+ 3 files changed, 919 insertions(+)
+ create mode 100644 drivers/input/touchscreen/cyttsp5.c
+
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 2f6adfb7b938..eb4e1b156683 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -284,6 +284,22 @@ config TOUCHSCREEN_CYTTSP4_SPI
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called cyttsp4_spi.
+ 
++config TOUCHSCREEN_CYTTSP5
++	tristate "Cypress TrueTouch Gen5 Touchscreen Driver"
++	depends on I2C
++	select REGMAP_I2C
++	select CRC_ITU_T
++	help
++	  Driver for Parade TrueTouch Standard Product Generation 5
++	  touchscreen controllers. I2C bus interface support only.
++
++	  Say Y here if you have a Cypress Gen5 touchscreen.
++
++	  If unsure, say N.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called cyttsp5.
++
+ config TOUCHSCREEN_DA9034
+ 	tristate "Touchscreen support for Dialog Semiconductor DA9034"
+ 	depends on PMIC_DA903X
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+index 39a8127cf6a5..0ea5c47f7fd9 100644
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -30,6 +30,7 @@ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_SPI)	+= cyttsp_spi.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_CORE)	+= cyttsp4_core.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_I2C)	+= cyttsp4_i2c.o cyttsp_i2c_common.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_SPI)	+= cyttsp4_spi.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP5)	+= cyttsp5.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9034)	+= da9034-ts.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9052)	+= da9052_tsi.o
+ obj-$(CONFIG_TOUCHSCREEN_DYNAPRO)	+= dynapro.o
+diff --git a/drivers/input/touchscreen/cyttsp5.c b/drivers/input/touchscreen/cyttsp5.c
+new file mode 100644
+index 000000000000..3ac45108090c
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp5.c
+@@ -0,0 +1,902 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Parade TrueTouch(TM) Standard Product V5 Module.
++ *
++ * Copyright (C) 2015 Parade Technologies
++ * Copyright (C) 2012-2015 Cypress Semiconductor
++ * Copyright (C) 2018 Bootlin
++ *
++ * Authors: Mylène Josserand <mylene.josserand@bootlin.com>
++ *                Alistair Francis <alistair@alistair23.me>
++ */
++
++#include <linux/crc-itu-t.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/input/mt.h>
++#include <linux/input/touchscreen.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <asm/unaligned.h>
++
++#define CYTTSP5_NAME				"cyttsp5"
++#define CY_I2C_DATA_SIZE			(2 * 256)
++#define HID_VERSION				0x0100
++#define CY_MAX_INPUT				512
++#define CYTTSP5_PREALLOCATED_CMD_BUFFER	32
++#define CY_BITS_PER_BTN			1
++#define CY_NUM_BTN_EVENT_ID			GENMASK(CY_BITS_PER_BTN, 0)
++
++#define MAX_AREA				255
++#define HID_OUTPUT_BL_SOP			0x1
++#define HID_OUTPUT_BL_EOP			0x17
++#define HID_OUTPUT_BL_LAUNCH_APP		0x3B
++#define HID_OUTPUT_BL_LAUNCH_APP_SIZE		11
++#define HID_OUTPUT_GET_SYSINFO			0x2
++#define HID_OUTPUT_GET_SYSINFO_SIZE		5
++#define HID_OUTPUT_MAX_CMD_SIZE		12
++
++#define HID_DESC_REG				0x1
++#define HID_INPUT_REG				0x3
++#define HID_OUTPUT_REG				0x4
++
++#define REPORT_ID_TOUCH			0x1
++#define REPORT_ID_BTN				0x3
++#define REPORT_SIZE_5				5
++#define REPORT_SIZE_8				8
++#define REPORT_SIZE_16				16
++
++/* Touch reports offsets */
++/* Header offsets */
++#define TOUCH_REPORT_DESC_HDR_CONTACTCOUNT	16
++/* Record offsets */
++#define TOUCH_REPORT_DESC_CONTACTID		8
++#define TOUCH_REPORT_DESC_X			16
++#define TOUCH_REPORT_DESC_Y			32
++#define TOUCH_REPORT_DESC_P			48
++#define TOUCH_REPORT_DESC_MAJ			56
++#define TOUCH_REPORT_DESC_MIN			64
++
++/* HID */
++#define HID_TOUCH_REPORT_ID			0x1
++#define HID_BTN_REPORT_ID			0x3
++#define HID_APP_RESPONSE_REPORT_ID		0x1F
++#define HID_APP_OUTPUT_REPORT_ID		0x2F
++#define HID_BL_RESPONSE_REPORT_ID		0x30
++#define HID_BL_OUTPUT_REPORT_ID		0x40
++
++#define HID_OUTPUT_RESPONSE_REPORT_OFFSET	2
++#define HID_OUTPUT_RESPONSE_CMD_OFFSET		4
++#define HID_OUTPUT_RESPONSE_CMD_MASK		GENMASK(6, 0)
++
++#define HID_SYSINFO_SENSING_OFFSET		33
++#define HID_SYSINFO_BTN_OFFSET			48
++#define HID_SYSINFO_BTN_MASK			GENMASK(7, 0)
++#define HID_SYSINFO_MAX_BTN			8
++
++#define CY_HID_OUTPUT_TIMEOUT_MS			200
++#define CY_HID_OUTPUT_GET_SYSINFO_TIMEOUT_MS	3000
++#define CY_HID_GET_HID_DESCRIPTOR_TIMEOUT_MS	4000
++
++/* maximum number of concurrent tracks */
++#define TOUCH_REPORT_SIZE			10
++#define TOUCH_INPUT_HEADER_SIZE		7
++#define BTN_REPORT_SIZE			9
++#define BTN_INPUT_HEADER_SIZE			5
++
++#define MAX_CY_TCH_T_IDS	32
++
++/* All usage pages for Touch Report */
++#define TOUCH_REPORT_USAGE_PG_X		0x00010030
++#define TOUCH_REPORT_USAGE_PG_Y		0x00010031
++#define TOUCH_REPORT_USAGE_PG_P		0x000D0030
++#define TOUCH_REPORT_USAGE_PG_CONTACTID	0x000D0051
++#define TOUCH_REPORT_USAGE_PG_CONTACTCOUNT	0x000D0054
++#define TOUCH_REPORT_USAGE_PG_MAJ		0xFF010062
++#define TOUCH_REPORT_USAGE_PG_MIN		0xFF010063
++#define TOUCH_COL_USAGE_PG			0x000D0022
++
++/* System Information interface definitions */
++struct cyttsp5_sensing_conf_data_dev {
++	u8 electrodes_x;
++	u8 electrodes_y;
++	__le16 len_x;
++	__le16 len_y;
++	__le16 res_x;
++	__le16 res_y;
++	__le16 max_z;
++	u8 origin_x;
++	u8 origin_y;
++	u8 btn;
++	u8 scan_mode;
++	u8 max_num_of_tch_per_refresh_cycle;
++} __packed;
++
++struct cyttsp5_sensing_conf_data {
++	u16 res_x;
++	u16 res_y;
++	u16 max_z;
++	u16 len_x;
++	u16 len_y;
++	u8 origin_x;
++	u8 origin_y;
++	u8 max_tch;
++};
++
++enum cyttsp5_tch_abs {	/* for ordering within the extracted touch data array */
++	CY_TCH_X,	/* X */
++	CY_TCH_Y,	/* Y */
++	CY_TCH_P,	/* P (Z) */
++	CY_TCH_T,	/* TOUCH ID */
++	CY_TCH_MAJ,	/* TOUCH_MAJOR */
++	CY_TCH_MIN,	/* TOUCH_MINOR */
++	CY_TCH_NUM_ABS
++};
++
++struct cyttsp5_tch_abs_params {
++	size_t ofs;	/* abs byte offset */
++	size_t size;	/* size in bits */
++	size_t min;	/* min value */
++	size_t max;	/* max value */
++	size_t bofs;	/* bit offset */
++};
++
++struct cyttsp5_touch {
++	int abs[CY_TCH_NUM_ABS];
++};
++
++struct cyttsp5_sysinfo {
++	struct cyttsp5_sensing_conf_data sensing_conf_data;
++	int num_btns;
++	struct cyttsp5_tch_abs_params tch_hdr;
++	struct cyttsp5_tch_abs_params tch_abs[CY_TCH_NUM_ABS];
++	u32 key_code[HID_SYSINFO_MAX_BTN];
++};
++
++struct cyttsp5_hid_desc {
++	__le16 hid_desc_len;
++	u8 packet_id;
++	u8 reserved_byte;
++	__le16 bcd_version;
++	__le16 report_desc_len;
++	__le16 report_desc_register;
++	__le16 input_register;
++	__le16 max_input_len;
++	__le16 output_register;
++	__le16 max_output_len;
++	__le16 command_register;
++	__le16 data_register;
++	__le16 vendor_id;
++	__le16 product_id;
++	__le16 version_id;
++	u8 reserved[4];
++} __packed;
++
++struct cyttsp5 {
++	struct device *dev;
++	struct completion cmd_done;
++	struct cyttsp5_sysinfo sysinfo;
++	struct cyttsp5_hid_desc hid_desc;
++	u8 cmd_buf[CYTTSP5_PREALLOCATED_CMD_BUFFER];
++	u8 input_buf[CY_MAX_INPUT];
++	u8 response_buf[CY_MAX_INPUT];
++	struct gpio_desc *reset_gpio;
++	struct input_dev *input;
++	char phys[NAME_MAX];
++	int num_prv_rec;
++	struct regmap *regmap;
++	struct touchscreen_properties prop;
++	struct regulator *vdd;
++};
++
++/*
++ * For what is understood in the datasheet, the register does not
++ * matter. For consistency, use the Input Register address
++ * but it does mean anything to the device. The important data
++ * to send is the I2C address
++ */
++static int cyttsp5_read(struct cyttsp5 *ts, u8 *buf, u32 max)
++{
++	int error;
++	u32 size;
++	u8 temp[2];
++
++	/* Read the frame to retrieve the size */
++	error = regmap_bulk_read(ts->regmap, HID_INPUT_REG, temp, sizeof(temp));
++	if (error)
++		return error;
++
++	size = get_unaligned_le16(temp);
++	if (!size || size == 2)
++		return 0;
++
++	if (size > max)
++		return -EINVAL;
++
++	/* Get the real value */
++	return regmap_bulk_read(ts->regmap, HID_INPUT_REG, buf, size);
++}
++
++static int cyttsp5_write(struct cyttsp5 *ts, unsigned int reg, u8 *data,
++			 size_t size)
++{
++	u8 cmd[HID_OUTPUT_MAX_CMD_SIZE];
++
++	if (size + 1 > HID_OUTPUT_MAX_CMD_SIZE)
++		return -E2BIG;
++
++	/* High bytes of register address needed as first byte of cmd */
++	cmd[0] = (reg >> 8) & 0xFF ;
++
++	/* Copy the rest of the data */
++	if (data)
++		memcpy(&cmd[1], data, size);
++
++	/*
++	 * The hardware wants to receive a frame with the address register
++	 * contained in the first two bytes. As the regmap_write function
++	 * add the register adresse in the frame, we use the low byte as
++	 * first frame byte for the address register and the first
++	 * data byte is the high register + left of the cmd to send
++	 */
++	return regmap_bulk_write(ts->regmap, reg & 0xFF, cmd, size + 1);
++}
++
++static void cyttsp5_get_touch_axis(int *axis, int size, int max, u8 *xy_data,
++				   int bofs)
++{
++	int nbyte;
++
++	for (nbyte = 0, *axis = 0; nbyte < size; nbyte++)
++		*axis += ((xy_data[nbyte] >> bofs) << (nbyte * 8));
++
++	*axis &= max - 1;
++}
++
++static void cyttsp5_get_touch_record(struct cyttsp5 *ts,
++				     struct cyttsp5_touch *touch, u8 *xy_data)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	enum cyttsp5_tch_abs abs;
++
++	for (abs = CY_TCH_X; abs < CY_TCH_NUM_ABS; abs++)
++		cyttsp5_get_touch_axis(&touch->abs[abs],
++				       si->tch_abs[abs].size,
++				       si->tch_abs[abs].max,
++				       xy_data + si->tch_abs[abs].ofs,
++				       si->tch_abs[abs].bofs);
++}
++
++static void cyttsp5_get_mt_touches(struct cyttsp5 *ts,
++				   struct cyttsp5_touch *tch, int num_cur_tch)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int i, t = 0, offset = 0;
++	DECLARE_BITMAP(ids, MAX_CY_TCH_T_IDS);
++	u8 *tch_addr;
++	int tmp;
++
++	bitmap_zero(ids, MAX_CY_TCH_T_IDS);
++	memset(tch->abs, 0, sizeof(tch->abs));
++
++	switch (ts->input_buf[2]) {
++	case HID_TOUCH_REPORT_ID:
++		offset = TOUCH_INPUT_HEADER_SIZE;
++		break;
++	case HID_BTN_REPORT_ID:
++		offset = BTN_INPUT_HEADER_SIZE;
++		break;
++	}
++
++	for (i = 0; i < num_cur_tch; i++) {
++		tch_addr = ts->input_buf + offset + (i * TOUCH_REPORT_SIZE);
++		cyttsp5_get_touch_record(ts, tch, tch_addr);
++
++		/* Convert MAJOR/MINOR from mm to resolution */
++		tmp = tch->abs[CY_TCH_MAJ] * 100 * si->sensing_conf_data.res_x;
++		tch->abs[CY_TCH_MAJ] = tmp / si->sensing_conf_data.len_x;
++		tmp = tch->abs[CY_TCH_MIN] * 100 * si->sensing_conf_data.res_x;
++		tch->abs[CY_TCH_MIN] = tmp / si->sensing_conf_data.len_x;
++
++		t = tch->abs[CY_TCH_T];
++		input_mt_slot(ts->input, t);
++		input_mt_report_slot_state(ts->input, MT_TOOL_FINGER, true);
++		__set_bit(t, ids);
++
++		/* position and pressure fields */
++		touchscreen_report_pos(ts->input, &ts->prop,
++				       tch->abs[CY_TCH_X], tch->abs[CY_TCH_Y],
++				       true);
++		input_report_abs(ts->input, ABS_MT_PRESSURE,
++				 tch->abs[CY_TCH_P]);
++
++		/* Get the extended touch fields */
++		input_report_abs(ts->input, ABS_MT_TOUCH_MAJOR,
++				 tch->abs[CY_TCH_MAJ]);
++		input_report_abs(ts->input, ABS_MT_TOUCH_MINOR,
++				 tch->abs[CY_TCH_MIN]);
++	}
++
++	ts->num_prv_rec = num_cur_tch;
++}
++
++static int cyttsp5_mt_attention(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int max_tch = si->sensing_conf_data.max_tch;
++	struct cyttsp5_touch tch;
++	u8 num_cur_tch;
++
++	cyttsp5_get_touch_axis((int *) &num_cur_tch, si->tch_hdr.size,
++			       si->tch_hdr.max,
++			       ts->input_buf + 3 + si->tch_hdr.ofs,
++			       si->tch_hdr.bofs);
++
++	if (num_cur_tch > max_tch) {
++		dev_err(dev, "Num touch err detected (n=%d)\n", num_cur_tch);
++		num_cur_tch = max_tch;
++	}
++
++	if (num_cur_tch == 0 && ts->num_prv_rec == 0)
++		return 0;
++
++	/* extract xy_data for all currently reported touches */
++	if (num_cur_tch)
++		cyttsp5_get_mt_touches(ts, &tch, num_cur_tch);
++
++	input_mt_sync_frame(ts->input);
++	input_sync(ts->input);
++
++	return 0;
++}
++
++static int cyttsp5_setup_input_device(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int max_x, max_y, max_p;
++	int max_x_tmp, max_y_tmp;
++	int error;
++
++	max_x_tmp = si->sensing_conf_data.res_x;
++	max_y_tmp = si->sensing_conf_data.res_y;
++	max_x = max_x_tmp - 1;
++	max_y = max_y_tmp - 1;
++	max_p = si->sensing_conf_data.max_z;
++
++	input_set_abs_params(ts->input, ABS_MT_POSITION_X, 0, max_x, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_POSITION_Y, 0, max_y, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_PRESSURE, 0, max_p, 0, 0);
++
++	input_set_abs_params(ts->input, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++	input_set_abs_params(ts->input, ABS_MT_TOUCH_MINOR, 0, MAX_AREA, 0, 0);
++
++	error = input_mt_init_slots(ts->input, si->tch_abs[CY_TCH_T].max,
++		INPUT_MT_DROP_UNUSED | INPUT_MT_DIRECT);
++	if (error < 0)
++		return error;
++
++	error = input_register_device(ts->input);
++	if (error < 0)
++		dev_err(dev, "Error, failed register input device r=%d\n", error);
++
++	return error;
++}
++
++static int cyttsp5_parse_dt_key_code(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++
++	if (!si->num_btns)
++		return 0;
++
++	/* Initialize the button to RESERVED */
++	memset32(si->key_code, KEY_RESERVED,  si->num_btns);
++
++	return device_property_read_u32_array(dev, "linux,keycodes",
++				   si->key_code, si->num_btns);
++}
++
++static int cyttsp5_btn_attention(struct device *dev)
++{
++	struct cyttsp5 *ts = dev_get_drvdata(dev);
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	int cur_btn, offset = 0;
++	int cur_btn_state;
++
++	switch (ts->input_buf[2]) {
++	case HID_TOUCH_REPORT_ID:
++		offset = TOUCH_INPUT_HEADER_SIZE;
++		break;
++	case HID_BTN_REPORT_ID:
++		offset = BTN_INPUT_HEADER_SIZE;
++		break;
++	}
++
++	if (ts->input_buf[2] != HID_BTN_REPORT_ID || !si->num_btns)
++		return 0;
++
++	/* extract button press/release touch information */
++	for (cur_btn = 0; cur_btn < si->num_btns; cur_btn++) {
++		/* Get current button state */
++		cur_btn_state = (ts->input_buf[offset] >> (cur_btn * CY_BITS_PER_BTN))
++			& CY_NUM_BTN_EVENT_ID;
++
++		input_report_key(ts->input, si->key_code[cur_btn],
++				 cur_btn_state);
++		input_sync(ts->input);
++	}
++
++	return 0;
++}
++
++static int cyttsp5_validate_cmd_response(struct cyttsp5 *ts, u8 code)
++{
++	u16 size, crc;
++	u8 status, report_id;
++	int command_code;
++
++	size = get_unaligned_le16(&ts->response_buf[0]);
++
++	if (!size)
++		return 0;
++
++	report_id = ts->response_buf[HID_OUTPUT_RESPONSE_REPORT_OFFSET];
++
++	switch (report_id) {
++	case HID_BL_RESPONSE_REPORT_ID: {
++		if (ts->response_buf[4] != HID_OUTPUT_BL_SOP) {
++			dev_err(ts->dev, "HID output response, wrong SOP\n");
++			return -EPROTO;
++		}
++
++		if (ts->response_buf[size - 1] != HID_OUTPUT_BL_EOP) {
++			dev_err(ts->dev, "HID output response, wrong EOP\n");
++			return -EPROTO;
++		}
++
++		crc = crc_itu_t(0xFFFF, &ts->response_buf[4], size - 7);
++		if (get_unaligned_le16(&ts->response_buf[size - 3]) != crc) {
++			dev_err(ts->dev, "HID output response, wrong CRC 0x%X\n",
++				crc);
++			return -EPROTO;
++		}
++
++		status = ts->response_buf[5];
++		if (status) {
++			dev_err(ts->dev, "HID output response, ERROR:%d\n",
++				status);
++			return -EPROTO;
++		}
++		break;
++	}
++	case HID_APP_RESPONSE_REPORT_ID: {
++		command_code = ts->response_buf[HID_OUTPUT_RESPONSE_CMD_OFFSET]
++			& HID_OUTPUT_RESPONSE_CMD_MASK;
++		if (command_code != code) {
++			dev_err(ts->dev,
++				"HID output response, wrong command_code:%X\n",
++				command_code);
++			return -EPROTO;
++		}
++		break;
++	}
++	}
++
++	return 0;
++}
++
++static void cyttsp5_si_get_btn_data(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++	unsigned int btns = ts->response_buf[HID_SYSINFO_BTN_OFFSET]
++		& HID_SYSINFO_BTN_MASK;
++
++	si->num_btns = hweight8(btns);
++}
++
++static int cyttsp5_get_sysinfo_regs(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sensing_conf_data *scd = &ts->sysinfo.sensing_conf_data;
++	struct cyttsp5_sensing_conf_data_dev *scd_dev =
++		(struct cyttsp5_sensing_conf_data_dev *)
++		&ts->response_buf[HID_SYSINFO_SENSING_OFFSET];
++
++	cyttsp5_si_get_btn_data(ts);
++
++	scd->max_tch = scd_dev->max_num_of_tch_per_refresh_cycle;
++	scd->res_x = get_unaligned_le16(&scd_dev->res_x);
++	scd->res_y = get_unaligned_le16(&scd_dev->res_y);
++	scd->max_z = get_unaligned_le16(&scd_dev->max_z);
++	scd->len_x = get_unaligned_le16(&scd_dev->len_x);
++	scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++
++	return 0;
++}
++
++static int cyttsp5_hid_output_get_sysinfo(struct cyttsp5 *ts)
++{
++	int rc;
++	u8 cmd[HID_OUTPUT_GET_SYSINFO_SIZE];
++
++	/* HI bytes of Output register address */
++	put_unaligned_le16(HID_OUTPUT_GET_SYSINFO_SIZE, cmd);
++	cmd[2] = HID_APP_OUTPUT_REPORT_ID;
++	cmd[3] = 0x0; /* Reserved */
++	cmd[4] = HID_OUTPUT_GET_SYSINFO;
++
++	rc = cyttsp5_write(ts, HID_OUTPUT_REG, cmd,
++			   HID_OUTPUT_GET_SYSINFO_SIZE);
++	if (rc) {
++		dev_err(ts->dev, "Failed to write command %d", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_OUTPUT_GET_SYSINFO_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID output cmd execution timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	rc = cyttsp5_validate_cmd_response(ts, HID_OUTPUT_GET_SYSINFO);
++	if (rc) {
++		dev_err(ts->dev, "Validation of the response failed\n");
++		return rc;
++	}
++
++	return cyttsp5_get_sysinfo_regs(ts);
++}
++
++static int cyttsp5_hid_output_bl_launch_app(struct cyttsp5 *ts)
++{
++	int rc;
++	u8 cmd[HID_OUTPUT_BL_LAUNCH_APP];
++	u16 crc;
++
++	put_unaligned_le16(HID_OUTPUT_BL_LAUNCH_APP_SIZE, cmd);
++	cmd[2] = HID_BL_OUTPUT_REPORT_ID;
++	cmd[3] = 0x0; /* Reserved */
++	cmd[4] = HID_OUTPUT_BL_SOP;
++	cmd[5] = HID_OUTPUT_BL_LAUNCH_APP;
++	put_unaligned_le16(0x00, &cmd[6]);
++	crc = crc_itu_t(0xFFFF, &cmd[4], 4);
++	put_unaligned_le16(crc, &cmd[8]);
++	cmd[10] = HID_OUTPUT_BL_EOP;
++
++	rc = cyttsp5_write(ts, HID_OUTPUT_REG, cmd,
++			   HID_OUTPUT_BL_LAUNCH_APP_SIZE);
++	if (rc) {
++		dev_err(ts->dev, "Failed to write command %d", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_OUTPUT_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID output cmd execution timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	rc = cyttsp5_validate_cmd_response(ts, HID_OUTPUT_BL_LAUNCH_APP);
++	if (rc) {
++		dev_err(ts->dev, "Validation of the response failed\n");
++		return rc;
++	}
++
++	return 0;
++}
++
++static int cyttsp5_get_hid_descriptor(struct cyttsp5 *ts,
++				      struct cyttsp5_hid_desc *desc)
++{
++	struct device *dev = ts->dev;
++	__le16 hid_desc_register = HID_DESC_REG;
++	int rc;
++	u8 cmd[2];
++
++	/* Set HID descriptor register */
++	memcpy(cmd, &hid_desc_register, sizeof(hid_desc_register));
++
++	rc = cyttsp5_write(ts, HID_DESC_REG, NULL, 0);
++	if (rc) {
++		dev_err(dev, "Failed to get HID descriptor, rc=%d\n", rc);
++		return rc;
++	}
++
++	rc = wait_for_completion_interruptible_timeout(&ts->cmd_done,
++						msecs_to_jiffies(CY_HID_GET_HID_DESCRIPTOR_TIMEOUT_MS));
++	if (rc <= 0) {
++		dev_err(ts->dev, "HID get descriptor timed out\n");
++		rc = -ETIMEDOUT;
++		return rc;
++	}
++
++	memcpy(desc, ts->response_buf, sizeof(*desc));
++
++	/* Check HID descriptor length and version */
++	if (le16_to_cpu(desc->hid_desc_len) != sizeof(*desc) ||
++	    le16_to_cpu(desc->bcd_version) != HID_VERSION) {
++		dev_err(dev, "Unsupported HID version\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static int fill_tch_abs(struct cyttsp5_tch_abs_params *tch_abs, int report_size,
++			int offset)
++{
++	tch_abs->ofs = offset / 8;
++	tch_abs->size = report_size / 8;
++	if (report_size % 8)
++		tch_abs->size += 1;
++	tch_abs->min = 0;
++	tch_abs->max = 1 << report_size;
++	tch_abs->bofs = offset - (tch_abs->ofs << 3);
++
++	return 0;
++}
++
++static irqreturn_t cyttsp5_handle_irq(int irq, void *handle)
++{
++	struct cyttsp5 *ts = handle;
++	int report_id;
++	int size;
++	int error;
++
++	error = cyttsp5_read(ts, ts->input_buf, CY_MAX_INPUT);
++	if (error)
++		return IRQ_HANDLED;
++
++	size = get_unaligned_le16(&ts->input_buf[0]);
++	if (size == 0) {
++		/* reset */
++		report_id = 0;
++		size = 2;
++	} else {
++		report_id = ts->input_buf[2];
++	}
++
++	switch (report_id) {
++	case HID_TOUCH_REPORT_ID:
++		cyttsp5_mt_attention(ts->dev);
++		break;
++	case HID_BTN_REPORT_ID:
++		cyttsp5_btn_attention(ts->dev);
++		break;
++	default:
++		/* It is not an input but a command response */
++		memcpy(ts->response_buf, ts->input_buf, size);
++		complete(&ts->cmd_done);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static int cyttsp5_deassert_int(struct cyttsp5 *ts)
++{
++	u16 size;
++	u8 buf[2];
++	int error;
++
++	error = regmap_bulk_read(ts->regmap, HID_INPUT_REG, buf, sizeof(buf));
++	if (error < 0)
++		return error;
++
++	size = get_unaligned_le16(&buf[0]);
++	if (size == 2 || size == 0)
++		return 0;
++
++	return -EINVAL;
++}
++
++static int cyttsp5_fill_all_touch(struct cyttsp5 *ts)
++{
++	struct cyttsp5_sysinfo *si = &ts->sysinfo;
++
++	fill_tch_abs(&si->tch_abs[CY_TCH_X], REPORT_SIZE_16,
++		     TOUCH_REPORT_DESC_X);
++	fill_tch_abs(&si->tch_abs[CY_TCH_Y], REPORT_SIZE_16,
++		     TOUCH_REPORT_DESC_Y);
++	fill_tch_abs(&si->tch_abs[CY_TCH_P], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_P);
++	fill_tch_abs(&si->tch_abs[CY_TCH_T], REPORT_SIZE_5,
++		     TOUCH_REPORT_DESC_CONTACTID);
++	fill_tch_abs(&si->tch_hdr, REPORT_SIZE_5,
++		     TOUCH_REPORT_DESC_HDR_CONTACTCOUNT);
++	fill_tch_abs(&si->tch_abs[CY_TCH_MAJ], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_MAJ);
++	fill_tch_abs(&si->tch_abs[CY_TCH_MIN], REPORT_SIZE_8,
++		     TOUCH_REPORT_DESC_MIN);
++
++	return 0;
++}
++
++static int cyttsp5_startup(struct cyttsp5 *ts)
++{
++	int error;
++
++	error = cyttsp5_deassert_int(ts);
++	if (error) {
++		dev_err(ts->dev, "Error on deassert int r=%d\n", error);
++		return -ENODEV;
++	}
++
++	/*
++	 * Launch the application as the device starts in bootloader mode
++	 * because of a power-on-reset
++	 */
++	error = cyttsp5_hid_output_bl_launch_app(ts);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on launch app r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_get_hid_descriptor(ts, &ts->hid_desc);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on getting HID descriptor r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_fill_all_touch(ts);
++	if (error < 0) {
++		dev_err(ts->dev, "Error on report descriptor r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_hid_output_get_sysinfo(ts);
++	if (error) {
++		dev_err(ts->dev, "Error on getting sysinfo r=%d\n", error);
++		return error;
++	}
++
++	return error;
++}
++
++static void cyttsp5_cleanup(void *data)
++{
++	struct cyttsp5 *ts = data;
++
++	regulator_disable(ts->vdd);
++}
++
++static int cyttsp5_probe(struct device *dev, struct regmap *regmap, int irq,
++			 const char *name)
++{
++	struct cyttsp5 *ts;
++	struct cyttsp5_sysinfo *si;
++	int error, i;
++
++	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++
++	/* Initialize device info */
++	ts->regmap = regmap;
++	ts->dev = dev;
++	si = &ts->sysinfo;
++	dev_set_drvdata(dev, ts);
++
++	init_completion(&ts->cmd_done);
++
++	/* Power up the device */
++	ts->vdd = devm_regulator_get(dev, "vdd");
++	if (IS_ERR(ts->vdd)) {
++		error = PTR_ERR(ts->vdd);
++		return error;
++	}
++
++	error = devm_add_action_or_reset(dev, cyttsp5_cleanup, ts);
++	if (error) {
++		return error;
++	}
++
++	error = regulator_enable(ts->vdd);
++	if (error) {
++		return error;
++	}
++
++	ts->input = devm_input_allocate_device(dev);
++	if (!ts->input) {
++		dev_err(dev, "Error, failed to allocate input device\n");
++		return -ENODEV;
++	}
++
++	ts->input->name = "cyttsp5";
++	scnprintf(ts->phys, sizeof(ts->phys), "%s/input0", dev_name(dev));
++	ts->input->phys = ts->phys;
++	input_set_drvdata(ts->input, ts);
++
++	/* Reset the gpio to be in a reset state */
++	ts->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(ts->reset_gpio)) {
++		error = PTR_ERR(ts->reset_gpio);
++		dev_err(dev, "Failed to request reset gpio, error %d\n", error);
++		return error;
++	}
++	gpiod_set_value(ts->reset_gpio, 0);
++
++	/* Need a delay to have device up */
++	msleep(20);
++
++	error = devm_request_threaded_irq(dev, irq, NULL, cyttsp5_handle_irq,
++				       IRQF_ONESHOT, name, ts);
++	if (error) {
++		dev_err(dev, "unable to request IRQ\n");
++		return error;
++	}
++
++	error = cyttsp5_startup(ts);
++	if (error) {
++		dev_err(ts->dev, "Fail initial startup r=%d\n", error);
++		return error;
++	}
++
++	error = cyttsp5_parse_dt_key_code(dev);
++	if (error < 0) {
++		dev_err(ts->dev, "Error while parsing dts %d\n", error);
++		return error;
++	}
++
++	touchscreen_parse_properties(ts->input, true, &ts->prop);
++
++	__set_bit(EV_KEY, ts->input->evbit);
++	for (i = 0; i < si->num_btns; i++)
++		__set_bit(si->key_code[i], ts->input->keybit);
++
++	return cyttsp5_setup_input_device(dev);
++}
++
++static int cyttsp5_i2c_probe(struct i2c_client *client,
++			     const struct i2c_device_id *id)
++{
++	struct regmap *regmap;
++	static const struct regmap_config config = {
++		.reg_bits = 8,
++		.val_bits = 8,
++	};
++
++	regmap = devm_regmap_init_i2c(client, &config);
++	if (IS_ERR(regmap)) {
++		dev_err(&client->dev, "regmap allocation failed: %ld\n",
++			PTR_ERR(regmap));
++		return PTR_ERR(regmap);
++	}
++
++	return cyttsp5_probe(&client->dev, regmap, client->irq, client->name);
++}
++
++static const struct of_device_id cyttsp5_of_match[] = {
++	{ .compatible = "cypress,tt21000", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cyttsp5_of_match);
++
++static const struct i2c_device_id cyttsp5_i2c_id[] = {
++	{ CYTTSP5_NAME, 0, },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cyttsp5_i2c_id);
++
++static struct i2c_driver cyttsp5_i2c_driver = {
++	.driver = {
++		.name = CYTTSP5_NAME,
++		.of_match_table = cyttsp5_of_match,
++	},
++	.probe = cyttsp5_i2c_probe,
++	.id_table = cyttsp5_i2c_id,
++};
++module_i2c_driver(cyttsp5_i2c_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Touchscreen driver for Cypress TrueTouch Gen 5 Product");
++MODULE_AUTHOR("Mylène Josserand <mylene.josserand@bootlin.com>");
+-- 
+GitLab
+
diff --git a/nongnu/packages/patches/touchscreen-driver-02.patch b/nongnu/packages/patches/touchscreen-driver-02.patch
new file mode 100644
index 0000000..9ccef92
--- /dev/null
+++ b/nongnu/packages/patches/touchscreen-driver-02.patch
@@ -0,0 +1,108 @@
+From d6bb8a6b5a5210fea70bc590350bfca3a9e3a7a2 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 15 Jan 2022 21:50:45 -0500
+Subject: [PATCH] Input: cyttsp5: support touchscreen device tree overrides
+
+It is possible for the cyttsp5 chip to not have a configuration burned
+to it.
+This leads to a sitatuion where all calibration values return zero,
+leading to a broken touchscreen configuration.
+
+The current driver does not support utilizing overrides from the device
+tree.
+Extend the driver to support this, and permit it to do some basic sanity
+checking of the values for the touchscreen and abort if they are
+invalid.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/input/touchscreen/cyttsp5.c | 62 ++++++++++++++++++++++++++---
+ 1 file changed, 57 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp5.c b/drivers/input/touchscreen/cyttsp5.c
+index 3ac45108090c..e837985d199a 100644
+--- a/drivers/input/touchscreen/cyttsp5.c
++++ b/drivers/input/touchscreen/cyttsp5.c
+@@ -507,15 +507,66 @@ static int cyttsp5_get_sysinfo_regs(struct cyttsp5 *ts)
+ 	struct cyttsp5_sensing_conf_data_dev *scd_dev =
+ 		(struct cyttsp5_sensing_conf_data_dev *)
+ 		&ts->response_buf[HID_SYSINFO_SENSING_OFFSET];
++	u32 tmp;
+ 
+ 	cyttsp5_si_get_btn_data(ts);
+ 
+ 	scd->max_tch = scd_dev->max_num_of_tch_per_refresh_cycle;
+-	scd->res_x = get_unaligned_le16(&scd_dev->res_x);
+-	scd->res_y = get_unaligned_le16(&scd_dev->res_y);
+-	scd->max_z = get_unaligned_le16(&scd_dev->max_z);
+-	scd->len_x = get_unaligned_le16(&scd_dev->len_x);
+-	scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++
++	if (scd->max_tch == 0) {
++		dev_dbg(ts->dev, "Max touch points cannot be zero\n");
++		scd->max_tch = 2;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-size-x", &tmp))
++		scd->res_x = get_unaligned_le16(&scd_dev->res_x);
++	else
++		scd->res_x = tmp;
++
++	if (scd->res_x == 0) {
++		dev_err(ts->dev, "ABS_X cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-size-y", &tmp))
++		scd->res_y = get_unaligned_le16(&scd_dev->res_y);
++	else
++		scd->res_y = tmp;
++
++	if (scd->res_y == 0) {
++		dev_err(ts->dev, "ABS_Y cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-max-pressure", &tmp))
++		scd->max_z = get_unaligned_le16(&scd_dev->max_z);
++	else
++		scd->max_z = tmp;
++
++	if (scd->max_z == 0) {
++		dev_err(ts->dev, "ABS_PRESSURE cannot be zero\n");
++		return -ENODATA;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-x-mm", &tmp))
++		scd->len_x = get_unaligned_le16(&scd_dev->len_x);
++	else
++		scd->len_x = tmp;
++
++	if (scd->len_x == 0) {
++		dev_dbg(ts->dev, "Touchscreen size x cannot be zero\n");
++		scd->len_x = scd->res_x + 1;
++	}
++
++	if(device_property_read_u32(ts->dev, "touchscreen-y-mm", &tmp))
++		scd->len_y = get_unaligned_le16(&scd_dev->len_y);
++	else
++		scd->len_y = tmp;
++
++	if (scd->len_y == 0) {
++		dev_dbg(ts->dev, "Touchscreen size y cannot be zero\n");
++		scd->len_y = scd->res_y + 1;
++	}
+ 
+ 	return 0;
+ }
+@@ -877,6 +928,7 @@ static int cyttsp5_i2c_probe(struct i2c_client *client,
+ 
+ static const struct of_device_id cyttsp5_of_match[] = {
+ 	{ .compatible = "cypress,tt21000", },
++	{ .compatible = "cypress,tma448", },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, cyttsp5_of_match);
+-- 
+GitLab
+
diff --git a/nongnu/packages/patches/wusb3801_patches_samsapti_20220725.patch b/nongnu/packages/patches/wusb3801_patches_samsapti_20220725.patch
new file mode 100644
index 0000000..e30a958
--- /dev/null
+++ b/nongnu/packages/patches/wusb3801_patches_samsapti_20220725.patch
@@ -0,0 +1,65 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts
+index 6bbc4c675d..92ef19676e 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts
+@@ -16,3 +16,39 @@ &pmu_io_domains {
+ &spk_amp {
+ 	VCC-supply = <&vcc_bat>;
+ };
++
++&usb2phy0_otg {
++	port {
++		usb2phy0_typec_hs: endpoint {
++			remote-endpoint = <&usbc_hs>;
++		};
++	};
++};
++
++&wusb3801 {
++	status = "okay";
++
++	connector {
++		compatible = "usb-c-connector";
++		label = "USB-C";
++		vbus-supply = <&otg_switch>;
++		power-role = "dual";
++		try-power-role = "sink";
++		data-role = "dual";
++		typec-power-opmode = "default";
++		pd-disable;
++
++		ports {
++			#address-cells = <0x01>;
++			#size-cells = <0x00>;
++
++			port@0 {
++				reg = <0x00>;
++
++				usbc_hs: endpoint {
++					remote-endpoint = <&usb2phy0_typec_hs>;
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+index 59ac178881..e5ab58cbc0 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+@@ -6,6 +6,7 @@
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/suspend/rockchip-rk3568.h>
++#include <dt-bindings/usb/pd.h>
+ 
+ #include "rk3566.dtsi"
+ 
+@@ -611,7 +612,7 @@ wusb3801: tcpc@60 {
+ 		interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ 		pinctrl-0 = <&tcpc_int_l>;
+ 		pinctrl-names = "default";
+-		status = "disabled";
++		status = "okay";
+ 	};
+ 
+ 	/* TODO: write binding */
diff --git a/nongnu/system/images/pinenote.scm b/nongnu/system/images/pinenote.scm
new file mode 100644
index 0000000..d1bc88b
--- /dev/null
+++ b/nongnu/system/images/pinenote.scm
@@ -0,0 +1,89 @@
+;;; GNU Guix --- Functional package management for GNU
+;;; Copyright © 2020 Mathieu Othacehe <m.othacehe@gmail.com>
+;;;
+;;; This file is part of GNU Guix.
+;;;
+;;; GNU Guix is free software; you can redistribute it and/or modify it
+;;; under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation; either version 3 of the License, or (at
+;;; your option) any later version.
+;;;
+;;; GNU Guix is distributed in the hope that it will be useful, but
+;;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
+
+(define-module (nongnu system images pinenote)
+  #:use-module (gnu bootloader)
+  #:use-module (gnu bootloader u-boot)
+  #:use-module (gnu image)
+  #:use-module (gnu packages certs)
+  #:use-module (gnu packages ssh)
+  #:use-module (gnu packages wm)
+  #:use-module (nongnu packages linux)
+  #:use-module (nongnu packages firmware)
+  #:use-module (nongnu packages bootloaders)
+  #:use-module (guix platforms arm)
+  #:use-module (gnu services)
+  #:use-module (gnu services base)
+  #:use-module (gnu services desktop)
+  #:use-module (gnu services sddm)
+  #:use-module (gnu system)
+  #:use-module (gnu system file-systems)
+  #:use-module (gnu system image)
+  #:use-module (srfi srfi-26)
+  #:export (pinenote-raw-image
+            pinenote-image-type
+            pinenote-barebones-raw-image))
+
+(define pinenote-barebone-os
+  (operating-system
+    (host-name "viso")
+    (timezone "Europe/Prague")
+    (locale "en_US.utf8")
+
+    (bootloader (bootloader-configuration
+                 (bootloader u-boot-pinenote-rk3566-bootloader)
+                 (targets '("/dev/vda"))))
+    (initrd-modules '())
+
+	(firmware (list pinenote-firmware))
+    (kernel linux-pinenote)
+    (file-systems (cons (file-system
+                          (device (file-system-label "my-root"))
+                          (mount-point "/")
+                          (type "ext4"))
+                        %base-file-systems))
+
+    (packages (append (list nss-certs
+                     openssh
+                     sway)
+                     %base-packages))
+
+    (services (cons (service agetty-service-type
+                             (agetty-configuration
+                              (extra-options '("-L")) ; no carrier detect
+                              (baud-rate "1500000")
+                              (term "vt100")
+                              (tty "ttyS2"))))
+                    %base-services)))
+
+(define pinenote-image-type
+  (image-type
+   (name 'pinenote-raw)
+   (constructor (cut image-with-os
+                     (raw-with-offset-disk-image (* 32 (expt 2 20))) ; 32MiB
+                     <>))))
+
+(define pinenote-barebones-raw-image
+  (image
+   (inherit
+    (os+platform->image pinenote-barebone-os aarch64-linux
+                        #:type pinenote-image-type))
+   (name 'pinenote-barebones-raw-image)))
+
+;; Return the default image.
+pinenote-barebones-raw-image
diff --git a/nongnu/system/images/pinephone-pro.scm b/nongnu/system/images/pinephone-pro.scm
new file mode 100644
index 0000000..a6359cf
--- /dev/null
+++ b/nongnu/system/images/pinephone-pro.scm
@@ -0,0 +1,88 @@
+;;; GNU Guix --- Functional package management for GNU
+;;; Copyright © 2020 Mathieu Othacehe <m.othacehe@gmail.com>
+;;;
+;;; This file is part of GNU Guix.
+;;;
+;;; GNU Guix is free software; you can redistribute it and/or modify it
+;;; under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation; either version 3 of the License, or (at
+;;; your option) any later version.
+;;;
+;;; GNU Guix is distributed in the hope that it will be useful, but
+;;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
+
+(define-module (nongnu system images pinephone-pro)
+  #:use-module (gnu bootloader)
+  #:use-module (gnu bootloader u-boot)
+  #:use-module (gnu image)
+  #:use-module (nongnu packages linux)
+  #:use-module (nongnu packages bootloaders)
+  #:use-module (guix platforms arm)
+  #:use-module (gnu services)
+  #:use-module (gnu services base)
+  #:use-module (gnu services networking)
+  #:use-module (gnu services ssh)
+  #:use-module (gnu system)
+  #:use-module (gnu system file-systems)
+  #:use-module (gnu system image)
+  #:use-module (srfi srfi-26)
+  #:export (quartz64-a-raw-image
+            quartz64-image-type
+            quartz64-barebones-raw-image))
+
+(define pinephone-pro-barebone-os
+  (operating-system
+    (host-name "viso")
+    (timezone "Europe/Paris")
+    (locale "en_US.utf8")
+
+    (bootloader (bootloader-configuration
+                 (bootloader u-boot-pinephone-pro-rk3399-bootloader)
+                 (targets '("/dev/vda"))))
+    (initrd-modules '())
+    (kernel linux-pinephone-pro)
+    (file-systems (append (list
+                          (file-system
+                          (device (file-system-label "root"))
+                          (mount-point "/")
+                          (type "ext4")))
+                        %base-file-systems))
+
+    (swap-devices (list (swap-space
+                         (target "/run/swapfile"))))
+
+    (services (append (list (service agetty-service-type
+                             (agetty-configuration
+                              (extra-options '("-L")) ; no carrier detect
+                              (baud-rate "1500000")
+                              (term "vt100")
+                              (tty "ttyS2")))
+                     (service dhcp-client-service-type)
+                     (service ntp-service-type)
+                              (service openssh-service-type))
+                    %base-services))))
+
+(define pinephone-pro-image-type
+  (image-type
+   (name 'pinephone-pro-raw)
+   (constructor (lambda (os)
+                  (image
+				   (inherit
+                     (raw-with-offset-disk-image (* 32 (expt 2 20)))) ; 32MiB
+                   (operating-system os)
+                   (platform aarch64-linux))))))
+
+(define pinephone-pro-barebones-raw-image
+  (image
+   (inherit
+    (os+platform->image pinephone-pro-barebone-os aarch64-linux
+                        #:type pinephone-pro-image-type))
+   (name 'quartz-barebones-raw-image)))
+
+;; Return the default image.
+pinephone-pro-barebones-raw-image
diff --git a/nongnu/system/images/quartz64a-desktop.scm b/nongnu/system/images/quartz64a-desktop.scm
new file mode 100644
index 0000000..ec2dd83
--- /dev/null
+++ b/nongnu/system/images/quartz64a-desktop.scm
@@ -0,0 +1,291 @@
+;;; GNU Guix --- Functional package management for GNU
+;;; Copyright © 2022 Petr Hodina <phodina@protonmail.com>
+;;;
+;;; This file is part of GNU Guix.
+;;;
+;;; GNU Guix is free software; you can redistribute it and/or modify it
+;;; under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation; either version 3 of the License, or (at
+;;; your option) any later version.
+;;;
+;;; GNU Guix is distributed in the hope that it will be useful, but
+;;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
+
+(define-module (nongnu system images quartz64a-desktop)
+  #:use-module (gnu bootloader)
+  #:use-module (gnu bootloader u-boot)
+  #:use-module (gnu image)
+  #:use-module (nongnu packages linux)
+  #:use-module (nongnu packages bootloaders)
+  #:use-module (gnu packages)
+  #:use-module (gnu packages glib)
+  #:use-module (gnu packages compression)
+  #:use-module (gnu packages certs)
+  #:use-module (gnu packages gnome)
+  #:use-module (gnu packages vim)
+  #:use-module (gnu packages ssh)
+  #:use-module (gnu packages bison)
+  #:use-module (gnu packages libffi)
+  #:use-module (gnu packages xorg)
+  #:use-module (gnu packages flex)
+  #:use-module (gnu packages pkg-config)
+  #:use-module (gnu packages python)
+  #:use-module (guix platforms arm)
+  #:use-module (guix download)
+  #:use-module (guix packages)
+  #:use-module (guix gexp)
+  #:use-module (guix utils)
+  #:use-module (guix build utils)
+  #:use-module ((guix licenses) #:prefix license:)
+  #:use-module (guix build emacs-build-system)
+  #:use-module (guix build-system gnu)
+  #:use-module (guix build-system meson)
+  #:use-module (gnu services)
+  #:use-module (gnu services desktop)
+  #:use-module (gnu services sddm)
+  #:use-module (gnu services ssh)
+  #:use-module (gnu services xorg)
+  #:use-module (gnu services base)
+  #:use-module (gnu system)
+  #:use-module (gnu system accounts)
+  #:use-module (gnu system file-systems)
+  #:use-module (gnu system image)
+  #:use-module (gnu system keyboard)
+  #:use-module (gnu system nss)
+  #:use-module (gnu system shadow)
+  #:use-module (srfi srfi-26)
+  #:use-module (srfi srfi-1) ;for the remove function
+  #:export (quartz64-a-raw-image
+            quartz64-image-type
+            quartz64-desktop-raw-image))
+
+(define (python-extension-suffix python triplet)
+  "Determine the suffix for C extensions for PYTHON when compiled
+for TRIPLET."
+  ;; python uses strings like 'x86_64-linux-gnu' instead of
+  ;; 'x86_64-unknown-linux-gnu'.
+  (define normalised-system
+    (string-replace-substring triplet "-unknown-" "-"))
+  (define major.minor (version-major+minor (package-version python)))
+  (define majorminor (string-delete #\. major.minor))
+  (string-append
+    ;; If guix' python package used "--with-pydebug", a #\d would
+    ;; need to be added, likewise "--with-pymalloc" and "--with-wide-unicode"
+    ;; would require a #\m and #\u, see cpython's configure.ac.
+    ".cpython-" majorminor "-" normalised-system
+    (if (target-mingw? triplet)
+        ".dll"
+        ".so")))
+
+(define (correct-library-name-phase python name)
+  "Return a G-exp evaluating to a phase renaming the python extension NAME
+from what Meson thinks its name should be to what python expects its name
+to be.  NAME must not include the platform-specific suffix.  This can only
+be used when cross-compiling."
+  #~(lambda _
+      (define name #$name)
+      (define native-suffix
+        #$(python-extension-suffix python
+                                   (nix-system->gnu-triplet (%current-system))))
+      (define target-suffix
+        #$(python-extension-suffix python (%current-target-system)))
+      (define native-name
+        (string-append name native-suffix))
+      (define target-name
+        (string-append name target-suffix))
+      (rename-file native-name target-name)))
+
+(define gobject-introspection
+  (package
+    (name "gobject-introspection")
+    (version "1.66.1")
+    (source (origin
+             (method url-fetch)
+             (uri (string-append "mirror://gnome/sources/"
+                   "gobject-introspection/" (version-major+minor version)
+                   "/gobject-introspection-" version ".tar.xz"))
+             (sha256
+              (base32 "078n0q7b6z682mf4irclrksm73cyixq295mqnqifl9plwmgaai6x"))
+             (patches (search-patches
+                       "gobject-introspection-cc.patch"
+                       "gobject-introspection-girepository.patch"
+                       "gobject-introspection-absolute-shlib-path.patch"))))
+    (build-system meson-build-system)
+    (arguments
+     `(,@(if (%current-target-system)
+             `(#:configure-flags
+               '("-Dgi_cross_use_prebuilt_gi=true"
+                 ;; Building introspection data requires running binaries
+                 ;; for ‘host’ on ‘build’, so don't do that.
+                 ;;
+                 ;; TODO: it would be nice to have introspection data anyways
+                 ;; as discussed here: https://issues.guix.gnu.org/50201#60.
+                 "-Dbuild_introspection_data=false"))
+             '())
+       #:phases
+       ,#~
+       (modify-phases %standard-phases
+         #$@(if (%current-target-system)
+                ;; 'typelibs' is undefined.
+                `((add-after 'unpack 'set-typelibs
+                    (lambda _
+                      (substitute* "meson.build"
+		;			    (("python3") "python")
+                        (("\\bsources: typelibs\\b")
+                         "sources: []")))))
+                '())
+         (add-after 'unpack 'do-not-use-/usr/bin/env
+           (lambda _
+             (substitute* "tools/g-ir-tool-template.in"
+               (("#!@PYTHON_CMD@")
+                (string-append "#!" #$(this-package-input "python")
+				"/bin/python3")))))
+         #$@(if (%current-target-system)
+               ;; Meson gives python extensions an incorrect name, see
+               ;; <https://github.com/mesonbuild/meson/issues/7049>.
+                #~((add-after 'install 'rename-library
+                     #$(correct-library-name-phase
+                         (this-package-input "python")
+                         #~(string-append #$output
+                                          "/lib/gobject-introspection/giscanner"
+                                          "/_giscanner"))))
+                #~()))))
+	(native-inputs
+     (list `(,glib "bin")
+       pkg-config
+       bison
+       flex))
+    (inputs
+     (list ;,@(if (%current-target-system)
+             python
+             bison
+             flex
+       zlib))
+    (propagated-inputs
+     (list glib
+           ;; In practice, GIR users will need libffi when using
+           ;; gobject-introspection.
+           libffi))
+    (native-search-paths
+     (list
+      (search-path-specification
+       (variable "GI_TYPELIB_PATH")
+       (files '("lib/girepository-1.0")))))
+    (search-paths native-search-paths)
+    (synopsis "GObject introspection tools and libraries")
+    (description "GObject introspection is a middleware layer between
+C libraries (using GObject) and language bindings.  The C library can be scanned
+at compile time and generate metadata files, in addition to the actual native
+C library.  Then language bindings can read this metadata and automatically
+provide bindings to call into the C library.")
+    (home-page "https://wiki.gnome.org/Projects/GObjectIntrospection")
+    (license
+     (list
+      ;; For library.
+      license:lgpl2.0+
+      ;; For tools.
+      license:gpl2+))))
+;; Fails to cross-compile - rewrite using gexp
+(define-public slock
+  (package
+    (name "slock")
+    (version "1.4")
+    (source (origin
+              (method url-fetch)
+              (uri (string-append "https://dl.suckless.org/tools/slock-"
+                                  version ".tar.gz"))
+              (sha256
+               (base32
+                "0sif752303dg33f14k6pgwq2jp1hjyhqv6x4sy3sj281qvdljf5m"))))
+    (build-system gnu-build-system)
+    (arguments
+     (list #:tests? #f                      ; no tests
+       #:make-flags
+       #~(list (string-append "CC=" #$(cc-for-target))
+             (string-append "PREFIX=" #$output))
+       #:phases #~(modify-phases %standard-phases (delete 'configure))))
+    (inputs
+     (list libx11 libxext libxinerama libxrandr))
+    (home-page "https://tools.suckless.org/slock/")
+    (synopsis "Simple X session lock")
+    (description
+     "Simple X session lock with trivial feedback on password entry.")
+    (license license:x11)))
+
+(define quartz64a-desktop-os
+  (operating-system
+    (host-name "quartz64a")
+    (timezone "Europe/Prague")
+    (locale "en_US.utf8")
+
+    (bootloader (bootloader-configuration
+                 (bootloader u-boot-quartz64a-rk3566-bootloader)
+                 (targets '("/dev/vda"))))
+    (initrd-modules '())
+    (kernel linux-quartz64)
+    (file-systems (append (list
+	                      (file-system
+                          (device (file-system-label "EFI"))
+                          (mount-point "/boot/efi")
+                          (type "vfat"))
+                          (file-system
+                          (device (file-system-label "root"))
+                          (mount-point "/")
+                          (type "ext4")))
+                        %base-file-systems))
+
+    (swap-devices (list (swap-space
+                         (target "/run/swapfile"))))
+
+    (users (cons* (user-account
+                   (name "pine")
+                   (group "users")
+                   (supplementary-groups '("wheel" "netdev" "audio" "video"))
+				   (password (crypt "quartz64" "$6$abc"))
+                   (home-directory "/home/pine"))
+                  %base-user-accounts))
+
+  ;; Add GNOME desktop
+  (services 
+                (append (list (service mate-desktop-service-type)
+                              (service xfce-desktop-service-type)
+                              (service openssh-service-type)
+                              (service agetty-service-type
+                               (agetty-configuration
+                                (extra-options '("-L")) ; no carrier detect
+                                (baud-rate "1500000")
+                                (term "vt100")
+                                (tty "ttyS2"))))
+                        %desktop-services))
+
+    (packages (cons* nss-certs
+                     openssh
+                     gvfs
+                     %base-packages))
+
+    (name-service-switch %mdns-host-lookup-nss)))
+
+(define quartz64-image-type
+  (image-type
+   (name 'quartz-raw)
+   (constructor (lambda (os)
+                  (image
+				   (inherit
+                     (raw-with-offset-disk-image (* 32 (expt 2 20)))) ; 32MiB
+                   (operating-system os)
+                   (platform aarch64-linux))))))
+
+(define quartz64-desktop-raw-image
+  (image
+   (inherit
+    (os+platform->image quartz64a-desktop-os aarch64-linux
+                        #:type quartz64-image-type))
+   (name 'quartz-desktop-raw-image)))
+
+;; Return the default image.
+quartz64-desktop-raw-image
diff --git a/nongnu/system/images/quartz64a.scm b/nongnu/system/images/quartz64a.scm
new file mode 100644
index 0000000..5bf9bdf
--- /dev/null
+++ b/nongnu/system/images/quartz64a.scm
@@ -0,0 +1,110 @@
+;;; GNU Guix --- Functional package management for GNU
+;;; Copyright © 2020 Mathieu Othacehe <m.othacehe@gmail.com>
+;;;
+;;; This file is part of GNU Guix.
+;;;
+;;; GNU Guix is free software; you can redistribute it and/or modify it
+;;; under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation; either version 3 of the License, or (at
+;;; your option) any later version.
+;;;
+;;; GNU Guix is distributed in the hope that it will be useful, but
+;;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
+
+(define-module (nongnu system images quartz64a)
+  #:use-module (gnu bootloader)
+  #:use-module (gnu bootloader u-boot)
+  #:use-module (gnu image)
+  #:use-module (nongnu packages linux)
+  #:use-module (nongnu packages bootloaders)
+  #:use-module (guix platforms arm)
+  #:use-module (gnu packages certs)
+  #:use-module (gnu packages ssh)
+  #:use-module (gnu services)
+  #:use-module (gnu services avahi)
+  #:use-module (gnu services base)
+  #:use-module (gnu services desktop)
+  #:use-module (gnu services networking)
+  #:use-module (gnu services ssh)
+  #:use-module (gnu system)
+  #:use-module (gnu system accounts)
+  #:use-module (gnu system file-systems)
+  #:use-module (gnu system image)
+  #:use-module (gnu system nss)
+  #:use-module (gnu system shadow)
+  #:use-module (srfi srfi-26)
+  #:export (quartz64-a-raw-image
+            quartz64-image-type
+            quartz64-barebones-raw-image))
+
+(define quartz64-a-barebone-os
+  (operating-system
+    (host-name "viso")
+    (timezone "Europe/Prague")
+    (locale "en_US.utf8")
+
+    (bootloader (bootloader-configuration
+                 (bootloader u-boot-quartz64a-rk3566-bootloader)
+                 (targets '("/dev/vda"))))
+    (initrd-modules '())
+    (kernel linux-quartz64)
+    (file-systems (append (list
+                          (file-system
+                          (device (file-system-label "root"))
+                          (mount-point "/")
+                          (type "ext4")))
+                        %base-file-systems))
+
+    (swap-devices (list (swap-space
+                         (target "/run/swapfile"))))
+
+    (users (cons* (user-account
+                   (name "pine")
+                   (group "users")
+                   (supplementary-groups '("wheel" "netdev" "audio" "video"))
+				   (password (crypt "quartz64" "$6$abc"))
+                   (home-directory "/home/pine"))
+                  %base-user-accounts))
+
+    (services (append (list (service agetty-service-type
+                             (agetty-configuration
+                              (extra-options '("-L")) ; no carrier detect
+                              (baud-rate "1500000")
+                              (term "vt100")
+                              (tty "ttyS2")))
+                     (service avahi-service-type)
+					 (service dhcp-client-service-type)
+                     (service ntp-service-type)
+                              (service openssh-service-type))
+                    %base-services))
+
+    (packages (cons* nss-certs
+                     openssh
+                     %base-packages))
+
+    (name-service-switch %mdns-host-lookup-nss)))
+
+(define quartz64-image-type
+  (image-type
+   (name 'quartz-raw)
+   (constructor (lambda (os)
+                  (image
+				   (inherit
+                     (raw-with-offset-disk-image (* 32 (expt 2 20)))) ; 32MiB
+                   (operating-system os)
+                   (platform aarch64-linux))))))
+
+(define quartz64-barebones-raw-image
+  (image
+   (inherit
+    (os+platform->image quartz64-a-barebone-os aarch64-linux
+                        #:type quartz64-image-type))
+   (name 'quartz-barebones-raw-image)))
+
+;; Return the default image.
+quartz64-barebones-raw-image